DETAILED ACTION
This non-final action is responsive to communications: application filed on 03/06/2025.
Claims 1-20 are pending. Claim 1 is independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. D) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103. E) Per MPEP 2173.04, undue breadth of the claim may be addressed under different statutory provisions, depending on the reasons for concluding that the claim is too broad.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
3. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 03/06/2025. This IDS has been considered.
Specification Objections
4a. The Title is objected to because the title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
4b. Content of the disclosure “Background” section does not discuss any meaningful background info, problematic structures and problems to be solved and is objected to. 37 C.F.R. 1.71(b) requires, “The specification must set forth the precise invention for which a patent is solicited, in such manner as to distinguish it from other inventions and from what is old.” Applicant is reminded that helpful guidance, as to preparing an application disclosure, is provided in the MPEP under section 608. Notably, MPEP 608.01(c) provides exemplary use of the heading “Background of the Invention”.
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
6. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. Such omission is tantamount to omitting essential structural cooperative relationships of elements also. See MPEP § 2172.01. A claim which omits subject matter disclosed to be essential to the invention as described in the specification or in other statements of record may be rejected as failing to claim the subject matter that the inventor or a joint inventor regards as the invention (See In re Mayhew, 527 F.2d 1229, 188 USPQ 356 (CCPA 1976); In re Venezia, 530 F.2d 956, 189 USPQ 149 (CCPA 1976); and In re Collier, 397 F.2d 1003, 158 USPQ 266 (CCPA 1968)). Such essential matter may include missing elements (circuitry components essential for function), steps or necessary structural cooperative relationships of elements described by the applicant(s) as necessary to practice the invention. For claim 1, omitted elements, lack of structural co-operative relationships are described (highlighted) in association with the limitation:
“…a latch circuit array connected to the first sense amplifier and the second sense amplifier and configured to store the first read data, the first write data, the second read data, and the second write data.” Missing element is circuitry components and associated architecture of “latch circuit” as part of the device. Invention reduces area by making two sense amplifier modules share one latch circuit array, or by segregating latch circuitry so that multiple planes can use a common peripheral circuitry. See descriptions in para e.g., [0049], [0126] - [0129]. The shared latch structure stores both read and write data for the two planes. Additional switches or selectors control which plane is actively coupled to the latch circuit array and manages access. See e.g., para [0105], para [0128], para [0157]. Disclosed invention in specification correlates this arrangement to smaller chip size and lower manufacturing cost Overall arrangement of the apparatus is unclear and vague without the description of these features. In the manner latch circuit coupling is described in claim language can be interpreted in multiple different which does not require common sharing as disclosed in spec. Thus, the limitation is vague and ambiguous.
All dependent claims inclusive of Claims 1-20 are rejected under this category. See art rejection for the interpretation of the art rejected claims.
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
10. Claims 1-20 is/are rejected under 35 U.S.C. 103 as being obvious over TOKIWA (US 2017/0052737 A1), in view of Hsu et al (US 2024/0071433 A1).
Regarding independent claim 1, TOKIWA teaches a semiconductor memory device (Fig. 3: 110 memory “core module”), comprising:
a first plane of memory cell array (Fig. 3: PLN0. See para [0079]) including a first memory cell string (Fig. 3: nand string connected to BL0_0. See para [0082]) and a first bit line connected to the first memory cell string (Fig. 3: BL0_0);
a second plane of memory cell array (Fig. 3: PLN1. See para [0079]) including a second memory cell string (Fig. 3: nand string connected to BL0_1. See para [0082]) and a second bit line connected to the second memory cell string (Fig. 3: BL0_1);
a first sense amplifier (Fig. 3: 115_0 “sense amplifier”) connected to the first bit line (Fig. 3: BL0_0), and configured to perform sensing of first read data that are read from a memory cell in the first memory cell string via the first bit line (Fig. 3 string coupling and in context of para [0063]: reading. See also para [0094]) and apply voltages corresponding to first write data that are to be written to a memory cell in the first memory cell string, to the first bit line (Fig. 3 string coupling and in context of para [0063]: writing. See also para [0073]-para [0074]);
a second sense amplifier (Fig. 3: 115_1 “sense amplifier”) connected to the second bit line (Fig. 3: BL0_1), and configured to perform sensing of second read data that are read from a memory cell in the second memory cell string (Fig. 3 string coupling and in context of para [0063]: reading. See also para [0094]) and apply voltages corresponding to second write data that are to be written to a memory cell in the second memory cell string, to the second bit line (Fig. 3 string coupling and in context of para [0063]: writing. See also para [0073]-para [0074]); and
a latch circuit array (Fig. 3: 113 “sense unit” with ADL, BDL, XDL latches) connected to the first sense amplifier (Fig. 3: 115_0) and the second sense amplifier (Fig. 3: 115_1) and configured to store the first read data, the first write data, the second read data, and the second write data (Fig. 3 in context of para [0093]-para [0094]).
TOKIWA does not explicitly teach latch circuit array arrangement details and common latch component being shared by first sense amplifier and second send amplifier.
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Hsu teaches latch circuit array arrangement (Fig. 12: latches between multiple planes) and common latch component being shared by first sense amplifier of first plane and second send amplifier of second plane (Fig. 12, Fig. 14A: XDL data “latch” is shared by Plane 0 and Plane 2. See para [0090], para [0094]).
TOKIWA and Hsu are in the same field of endeavor of nand flash memory read/ write operation employing data latch functions and they are in analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Hsu’s data latch architecture and functionality into the apparatus of TOKIWA such that claimed device can be employed in order to improve read execution speed, and reduce area allowing “area-efficient” design in multi-plane memory structure (Hsu para [0031]).
Regarding claim 2, TOKIWA and Hsu teach the semiconductor memory device of claim 1. Hsu teaches wherein the first sense amplifier (Fig. 12, Fig. 14A: SA with plane 0), the second sense amplifier (Fig. 12, Fig. 14A: SA with plane 2), and the latch circuit array (Fig. 12, Fig. 14A: common XDL and additional latches) are arranged between the first plane of memory cell array (Fig. 12: Plane 0) and the second plane of memory cell array (Fig. 12: Plane 2) in a first direction (Fig. 12: y-direction. See similarity to instant claim application drawings fig. 3 or fig. 5).
Regarding claim 3, TOKIWA and Hsu teach the semiconductor memory device of claim 2. TOKIWA and Hsu teaches all the limitations of the claim except silent with respect to latch circuit arrangement “…latch circuit array is arranged between the first plane of memory cell array and the first sense amplifier in the first direction…”. However, it would have been obvious to one of ordinary skill in the art before the effective filing date to rearrange data latches so that they are located between plane and sense amplifier to facilitate fabrication process (allows fabrication of group of sense amplifier in a center region reducing probability of defect and mismatch), since it has been held that rearranging parts of an invention involves only routine skill in the art. See Under MPEP Section 2144.04.
Regarding claim 4, TOKIWA and Hsu teach the semiconductor memory device of claim 1. Hsu teaches further comprising: a first switch connected between the latch circuit array and the first sense amplifier (e.g., Fig. 14C: 1555/1552 with bottom latch circuit of Fig. 14A); and
a second switch connected between the latch circuit array and the second sense amplifier (e.g., Fig. 14C: 1555/ 1552 with top latch circuit of Fig. 14A).
Regarding claim 5, TOKIWA and Hsu teach the semiconductor memory device of claim 4. Hsu teaches further comprising: a control circuit (Fig. 3B: 311) configured to turn on the first switch and turn off the second switch (e.g., when read from single plane is performed) in response to receiving first address information indicating a location in the first plane of memory cell array (para [0101] in context of Fig. 12, Fig. 14A, Fig. 14C: e.g., 1555/1552 is turned on associated with addressed plane).
Regarding claim 6, TOKIWA and Hsu teach the semiconductor memory device of claim 5. Hsu teaches wherein the control circuit (Fig. 3B: 311) is further configured to turn off the first switch and turn on the second switch (e.g., when read from single plane is performed) in response to receiving second address information indicating a location in the second plane of memory cell array (para [0101] in context of Fig. 12, Fig. 14A, Fig. 14C: e.g., 1555/1552 is turned on associated with addressed plane).
Regarding claim 7, TOKIWA and Hsu teach the semiconductor memory device of claim 5. Hsu teaches wherein the latch circuit array includes a plurality of first latch circuits (Fig. 14A, Fig. 12: SDL-ADLs in lower plane), and a second latch circuit (Fig. 14A, Fig. 12: common XDL) connected to an input/output circuit (Fig. 14A, Fig. 12: common XDL), and
the plurality of first latch circuits (Fig. 14A, Fig. 12: SDL-ADLs in lower plane) is configured to receive the first write data and the second write data from the input/output circuit via the second latch circuit (para [0086], para [0092]: write data), and output the first read data and the second read data to the input/output circuit via the second latch circuit (para [0085], para [0092]: sense data).
Regarding claim 8, TOKIWA and Hsu teach the semiconductor memory device of claim 7. TOKIWA teaches wherein each of the first write data, the second write data, the first read data, and the second read data is multi-bit data (para [0098]-para [0102]: 2-bit data. Number of bits can be greater), and
each of the first latch circuits stores one bit of the first write data, one bit of the second write data, one bit of the first read data, and one bit of the second read data (Fig. 6 in context of para [0117], para [0129]).
Regarding claim 9, TOKIWA and Hsu teach the semiconductor memory device of claim 7. TOKIWA teaches wherein a number of the first latch circuits is equal to or greater than a maximum number of bits of data storable in each memory cell in the first plane of memory cell array and a maximum number of bits of data storable in each memory cell in the second plane of memory cell array (Fig. 6 in context of para [0098]-para [0102], para [0117], para [0129]: 2 latches are used for 2 bit data)
Regarding claim 10, TOKIWA and Hsu teach the semiconductor memory device of claim 7. Hsu teaches wherein a number of the first latch circuits is four or more (Fig. 12, Fig. 14A: SDL-ADL).
Regarding claim 11, TOKIWA and Hsu teach the semiconductor memory device of claim 1. Hsu teaches wherein the latch circuit array includes a first plurality of latch circuits (Fig. 14A, Fig. 12: SDL-ADLs in lower plane), a second plurality of latch circuits (Fig. 14A, Fig. 12: SDL-ADLs in upper plane), and a second latch circuit (Fig. 14A, Fig. 12: common XDL) connected (operably connected) to an input/output circuit (Fig. 14A, Fig. 12; 902), and
the semiconductor memory device further comprises:
a first switch (Fig. 14A, Fig. 14B: 1509/ 1503 associated with lower plane) connected between the first plurality of latch circuits (Fig. 12: SDL-ADL in lower plane), and the second latch circuit (Fig. 12: common XDL); and
a second switch (Fig. 14A, Fig. 14B: 1509/ 1503 associated with upper plane) connected between the second plurality of latch circuits (Fig. 12: SDL-ADL in upper plane) and the second latch circuit (Fig. 12: common XDL).
Regarding claim 12, TOKIWA and Hsu teach the semiconductor memory device of claim 11. Hsu teaches further comprising: a control circuit (Fig. 3B: 311) configured to turn on the first switch and turn off the second switch (e.g., when read from single plane is performed) in response to receiving first address information indicating a location in the first plane of memory cell array (para [0101] in context of Fig. 12, Fig. 14A, Fig. 14C: e.g., 1555/1552 is turned on associated with addressed plane).
Regarding claim 13, TOKIWA and Hsu teach the semiconductor memory device of claim 12. Hsu teaches wherein the control circuit (Fig. 3B: 311) is further configured to turn off the first switch and turn on the second switch (e.g., when read from single plane is performed) in response to receiving second address information indicating a location in the second plane of memory cell array (para [0101] in context of Fig. 12, Fig. 14A, Fig. 14C: e.g., 1555/1552 is turned on associated with addressed plane).
Regarding claim 14, TOKIWA and Hsu teach the semiconductor memory device of claim 11, wherein the first plurality of latch circuits is configured to receive the first write data from the input/output circuit via the second latch circuit, and output the first read data to the input/output circuit via the second latch circuit, and the second plurality of latch circuits is configured to receive the second write data from the input/output circuit via the second latch circuit, and output the second read data to the input/output circuit via the second latch circuit. (See claims 1-7 rejection analysis)
Regarding claim 15, TOKIWA and Hsu teach the semiconductor memory device of claim 14, wherein each of the first write data, the second write data, the first read data, and the second read data is multi-bit data, each of the first plurality of latch circuits stores one bit of the first write data and one bit of the first read data, and each of the second plurality of latch circuits stores one bit of the second write data and one bit of the second read data. (See claims 8-9 rejection analysis)
Regarding claim 16, TOKIWA and Hsu teach the semiconductor memory device of claim 1. Hsu teaches further comprising:
a third plane of memory cell array (Fig. 12: Plane 1) including a third memory cell string and a third bit line connected to the third memory cell string (in context of Fig. 4A-Fig. 6 and Fig. 12);
a fourth plane of memory cell array (Fig. 12: Plane 3) including a fourth memory cell string and a fourth bit line connected to the fourth memory cell string (in context of Fig. 4A-Fig. 6 and Fig. 12);
a third sense amplifier connected to the third bit line (Fig. 14A: SA applicable for Fig. 12: Plane 1), and configured to perform sensing of third read data that are read from a memory cell in the third memory cell string and apply voltages corresponding to third write data that are to be written to a memory cell in the third memory cell string, to the third bit line (Fig. 1-Fig. 6 and Fig. 12, Fig. 14A architecture and function);
a fourth sense amplifier connected to the fourth bit line (Fig. 14A: SA applicable for Fig. 12: Plane 3), and configured to perform sensing of fourth read data that are read from a memory cell in the fourth memory cell string and apply voltages corresponding to fourth write data that are to be written to a memory cell in the fourth memory cell string, to the fourth bit line (Fig. 1-Fig. 6 and Fig. 12, Fig. 14A architecture and function); and
a second latch circuit array (Fig. 12, Fig. 14A latches connected between plane 1, plane 3) connected to the third sense amplifier and the fourth sense amplifier (Fig. 12, Fig. 14A SA of plane 1, plane 3) and configured to store the third read data, the third write data, the fourth read data, and the fourth write data (Fig. 12, Fig. 14A in context of para [0084]).
Regarding claim 17, TOKIWA and Hsu teach the semiconductor memory device of claim 16. Hsu teaches wherein the third sense amplifier (Fig. 12, Fig. 14A: SA with plane 1), the fourth sense amplifier (Fig. 12, Fig. 14A : SA with plane 3), and the second latch circuit array (Fig. 12, Fig. 14A latches connected between plane 1, plane 3) are arranged between the third plane of memory cell array (Fig. 12, Fig. 14A: plane 1) and the fourth plane of memory cell array (Fig. 12, Fig. 14A: plane 3).
Regarding claim 18, TOKIWA and Hsu teach the semiconductor memory device of claim 16. TOKIWA teaches further comprising:
a fifth plane of memory cell array including a fifth memory cell string and a fifth bit line connected to the fifth memory cell string;
a sixth plane of memory cell array including a sixth memory cell string and a sixth bit line connected to the sixth memory cell string;
a fifth sense amplifier connected to the fifth bit line, and configured to perform sensing of fifth read data that are read from a memory cell in the fifth memory cell string and apply voltages corresponding to fifth write data that are to be written to a memory cell in the fifth memory cell string, to the fifth bit line;
a sixth sense amplifier connected to the sixth bit line, and configured to perform sensing of sixth read data that are read from a memory cell in the sixth memory cell string and apply voltages corresponding to sixth write data that are to be written to a memory cell in the sixth memory cell string, to the sixth bit line; and
a third latch circuit array connected to the fifth sense amplifier and the sixth sense amplifier and configured to store the fifth read data, the fifth write data, the sixth read data, and the sixth write data.
(Fig. 3 in context of para [0079], para [0080], para [0093], para [0094]: architecture supports third and fourth planes similar to PLN0, PLN1 and similar sense and latch architecture and thus the limitations are satisfied)
Regarding claim 19, TOKIWA and Hsu teach the semiconductor memory device of claim 18. Hsu teaches wherein the fifth sense amplifier, the sixth sense amplifier, and the third latch circuit array are arranged between the fifth plane of memory cell array and the sixth plane of memory cell array (See Fig. 12, Fig. 14A, para [0031]: supports “pairs of planes” and different number of planes. Thus, sense amp and latch connections are satisfied).
Regarding claim 20, TOKIWA and Hsu teach the semiconductor memory device of claim 18. TOKIWA and Hsu teach do not explicitly teach the limitations of this claim. However, it would have been obvious to one of ordinary skill in the art before the effective filing date to rearrange components so that the first sense amplifier, the second sense amplifier, and the latch circuit array are arranged between the first plane of memory cell array and the second plane of memory cell array in a first direction, the third sense amplifier, the fourth sense amplifier, and the second latch circuit array are arranged between the third plane of memory cell array and the fourth plane of memory cell array in the first direction, the fifth sense amplifier, the sixth sense amplifier, and the third latch circuit array are arranged between the fifth plane of memory cell array and the sixth plane of memory cell array in the first direction, the first, third, and fifth planes of memory cell array are arranged in a second direction, and the second, fourth, and sixth planes of memory cell array are arranged in the second direction. The arrangement would be amplifier to facilitate fabrication process (allows fabrication of group of sense amplifier in a center region reducing probability of defect and mismatch), since it has been held that rearranging parts of an invention involves only routine skill in the art. See Under MPEP Section 2144.04.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure: SHIMIZU (US 2022/0093174 A1): Fig. 1-Fig. 19 disclosure applicable for all claims. SATO (US 2021/0142833 A1): Fig. 2-Fig. 22 disclosure applicable for all claims. Piccardi et al. (US 10,796,773 B1) is applicable for all claims: prior art teaches a nonvolatile memory device (Fig. 3: 300 NAND memory device), comprising: a cell array (Fig. 3: 302 memory array) divided into a plurality of planes (Fig. 7: 304 “planes”; see col. 7, lines 6-12); a control circuit (Fig. 3: 318) configured to set up word line voltages of each of the plurality of planes to the word line voltage in response to an activated pseudo plane independent read mode setting (col. 8, lines 1-20: power modes to access and turn on word lines of first plane and second plane), wherein the control circuit, in response to receiving a multi-plane command (col. 8, lines 1-20: “…a synchronous command…a command to access multiple planes of the memory array in parallel…”), is configured to sequentially shift voltage setup times of selected word lines by a specified time delay (Fig. 5A: 516) corresponding to a number of the plurality of planes (Fig. 5A in context of col. 10, lines 20-54: see 504 applied to first plane and after 514 is applied to second plane with 516 delay), the planes in the plurality of planes being selected by the multi-plane command (“synchronous command”, see col. 8, liens 25-32; col. 8, lines 1-20).
Conclusion
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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