Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/06/2025, and 11/11/2025 are being considered by the examiner.
Claim Objections
Claims 3-4, 6, 10-11, 13, 17-18 and 20 are objected to because of the following informalities:
Claim 3, line 2, claim 6 line 6, Claim 10, line 2, Claim 13, line 7, Claim 17, line 4, Claim 20, line 8, recite “indices of the PCM rows”, it should be “the indices of the PCM rows”.
Any claim not specifically mentioned above, is objected due to its dependency on the objected claim.
Appropriate correction is required.
Claim Rejections – 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
[Claim 1] A method for decoding low-density parity check (LDPC) codes in a communication system, the method comprising:
(a) identifying a set of indices of variable nodes (VNs) having log-likelihood ratios (LLRs) greater than a threshold;
(b) dividing indices of parity check matrix (PCM) rows into subsets each including a same number of non-zero row elements at indices of punctured VNs;
(c) ordering the subsets of the indices of the PCM rows based on the number of non-zero row elements at the indices of the punctured VNs;
(d) generating a schedule based on the ordered subsets of the indices of the PCM rows; and
(e) performing layered LDPC decoding according to the schedule.
Claim 1 is ineligible. (Similarly claim 8 and 15)
Claim Interpretation: Under the broadest reasonable interpretation, the terms of the claim are presumed to have their plain meaning consistent with the specification as it would be interpreted by one of ordinary skill in the art. See MPEP 2111.
Step (a) recites “identifying a set of indices of variable nodes (VNs) having log-likelihood ratios (LLRs) greater than a threshold;” encompasses performing mathematical calculations supported by [0085] FIG. 7, the process 700 begins with identifying a set of indices of VNs whose corresponding LLRs, calculated based on channel observations, have amplitudes larger than a threshold (step 701).
Step (b) recites “dividing indices of parity check matrix (PCM) rows into subsets each including a same number of non-zero row elements at indices of punctured VNs;” encompasses mental choices or evaluations as evidenced by [0087].
Step (c) recites “ordering the subsets of the indices of the PCM rows based on the number of non-zero row elements at the indices of the punctured VNs;”which uses mathematical formulas or equations and mathematical calculations as evidenced by [0087] the subsets {ϕ.sup.(p):p=0,1, . . . , P} are sorted in an ascending order of the number of non-zero elements of rows at the indices of the punctured VNs; [0127] Divide the row indices into subsets and sort the subsets both based on row weight at the punctured VNs.
Step (d) recites “generating a schedule based on the ordered subsets of the indices of the PCM rows;” which encompasses mental choices or evaluations as evidenced by [0134] A schedule B is generated by ordering the row indices within each subset in an ascending order based on the row weight, without considering the elements at the indices of the shortening VNs and the identified indices (step 1104).
Step (e) recites “performing layered LDPC decoding according to the schedule;” which uses mathematical formulas or equations and mathematical calculations, supported by Fig.14, [0025], [0090].
Steps (a), (b), (c), (d) and (e) are all recited as being performed by a computer/processor (Claims 8 and 15). The recited computer/processor is recited at a high level of generality, i.e., as a generic computer performing generic computer functions.
Step 1: This part of the eligibility analysis evaluates whether the claim falls within any statutory category. See MPEP 2106.03. The claim recites a computer. The claim is directed to a physical device, which is a machine and/or manufacture, and falls within one of the statutory categories of invention. (Step 1: YES).
Step 2A, Prong One: This part of the eligibility analysis evaluates whether the claim recites a judicial exception. As explained in MPEP 2106.04, subsection II, a claim “recites” a judicial exception when the judicial exception is “set forth” or “described” in the claim.
As discussed above, the broadest reasonable interpretation of steps (a), (c), and (e), fall within the mathematical concepts groupings of abstract ideas, step (b), and (d) falls within the mental process groupings of abstract ideas because they cover concepts performed in the human mind, including observation, evaluation, judgment, and opinion. See MPEP 2106.04(a)(2), subsection III, therefore, claim 1 recites multiple abstract ideas, As steps (a), (c), and (e), and step (b), (d) fall within different groupings of abstract ideas (i.e., mathematical concepts and mental processes, respectively), these limitations are considered together as a single abstract idea for further analysis. (Step 2A, Prong One: YES).
Step 2A, Prong Two: This part of the eligibility analysis evaluates whether the claim as a whole integrates the recited judicial exception into a practical application of the exception or whether the claim is “directed to” the judicial exception. This evaluation is performed by (1) identifying whether there are any additional elements recited in the claim beyond the judicial exception, and (2) evaluating those additional elements individually and in combination to determine whether the claim as a whole integrates the exception into a practical application. See MPEP 2106.04(d).
The claim recites additional element of “a transceiver” (Claim 8), “an electronic device” (Claim 15), “a processor” (Claim 1, 8, 15), When determining whether a claim simply recites a judicial exception with the words “apply it” (or an equivalent), such as mere instructions to implement an abstract idea on a computer, examiners may consider: (1) whether the claim recites only the idea of a solution or outcome i.e., the claim fails to recite details of how a solution to a problem is accomplished; (2) whether the claim invokes computers or other machinery merely as a tool to perform an existing process; and (3) the particularity or generality of the application of the judicial exception. See MPEP 2106.05(f). Here, these circuits are used to generally apply the abstract idea (i.e., perform the mathematical calculation using the recited mathematical equation) without placing any limitation on how this is accomplished. The claim omits any details as to how these circuits solve a technical problem, and instead recites only the idea of a solution or outcome. Also, the claim invokes these circuits merely as a tool for making the recited mathematical calculation rather than purporting to improve the technology or a computer. See MPEP 2106.05(f). Therefore, the limitation represents no more than mere instructions to apply the judicial exception on a computer. It can also be viewed as nothing more than an attempt to generally link the use of the judicial exception to the technological environment of computers.
The recited generic “a transceiver” (Claim 8), “an electronic device” (Claim 15), “a processor” (Claim 1, 8, 15), merely add a generic computer/circuit component to perform the steps and therefore fails to provide an improvement to the technology or technical field. See MPEP 2106.05(a). Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application (Step 2A, Prong Two: NO), and the claim is directed to the judicial exception. (Step 2A: YES).
Step 2B: This part of the eligibility analysis evaluates whether the claim as a whole amounts to significantly more than the recited exception i.e., whether any additional element, or combination of additional elements, adds an inventive concept to the claim. See MPEP 2106.05.
As explained with respect to Step 2A, Prong Two, there are additional elements. The additional element of “a transceiver” (Claim 8), “an electronic device” (Claim 15), “a processor” (Claim 1, 8, 15) in limitations is at best mere instructions to “apply” the abstract ideas, which cannot provide an inventive concept. See MPEP 2106.05(f).
As discussed in Step 2A, Prong Two above, the recitation of “a transceiver” (Claim 8), “an electronic device” (Claim 15), “a processor” (Claim 1, 8, 15) to perform limitations (a), (b), (c), (d) and (e) amounts to no more than mere instructions to apply the exception using a generic computer component. Even when considered in combination, these additional elements represent mere instructions to implement an abstract idea or other exception on a computer and insignificant extra-solution activity, which do not provide an inventive concept. (Step 2B: NO).
Claims 2, recites additional elements “wherein the subsets of the indices of the PCM rows are ordered in ascending number of the non-zero row elements at the indices of the punctured VNs.”, which further details ordering, i.e. Mathematical Concepts.
Claim 3, recites additional elements “further comprising: for each of the subsets of the indices of the PCM rows, ordering indices of the PCM rows within the respective subset based on row weight, excluding row elements at the identified set of indices of the VNs.” which further details ordering, i.e. Mathematical Concepts.
Claim 4, recites additional elements “wherein the row weight for each of the PCM rows accounts for shortening VNs and high LLR VNs.”, i.e. recites additional mathematical formulas or equations - Mathematical Concepts.
Claim 5, recites additional elements “where performing layered LDPC decoding according to the schedule further comprises: processing check nodes (CNs) in an order according to the schedule in each decoding iteration.” which further details decoding, i.e. Mathematical Concepts.
Claim 6, recites additional elements “wherein generating a schedule based on the ordered subsets of the indices of the PCM rows comprises generating a first schedule and a second schedule, and wherein ordering the subsets of the indices of the PCM rows based on the number of non-zero row elements at the indices of the punctured VNs forms the first schedule, …… ordering indices of the PCM rows on row weight, excluding row elements at the identified set of indices of the VNs, to form the second schedule, wherein performing layered LDPC decoding according to the schedule comprises: processing check nodes (CNs) in an order according to the second schedule in initial decoding iterations, and then in an order according to the first schedule in remaining decoding iterations.” which further details ordering, generating a schedule, decoding, i.e. Mathematical Concepts.
Claim 7, recites additional elements “performing decoding iterations according to a desired block error rate (BLER) is achieved.” which further details decoding, i.e. Mathematical Concepts.
Claims 9-13 and 16-20 are the apparatus/A non-transitory machine readable medium claim of claim 2-6, Claim 14 is the apparatus claim of claim 7, thus the same 101 rejection analysis as corresponding claims 1-7 are applied.
Examiner Notes
There are no art rejection for Claims 1-20, however they are under 101 rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
SHIRAZINIA et al., US 20190372593, “Systems And Methods For Fast Layered Decoding For Low-Density Parity-Check (LDPC) Codes”
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/RONG TANG/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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