Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application has been examined. Claims 1-20 are pending.
The Group and/or Art Unit location of your application in the PTO has changed. To aid in correlating any papers for this application, all further correspondence regarding this application should be directed to Group Art Unit 2175.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of the second paragraph of 35 U.S.C. 112:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 8, and 13 are rejected under 35 U.S.C. 112(b) as indefinite:
• Claim 4: recites “the volatile memory,” but claim 4 depends from claim 1, which does not introduce a volatile memory (the volatile memory is first introduced in claim 2). There is insufficient antecedent basis for “the volatile memory.” Suggest depending claim 4 from claim 2, or reciting “a volatile memory.”
• Claim 8: recites “the storage memory,” but claim 1 recites “a non-volatile memory” and does not introduce “storage memory.” There is insufficient antecedent basis for “the storage memory.” Suggest conforming the term to “the non-volatile memory.”
• Claim 13: recites “The method of any of claim 12,” which is grammatically improper for a claim depending on a single claim, rendering the scope unclear. Suggest “The method of claim 12.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art t which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-12, 14-17, and 20 are rejected under 35 U.S.C. 103 as unpatentable over Wilson (“Wilson”) (US 8,230,257) in view of Mardikar (“Mardikar”) (US 8,630,907).
In order to expedite and avoid piecemeal prosecution, the following rejection is made to the extent that the claims are understood, by considering those elements which are understood and interpreting their function in a manner which is consistent with the recited goals of the claims, and then applying the best available art.
The examiner relies on the entire teachings of Wilson and Mardikar references; the applicant should carefully consider the entire teachings of the above-mentioned references to better understand the examiner’s position.
In regard to claim 1, Wilson teaches a memory controller configured to store the transaction data in a non-volatile memory (as shown in Fig. 1, which is reproduced below for ease of reference and convenience, Wilson discloses a memory controller (110/112/114) that facilitates access to stored data and, in response to primary-power problems, writes the cached (volatile) data to a non-volatile memory (116/118/120) that is not subject to data loss in the absence of primary power (FIG. 1; Summary; claim 1);
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a voltage monitor configured to monitor an input voltage from an external power source to identify a loss in power and provide an alert to the processor indicating the loss in power (in the primary power is monitored (FIG. 2, block 208) and a loss is identified by “determining that the voltage level of the primary power source has fallen below a threshold level” (block 210); the secondary switch is enabled “in response to detecting a voltage drop in the primary power” (claims 7-8), and the memory system is signaled to perform the write. Combined with Mardikar’s processor 212 for the recited alert-to-processor) and
provide an alert to the processor indicating the loss in power (in a secondary/backup power source (100/304/408) provides power to the operating power circuit which powers the memory controllers in response to the primary-power problem; the backup source is a capacitor (FIG. 3, element 304) and, in FIG. 4, col. 6:62-67: power-providing modules 404 “each contain a supercapacitor”) and
a supercapacitor configured to provide power to the processor and memory controller in response to the alert (in a secondary/backup power source (100/304/408) provides power to the operating power circuit which powers the memory controllers in response to the primary-power problem; the backup source is a capacitor (FIG. 3, element 304) and, in FIG. 4; col. 6:62-67, power-providing modules 404 “each contain a supercapacitor”) wherein the supercapacitor provides power for an amount of time sufficient to store the transaction data in the non-volatile memory (in the backup source “provides temporary power to the memory system for a time sufficiently long to complete the write procedure”; claim 6 recites a capacitor storing “a peak charge sufficient to provide substantially all power … for a time period sufficiently long to complete pending writes”). But Wilson does not expressly disclose a point-of-sale (POS) device, comprising: an input device configured to receive transaction data; a processor configured to process the transaction data. In the same field of endeavor, Mardikar expressly teaches a point-of-sale (POS) device, comprising: an input device configured to receive transaction data (as shown in Fig. 2, which is reproduced below for ease of reference and convenience, Mardikar discloses a point-of-sale (POS) device 104 (FIG. 2; “components inside a terminal or point of sale (POS) device”). Mardikar further teaches the input 206 of POS 104 “adapted to receive data such as account information necessary to support a transaction” e.g., a keypad/keyboard for entering a PAN and money amount, or a magnetic-stripe/RFID/NFC reader (FIG. 2);
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a processor configured to process the transaction data (in Mardikar, processor 212 of POS 104, communicatively connected and adapted to control the components and process the transaction information (FIG. 2). Mardikar discloses a POS device 104 having an input 206 that receives transaction data (account information such as a PAN and money amount) and a processor 212 that processes/controls the transaction (FIG. 2). It would have been obvious to one of ordinary skill in the art before the effective filing date to apply Wilson’s supercapacitor-backed power-loss data-protection (detect voltage drop [Wingdings font/0xE0] hold up the memory system with a supercapacitor [Wingdings font/0xE0] write volatile/cached data to non-volatile memory [Wingdings font/0xE0] safely power down) to the POS device of Mardikar. Both are in the field of processor-based devices that write critical data to memory, and Wilson expressly addresses the very problem the POS art faces loss/corruption of cached data on unexpected power loss. Combining them predictably prevents loss or corruption of transaction data on a POS power failure the applicant’s own stated objective and amounts to applying a known power-loss-protection mechanism (Wilson) to a known POS device of Mardikar to yield the expected result (KSR; MPEP 2143(A)/(G)), with a reasonable expectation of success because Wilson’s mechanism operates on any volatile-to-non-volatile write.
In regard to claim 2, Wilson teaches further: a volatile memory, wherein the processor causes the transaction data to be moved from the volatile memory to the non-volatile memory (in Wilson: memory controller “writes the cached data” from volatile memory to non-volatile memory 116/118/120 (Summary; FIG. 2, block 216).
In regard to claims 3 and 14, Wilson teaches wherein the transaction data includes transaction data which was being written to the non-volatile memory when the loss in power was identified (in Wilson, “complete pending writes to the solid-state memory circuit” in response to primary-power problems (claim 1; Summary).
In regard to claims 4 and 15, Wilson teaches wherein the transaction data includes cached transaction data in the volatile memory (in Wilson: the memory “caches data in volatile memory” and that cached data is written out on power loss (Summary). (See §112(b) as to claim 4 antecedent basis).
In regard to claims 5 and 16, Wilson teaches wherein the processor, in response to the alert indicating the loss in power, shuts down subsystems of the POS device to conserve the power provided by the supercapacitor (in Wilson configures the system for power-removal and safely powers down. To the extent not express, it is well known and conventional to shut down non-essential subsystems during a backup-powered graceful shutdown to conserve limited backup energy for the data-save operation (Official Notice; MPEP 2144.03). Motivation: extend the hold-up time available for the write).
In regard to claims 6 and 17, even though Wilson or Mardikar does not expressly teach a display, wherein shutting down the subsystems of the POS device includes shutting down the display, however the display is a notoriously well-known, high-draw POS subsystem; shutting it down to conserve backup power is a conventional expedient (Official Notice).
In regard to claim 8, Wilson teaches wherein the processor, in response to the transaction data being stored in the storage memory during the loss in power, shuts down the POS device (in Wilson: after the writing and other functionality are completed (block 218), “the device can then be safely powered down” (FIG. 2, block 224)).
In regard to claims 9 and 12-13, Wilson teaches wherein the voltage monitor identifies the loss in power by determining that the input voltage has dropped below a predetermined threshold (in Wilson: loss identified by “determining that the voltage level of the primary power source has fallen below a threshold level”).
In regard to claims 10 and 20, Wilson teaches wherein the transaction data is stored in the non-volatile memory within 500 ms of the voltage monitor identifying the loss in power (in Wilson, sizes the backup source to hold up the system “for a time sufficiently long to complete the write.” Selecting a specific completion window (e.g., 500 ms) is an obvious design choice / optimization of a result-effective variable (backup hold-up time vs. supercapacitor size). In re Aller, 220 F.2d 454 (C.C.P.A. 1955).
Claim 11 (method) recites the same operative limitations as system claim 1. Wilson further teaches in response to the transaction data being written to the non-volatile memory, automatically shutting down, using the processor, the POS device (in Wilson, after the writing and other functionality are completed (block 218), “the device can then be safely powered down” (FIG. 2, block 224)). The change in claim format from system to method does not confer patentability where the underlying operations are identical to those taught by the applied references. See MPEP § 2114; In re Bernhart, 417 F.2d 1395 (CCPA 1969). The element-by-element mapping set forth for claim 1 applies with equal force to claim 11.
In regard to claim 19, even though Wilson or Mardikar does not expressly teaches: making, by the processor, a power off API call to the subsystems of the POS device however, by issuing a power-off API/command call to shut down subsystems is a conventional operating-system mechanism (Official Notice).
If Applicant traverses any statement of Official Notice, documentary evidence will be provided in the next action (MPEP 2144.03(C)).
Examiner's note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Allowable Subject Matter
Claims 7 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an Examiner's statement of reasons for the indication of allowable subject matter:
Claims 7 and 18 recite shutting down the subsystems of the POS device “directly from a kernel of an operating system running on the processor.” Neither Wilson nor Mardikar teaches performing the subsystem shutdown from kernel space (as opposed to user space) to achieve a faster shutdown that conserves the limited supercapacitor energy. This kernel-space shutdown is the applicant’s asserted point of novelty and is not fairly taught or suggested by the applied art. (Examiner to confirm no additional prior art teaches kernel-space power-off of subsystems in a backup-powered shutdown before indicating allowability).
Conclusion
Claims 1-6, 8-17, 19-20 are rejected. Claims 7 and 18 are objected.
The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure.
Stenfort et al., US 9,383,795, teach storage device power-failure infrastructure; capacitor backup, save cache to non-volatile memory on power loss.
Cagno et al., US 8,093,868, teach supercapacitor holds up voltage while data is saved from volatile memory to non-volatile storage on power loss (SSD context).
Portman et al., US 6,496,939, teach super-capacitors provide backup on loss of external power; automatically transfer all data from volatile to non-volatile memory, then shut down.
Ekanayake et al., US 11,209,883, teach supercapacitor powers CPU and memory for a few seconds after power loss to enable a graceful shutdown; power-off detector.
Spiers et al., US 2006/0080515, teach capacitor/battery backup; on power interruption, move data from backup volatile memory to non-volatile memory.
Alcom et al., US 10,198,320, teach power-loss protection.
Beatly et al., US 9,704,355, teach secure point-of-sale terminal (POS device context; IDC/MUX/secure processor/applications processor).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Raymond Phan, whose telephone number is (571) 272-3630. The examiner can normally be reached on Monday-Friday from 6:30AM- 3:00PM. The Group Fax No. (571) 273-8300.
Communications via Internet e-mail regarding this application, other than those under 35 U.S.C. 132 or which otherwise require a signature, may be used by the applicant and should be addressed to [raymond.phan@uspto.gov].
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 central telephone number is (571) 272-2100.
/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175
Prosecution Insights