DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/07/2025 has been considered by the examiner. The submission is in compliance with the provisions of 37 CFR 1.97.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 2, 4 – 5, 8 – 10, 14 – 15, and 18 – 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by MASHINO (US PgPub No. 20090290317).
Regarding claim 1, MASHINO teaches an electronic device (paragraph 0019; a semiconductor device) comprising: a circuit device having a specific region (paragraphs 0019 – 0021; printed circuit board) comprising: two conductors formed on a surface of the circuit device to be spaced apart from each other by a first distance in a first direction and to have substantially equal widths in the first direction (figure 3 and 10 – 17 items 25 and 26); and at least two solderless portions arranged to be spaced apart from each other by a second distance in a second direction intersecting the first direction and to intersect the two conductors (figures 10 – 17 items 22, 22a, 36, and/or 105); and an electronic component comprising two electrodes soldered to the two conductors, respectively, between the at least two solderless portions (figures 3 and 10 – 17 items 28 and 29).
Regarding claim 2, as mentioned above in the discussion of claim 1, MASHINO teaches all of the limitations of the parent claim. Additionally, MASHINO teaches wherein the circuit device is a three-dimensional circuit device (figure 3 and 10 – 17; three-dimensional circuit device), the two conductors extend substantially parallel to each other in the second direction orthogonal to the first direction, and the at least two solderless portions extend substantially parallel to each other in the first direction (figure 3 and 10 – 17 items 25 and 26 also figures 10 – 17 items 22, 22a, and 105).
Regarding claim 4, as mentioned above in the discussion of claim 1, MASHINO teaches all of the limitations of the parent claim. Additionally, MASHINO teaches wherein the at least two solderless portions have substantially equal widths in the second direction (figures 10 – 17 items 22, 22a, 36, and/or 105; at least two solderless portions have substantially equal widths in the second direction).
Regarding claim 5, as mentioned above in the discussion of claim 1, MASHINO teaches all of the limitations of the parent claim. Additionally, MASHINO teaches wherein the at least two solderless portions have different widths in the second direction (figures 10 – 17 items 22, 22a, 36, and/or 105; at least two solderless portions have different widths in the second direction).
Regarding claim 8, as mentioned above in the discussion of claim 1, MASHINO teaches all of the limitations of the parent claim. Additionally, MASHINO teaches wherein the electronic component comprises a capacitor (paragraph 0048; plurality of capacitors 28 and 29).
Regarding claim 9, as mentioned above in the discussion of claim 1, MASHINO teaches all of the limitations of the parent claim. Additionally, MASHINO teaches wherein the circuit device is a molded interconnect device (paragraph 0048; multi-level interconnection structure).
Regarding claim 10, as mentioned above in the discussion of claim 1, MASHINO teaches all of the limitations of the parent claim. Additionally, MASHINO teaches wherein the at least two solderless portions are two line-shaped resist portions (figures 10 – 17 items 22, 22a, 36, and/or 105).
Regarding claim 14, as mentioned above in the discussion of claim 1, MASHINO teaches all of the limitations of the parent claim. Additionally, MASHINO teaches an additional electronic component (figures 10 – 17; item 24), wherein the electronic component and the additional electronic component have different sizes (figures 10 – 17; item 24 vs items 28 and 29).
Regarding claim 15, as mentioned above in the discussion of claim 1, MASHINO teaches all of the limitations of the parent claim. Additionally, MASHINO teaches wherein each solderless portion extends across the two conductors from a first end to a second end in the first direction, the first end and the second end of each solderless portion being positioned outside the two conductors in the first direction (figures 10 – 17 items 22, 22a, 36, and/or 105).
Regarding claim 18, MASHINO teaches a manufacturing method for an electronic device (paragraph 0019; a semiconductor device), comprising: fabricating a circuit device (paragraphs 0019 – 0021; printed circuit board) by: forming two conductors in a specific region on a surface of the circuit device, the two conductors being arranged to be spaced apart from each other by a first distance in a first direction and to have substantially equal widths in the first direction (figure 3 and 10 – 17 items 25 and 26); and forming at least two solderless portions in the specific region, the at least two solderless portions being arranged to be spaced apart from each other by a second distance in a second direction intersecting the first direction and to intersect the two conductors (figures 10 – 17 items 22, 22a, 36, and/or 105); and soldering two electrodes of an electronic component to the two conductors, respectively, between the at least two solderless portions formed in the specific region of the circuit device (figures 3 and 10 – 17 items 28 and 29).
Regarding claim 19, as mentioned above in the discussion of claim 18, MASHINO teaches all of the limitations of the parent claim. Additionally, MASHINO teaches placing two resist portions using a dispenser, thereby forming the at least two solderless portions (figures 10 – 17 items 22, 22a, 36, and/or 105).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11 – 13, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over MASHINO (US PgPub No. 20090290317) in view of NAKAYAMA (US PgPub No. 20140264697).
Regarding claim 11, as mentioned above in the discussion of claim 1, MASHINO teaches all of the limitations of the parent claim.
Additionally, MASHINO teaches each of the at least two solderless portions has a region without the gold plating layer on the outer surface of a corresponding one of the two conductors (figures 10 – 17 items 22, 22a, 36, and/or 105 on outer surface of figure 3 and 10 – 17 items 25 and 26).
However, MASHINO fails to teach wherein each of the two conductors comprises a gold plating layer applied on an outer surface of each conductor. NAKAYAMA, on the other hand teaches gold plating layer applied on an outer surface.
More specifically, NAKAYAMA teaches gold plating layer applied on an outer surface (paragraph 0073).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to incorporate the teachings of NAKAYAMA with the teachings of MASHINO to have a system of improved durability using gold plating, thereby improving the system of MASHINO.
Regarding claim 12, as mentioned above in the discussion of claim 1, MASHINO teaches all of the limitations of the parent claim.
However, MASHINO fails to teach a camera unit mounted on the circuit device. NAKAYAMA, on the other hand teaches a camera unit mounted on the circuit device.
More specifically, NAKAYAMA teaches a camera unit mounted on the circuit device (abstract and paragraph 3 and figures 11 - 13).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to incorporate the teachings of NAKAYAMA with the teachings of MASHINO to have a system including image pickup capability, thereby improving the system of MASHINO.
Regarding claim 13, as mentioned above in the discussion of claim 12, MASHINO in view of NAKAYAMA teach all of the limitations of the parent claim.
Additionally, NAKAYAMA teaches wherein the circuit device comprises: a first surface on which the camera unit is mounted (figures 11 – 13; to the left of item 29); and a second surface opposite to the first surface, the second surface having the specific region (figures 11 – 13; to the right of item 50).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to incorporate the teachings of NAKAYAMA with the teachings of MASHINO to have a system including image pickup capability, thereby improving the system of MASHINO.
Regarding claim 17, as mentioned above in the discussion of claim 12, MASHINO in view of NAKAYAMA teach all of the limitations of the parent claim.
Additionally, NAKAYAMA teaches a endoscope (paragraph 0064) comprising: an insertion portion configured to be inserted into a subject (figure 13 and paragraph 0064; image pickup unit portion); and the electronic device according to claim 12 (please see discussion of claim 12 above), the electronic device being disposed in the insertion portion (figure 13 and paragraph 0064; image pickup unit portion).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to incorporate the teachings of NAKAYAMA with the teachings of MASHINO to have a system including image pickup capability, thereby improving the system of MASHINO.
Regarding claim 20, as mentioned above in the discussion of claim 18, MASHINO teaches all of the limitations of the parent claim.
Additionally, MASHINO teaches removing the gold plating layers on the two conductors, thereby forming the at least two solderless portions (figures 10 – 17 items 22, 22a, 36, and/or 105 on outer surface of figure 3 and 10 – 17 items 25 and 26).
However, MASHINO fails to teach applying a gold plating layer on an outer surface of each of the two conductors. NAKAYAMA, on the other hand teaches applying a gold plating layer on an outer surface.
More specifically, NAKAYAMA teaches applying a gold plating layer on an outer surface (paragraph 0073).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to incorporate the teachings of NAKAYAMA with the teachings of MASHINO to have a system of improved durability using gold plating, thereby improving the system of MASHINO.
Allowable Subject Matter
Claims 3, 6 – 7, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The following is a statement of reasons for the indication of allowable subject matter for claim 3: “wherein an angle between the two conductors is less than 10 degrees, the widths of the two conductors are within a range of 90 % to 110 % of an average value of the widths of the two conductors, and an angle between the at least two solderless portions is less than 10 degrees” in combination with the other limitations in the claim and the parent claim is not discussed or suggested in any of the prior art that was searched.
The following is a statement of reasons for the indication of allowable subject matter for claim 6: “wherein the widths of the two conductors are greater than 70 % but less than 130 % of the first distance, and the first distance is greater than 100 % but less than 180 % of the second distance” in combination with the other limitations in the claim and the parent claim is not discussed or suggested in any of the prior art that was searched.
The following is a statement of reasons for the indication of allowable subject matter for claim 7: “wherein the first distance is greater than 0.16 mm but less than 0.30 mm, the widths of the two conductors are greater than 0.12 mm but less than 0.35 mm, and the second distance is greater than 0.20 mm but less than 0.40 mm” in combination with the other limitations in the claim and the parent claim is not discussed or suggested in any of the prior art that was searched.
The following is a statement of reasons for the indication of allowable subject matter for claim 16: “wherein the two conductors comprise: a first conductor; and a second conductor spaced apart from the first conductor by the first distance in the first direction, the at least two solderless portions comprise: a first solderless portion positioned on the first conductor; a second solderless portion positioned on the first conductor and spaced apart from the first solderless portion by the second distance in the second direction; a third solderless portion positioned on the second conductor; a fourth solderless portion positioned on the second conductor and spaced apart from the third solderless portion by the second distance in the second direction, and the two electrodes of the electronic component comprise: a first electrode soldered to the first conductor between the first solderless portion and the second solderless portion; and a second electrode soldered to the second conductor between the third solderless portion and the fourth solderless portion” in combination with the other limitations in the claim and the parent claim is not discussed or suggested in any of the prior art that was searched.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
ODA (US PgPub No. 20100252316) teaches a system with electronic components.
NAGAMIZU (US PgPub No. 20100309553) teaches a system with electronic components.
DRESHER (US PgPub No. 20140051927) teaches a system with electronic components.
SHIMOHATA (US PgPub No. 20200337539) teaches a system with electronic components.
MAEDA (US PgPub No. 20230369180) teaches a system with electronic components.
NAKANO (US PgPub No. 20240008716) teaches a system with electronic components.
Kodama (US patent No. 11957306) teaches a system with electronic components.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Usman A Khan whose telephone number is (571)270-1131. The examiner can normally be reached on M - Th 5:30 AM - 2 PM, F 5:30 AM - Noon.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sinh Tran can be reached on (571)272-7564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Usman Khan
/USMAN A KHAN/Primary Examiner, Art Unit 2637
06/29/2026
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