Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending in this action.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/25/2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 12301359. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following:
Instant Application
US 12301359
As per claim 1:
A device, comprising:
a processor;
a memory communicatively coupled to the processor; and
a transmission logic, configured to:
receive a bitstream corresponding to a data packet;
detect an interruption;
generate an intra-packet word based on the interruption;
insert the intra-packet word; and
transmit a signal indicative of the intra-packet word.
As per claim 9:
transmission logic …. to encode … the intra-packet word ….
As per claim 1:
A device, comprising:
a processor;
a memory communicatively coupled to the processor; and
a transmission logic, configured to:
receive a bitstream corresponding to a data packet;
detect an interruption in a reception of the bitstream;
generate an intra-packet idle word based on the interruption;
encode the intra-packet idle word to generate an encoded intra-packet idle word; and
transmit a physical idle signal indicative of the encoded intra-packet idle word.
encode the intra-packet idle word …
As per claim 13:
A device, comprising:
a processor;
a memory communicatively coupled to the processor; and
a reception logic, configured to:
initiate a receive state;
receive a first data signal configured
to retrieve a first part of a data packet;
receive an idle signal;
retrieve an intra-packet word;
maintain the receive state based on the intra-packet word;
receive a second data signal configured to retrieve a second part of the data packet; and
retrieve the data packet based on at least the first part of the data packet and the second part of the data packet.
As per claim 13:
A device, comprising:
a processor;
a memory communicatively coupled to the processor; and
a reception logic, configured to:
initiate a receive state;
receive a first physical data signal;
…
to retrieve a first part of a data packet;
receive a physical idle signal; …
retrieve an intra-packet idle word;
maintain the receive state based on the intra-packet idle word;
receive a second physical data … to retrieve a second part of the data packet; and
retrieve the data packet based on the first part of the data packet and the second part of the data packet.
As per claim 15:
A method, comprising:
receiving a bitstream corresponding to a data packet;
detecting an interruption in a reception of the bitstream;
generating an intra-packet word based on the interruption; and
transmitting an idle signal indicative of the intra-packet word.
As per claim 19:
encoding the data packet based onthe encoding standard.
As per claim 15:
A method, comprising:
receiving a bitstream corresponding to a data packet;
detecting an interruption in a reception of the bitstream;
generating an intra-packet idle word based on the interruption;
encoding the intra-packet idle word for generating an encoded intra-packet idle word; and
transmitting a physical idle signal indicative of the encoded intra-packet idle word.
encoding the intra-packet idle word …
One of ordinary skill in the art would clearly recognize independent claims of current application is an obvious variation of the claimed subject matter of independent claims of US Patent 12301359. The primary difference of the current application is that it has fewer requirements than US Patent 12301359.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
In analyzing under step 1, is the claim to a process, machine manufacture or composition of matter? Yes.
In analyzing under step 2A Prong One, Does the claim recite an abstract idea law of nature or natural phenomenon? Yes.
The claim(s) 1 and 15 recite(s) the abstract limitations such as “receiving a bitstream corresponding to a data packet; detecting an interruption in a reception of the bitstream; generating an intra-packet word based on the interruption; and transmitting an idle signal indicative of the intra-packet word”
Claims 1 and 15 are a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mental processes but for the recitation of generic computer such as “a device, comprising: a processor; a memory communicatively coupled to the processor; and a reception logic, configured to:” (see claim 1).
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation under mental processes but for the recitation of generic computer components and software module, then it falls within the “Mental Processes” grouping of abstract ideas.
The mental process with the generic processor can receive a bitstream of a data packet, detect an interruption, generate a data word; and transmit/output the generated data word”
Claims 2 and 16 recite the abstract limitation such as “storing a configurable threshold value”. The mental process can store a threshold value.
Claim 6 recite the abstract limitation such as “word includes a …bit sequence” The mental process can generate a word including a bit sequence.
Claim 7 recite the abstract limitation such as “select a …bit sequence for …word” The mental process can generate/select a bit sequence for the word.
Other dependent claims do not recite limitations that would overcome abstract rejection.
Accordingly, the claim recites an abstract limitation.
The claim(s) 13 recite(s) the abstract limitations such as “initiate a receive state; receive a first data signal configured to retrieve a first part of a data packet; receive an idle signal; retrieve an intra-packet word; maintain the receive state based on the intra-packet word; receive a second data signal configured to retrieve a second part of the data packet; and retrieve the data packet based on at least the first part of the data packet and the second part of the data packet”
The claim(s) 14 recite(s) the abstract limitations such as “receive an error signal after receiving the first data signal; and discard the first part of the data packet based on the error signal”
Claims 13-14 are a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mental processes but for the recitation of generic computer processor such as “a device, comprising: a processor; a memory communicatively coupled to the processor; and a reception logic, configured to:” (see claim 13). If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation under mental processes but for the recitation of generic computer components and software module, then it falls within the “Mental Processes” grouping of abstract ideas.
The mental process with the generic processor can initiate a state to receive input data and afterward the mental process can receive first data signal, retrieve a first part of a data packet, receive an idle signal, retrieve an intra-packet word” and maintain ; maintain a state to receive more input data and afterward to receive a second data signal, to retrieve a second part of the data packet and retrieve the data packet” and “receive an error signal and discard data”
Accordingly, the claim recites an abstract limitation.
This judicial exception is not integrated into a practical application under Step 2A Prong 2. The recited steps of "receiving input…" (see claims 13-14 above) are extra-solution activity to the judicial exception, and hence these features are not indicative of integration into a practical application.
In analyzing under step 2A Prong Two, Does the claim recite additional elements that integrate the judicial exception into a practical application? NO.
This judicial exception is not integrated into a practical application because the claims recite a generic processor such as ““a device, comprising: a processor; a memory communicatively coupled to the processor; and a reception logic, configured to:” (see claims 1 and 13) for receiving inputs. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because a generic processor and software module which are high level of generality performing code generation. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
In analyzing under step 2B, does the claim recite additional elements that amount to significantly more than the judicial exception? NO
Claims 1-20 do not recite any additional elements except a generic processor with software module for receiving.
Accordingly, the additional generic elements do not amount to significantly more than the judicial exception because a generic processor and software module which are high level of generality performing code generation
The claim is directed at an abstract idea.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6, 7, 15, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Varanese et al. (US 2014/0,010,539)
As per claim 1:
Varanese discloses:
A device, comprising: a processor; a memory communicatively coupled to the processor; and a transmission logic, configured to:
(Varanese, Figs 1-13)
receive a bitstream corresponding to a data packet;
(Varanese, [0049] The PCS 514 receives the bitstream 710, detects the frames 702-1 through 702-4 and 704 by virtue of the idle character sequences 712, and deletes the idle character sequences 712. The encoder 518 adds parity bits to the data (D+P) and encodes each frame 702-1 through 702-4 using specified MCSs (e.g., as specified by information in the dummy frame 704)
detect
(Varanese, [0049] The PCS 514 receives the bitstream 710, detects the frames 702-1 through 702-4 and 704 by virtue of the idle character sequences 712…)
an interruption;
(Varanese, Fig. 7 shows a bitstream 700 with a gap (which can be considered as interruption) between frame 702-1 and 702-2 )
(Varanese, Fig. 7 shows a bitstream 710 with idle character (which can be considered as interruption also) between frame 702-1 and 702-2 )
(Varanese, [0049] The PCS 514 receives the bitstream 710, detects the frames 702-1 through 702-4 and 704 by virtue of the idle character sequences 712, and deletes the idle character sequences 712….)
generate an intra-packet word based
(Varanese, [0049] … and deletes the idle character sequences 712. The encoder 518 adds parity bits to the data (D+P) and encodes each frame 702-1 through 702-4 using specified MCSs (e.g., as specified by information in the dummy frame 704)
on the interruption;
(Varanese, Fig. 7 shows a bitstream 700 with a gap (which can be considered as interruption) between frame 702-1 and 702-2 )
(Varanese, Fig. 7 shows a bitstream 710 with idle character (which can be considered as interruption also) between frame 702-1 and 702-2 )
insert the intra-packet word; and
(Varanese, [0049] … The encoder 518 adds parity bits to the data (D+P) and encodes each frame 702-1 through 702-4 using …)
(Varanese, Fig. 7 shows an insertion parity such as D+P into the bitstream 700 or 710)
transmit a signal indicative of the intra-packet word.
(Varanese,[0050] The signal 720 is provided to the PMA 524)
(Varanese in [0050] discloses that the signal 720 as shown in figure 7 is transmitted to PMA 524)
As per claim 6:
Varanese further discloses:
wherein the intra-packet word includes a predetermined bit sequence.
(Varanese, Fig. 7 shows a bitstream 700 with a gap (which can be considered as interruption) between frame 702-1 and 702-2 )
(Varanese, Fig. 7 shows a bitstream 710 with idle character (which can be considered as interruption also) between frame 702-1 and 702-2 )
(Varanese, [0049] The PCS 514 receives the bitstream 710, detects the frames 702-1 through 702-4 and 704 by virtue of the idle character sequences 712, and deletes the idle character sequences 712….)
As per claim 7:
Varanese further discloses:
wherein the transmission logic is further configured to select a bit sequence for the intra-packet word based on a required error correction metric.
(Varanese, [0049] … and deletes the idle character sequences 712. The encoder 518 adds parity bits to the data (D+P) and encodes each frame 702-1 through 702-4 using specified MCSs (e.g., as specified by information in the dummy frame 704)
As per claim 15:
Varanese discloses:
A method, comprising:
(Varanese, Figs 1-13)
receiving a bitstream corresponding to a data packet;
(Varanese, [0049] The PCS 514 receives the bitstream 710, detects the frames 702-1 through 702-4 and 704 by virtue of the idle character sequences 712, and deletes the idle character sequences 712. The encoder 518 adds parity bits to the data (D+P) and encodes each frame 702-1 through 702-4 using specified MCSs (e.g., as specified by information in the dummy frame 704)
detecting
(Varanese, [0049] The PCS 514 receives the bitstream 710, detects the frames 702-1 through 702-4 and 704 by virtue of the idle character sequences 712…)
an interruption in a reception of the bitstream;
(Varanese, Fig. 7 shows a bitstream 700 with a gap (which can be considered as interruption) between frame 702-1 and 702-2 )
(Varanese, Fig. 7 shows a bitstream 710 with idle character (which can be considered as interruption also) between frame 702-1 and 702-2 )
(Varanese, [0049] The PCS 514 receives the bitstream 710, detects the frames 702-1 through 702-4 and 704 by virtue of the idle character sequences 712, and deletes the idle character sequences 712….)
generating an intra-packet word
(Varanese, [0049] … and deletes the idle character sequences 712. The encoder 518 adds parity bits to the data (D+P) and encodes each frame 702-1 through 702-4 using specified MCSs (e.g., as specified by information in the dummy frame 704)
on the interruption; and
(Varanese, Fig. 7 shows a bitstream 700 with a gap (which can be considered as interruption) between frame 702-1 and 702-2 )
(Varanese, Fig. 7 shows a bitstream 710 with idle character (which can be considered as interruption also) between frame 702-1 and 702-2 )
transmitting an idle signal indicative of the intra-packet word.
(Varanese,[0050] The signal 720 is provided to the PMA 524)
(Varanese in [0050] discloses that the signal 720 as shown in figure 7 is transmitted to PMA 524)
As per claim 18:
Varanese further discloses:
selecting a bit sequence for the intra- packet word based on a required error correction metric.
(Varanese, [0049] … and deletes the idle character sequences 712. The encoder 518 adds parity bits to the data (D+P) and encodes each frame 702-1 through 702-4 using specified MCSs (e.g., as specified by information in the dummy frame 704)
As per claim 19:
Varanese further discloses:
determining an encoding standard corresponding to a type of a physical channel; and encoding the data packet based on the encoding standard.
(Varanese, [0049] … and deletes the idle character sequences 712. The encoder 518 adds parity bits to the data (D+P) and encodes each frame 702-1 through 702-4 using specified MCSs (e.g., as specified by information in the dummy frame 704)
As per claim 20:
Varanese further discloses:
transmitting a data signal indicative of an encoded data packet.
(Varanese, [0050] The signal 720 is provided to the PMA 524)
(Varanese in [0050] discloses that the signal 720 as shown in figure 7 is transmitted to PMA 524)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THIEN DANG NGUYEN whose telephone number is (571)272-9189. The examiner can normally be reached Monday-Friday 7 AM - 3:30 PM.
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/Thien Nguyen/ Primary Examiner, Art Unit 2111
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