DETAILED ACTION
This action is responsive to the application filed March 7, 2025. Claims 1-15 are pending. Claim 1 is independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application PCT Application No. PCT/JP2022/045360, filed December 8, 2022 under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statements (IDS) filed on March 7, 2025 and March 17, 2025. These IDS have been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Multi-Chip Semiconductor Memory Device with Shared Word Line and Differential Initial Program Voltages.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over Ogawa et al. (US 20220139441), in view of Nosaka et al. (US 20200026346).
Regarding independent claim 1, Ogawa discloses a semiconductor memory device comprising:
a first chip including:
a first pillar including a first memory cell; and a second pillar including a second memory cell (Fig. 27A; first semiconductor die 801, which includes a plurality of memory opening fill structures 58 which contain a plurality of memory stack (pillar) structures 55);
a second chip including:
a third pillar including a third memory cell; and a fourth pillar including a fourth memory cell (Fig. 27A; second semiconductor die 802, which includes a plurality of memory opening fill structures 58 which contain a plurality of memory stack (pillar) structures 55;
and a third chip including:
a row decoder to which a first word line coupled to a gate of each of the first to the fourth memory cells is coupled (Abstr. "The peripheral circuit includes a first word line driver circuit having first word line driver output nodes electrically connected to at least some of the first word lines and at least some of the second word lines, and each first word line is electrically connected to a respective second word line.");
Ogawa discloses a muti-chip semiconductor memory device comprising first and second three-dimensional memory arrays bonded to a peripheral circuit die connecting corresponding word lines on both array dies, but is silent with respect to applying different initial program voltages on the shared word lines.
However, Nosaka teaches and a controller configured to execute a write operation in which a program loop is repeated, the program loop including a program operation and a program verify operation (Fig. 4; See also para. 20; "the write operation includes two operation modes: a normal mode and a smart verify mode"),
wherein in a first time of the program operation of the write operation of the first memory cell, the row decoder applies a first program voltage to the first word line (para. 68; "The normal mode is an operation mode of executing a write operation using a voltage VPGM set in advance as a program voltage of a first program loop.". See also para. 71; "in the first program loop, the row decoder 109 applies a voltage VPGM as a program voltage to the selected word line WL during a program operation (PG)"),
in a first time of the program operation of the write operation of the second memory cell, the row decoder applies a second program voltage higher than the first program voltage to the first word line (para. 69; "The smart verify mode is an operation mode of executing a write operation using a voltage VPGMS set on the basis of the program parameter information as a program voltage of a first program loop. The voltage VPGMS is a voltage higher than the voltage VPGM.". See also para. 71; "the first program voltage VPGMS of the smart verify mode is determined". And see para. 72; "the first program loop is executed using the set voltage VPGMS".),
in a first time of the program operation of the write operation of the third memory cell, the row decoder applies a third program voltage to the first word line (para. 68; "The normal mode is an operation mode of executing a write operation using a voltage VPGM set in advance as a program voltage of a first program loop." It is noted that the program voltage is applied to corresponding cells on the second chip via the electrically common word line taught by Ogawa.),
and in a first time of the program operation of the write operation of the fourth memory cell, the row decoder applies a fourth program voltage higher than the third program voltage to the first word line (para. 69; "The voltage VPGMS is a voltage higher than the voltage VPGM.". Id. and for the same reason.)
Ogawa and Nosaka are from the same field of endeavor as applicant' s invention directed to programming operations in non-volatile memory devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the multi-chip memory device of Ogawa by incorporating the differential initial program voltage scheme of Nosaka (normal mode lower initial voltage VPGM and smart-verify higher initial voltage VPGMS determined from a prior write result). Ogawa already provides a shared word line driven by a common driver across multiple array dies. Applying Nosaka's known technique of using a higher initial program voltage for subsequent writes (based on information obtained from a prior write) to the shared word lines of Ogawa would have yielded the predictable benefit of reducing the number of program loops, and thereby reducing programming time and power consumption, on both array dies simultaneously. Doing so would improve programming efficiency in the multi-chip architecture of Ogawa without changing its basic operating principle.
Regarding claim 2, Ogawa and Nosaka combined disclose the limitations of claim 1.
As applied, Nosaka further discloses wherein the controller sets the second program voltage based on a result of the write operation of the first memory cell (Abstr, " a program voltage used in the second operation mode being determined on the basis of first information obtained in the first operation mode". See also para 69. "The smart verify mode is an operation mode of executing a write operation using a voltage VPGMS set on the basis of the program parameter information as a program voltage of a first program loop", "the first write operation in a target memory area is executed in the normal mode, and the program parameter information is extracted using the smart verify function. Then, subsequent write operations in the target memory area are executed in the smart verify mode."),
and sets the fourth program voltage based on a result of the write operation of the third memory cell (para. 69; "a voltage VPGMS set on the basis of the program parameter information". See also para. 72; "As illustrated in a lower figure of FIG. 4, on the basis of the result of the normal mode, for example, the fourth program voltage (VPGM+3×DVPGM) in the normal mode is set as the voltage VPGMS").
Regarding claim 3, Ogawa and Nosaka combined disclose the limitations of claim 1.
As applied, Nosaka further discloses wherein the first program voltage and the third program voltage are identical (para. 68; "The normal mode is an operation mode of executing a write operation using a voltage VPGM set in advance as a program voltage of a first program loop". It is noted that Nosaka teaches a single predetermined initial programming voltage (VPGM) used as the starting voltage in normal mode. When this teaching is applied to the multi-chip structure of Ogawa (in which a common word line is electrically shared across the first and second chips), the same predetermined initial voltage is necessarily applied to both the first memory cell and the third memory cell..
Regarding claim 4, Ogawa and Nosaka combined disclose the limitations of claim 1.
As applied, Nosaka further discloses wherein a number of times of the program loop in the write operation of the second memory cell is smaller than a number of times of the program loop in the write operation of the first memory cell (para. 72; "in the smart verify mode, the verification is passed in the second program loop, and the number of program loops is reduced from five to two.").
Regarding claim 5, Ogawa and Nosaka combined disclose the limitations of claim 1.
As applied, Nosaka further discloses wherein the first program voltage increases along with repetition of the program loop (para. 71; "each time the program loop is repeated, the program voltage is stepped up by a voltage DVPGM").
Regarding claim 6, Ogawa and Nosaka combined disclose the limitations of claim 1.
As applied Ogawa further discloses wherein the third chip further includes a sense amplifier (para. 54; "the first bit line driver circuit 720B includes sense amplifiers and other peripheral circuit components") to which a bit line commonly coupled to one end of each of the first to the fourth pillars is coupled (para. 54; " the first bit line driver circuit 720B has first bit line driver output nodes configured to be electrically connected to, and to drive, a first subset of the first bit lines in the first three-dimensional memory array to be subsequently formed, and a first subset of the second bit lines in a second three-dimensional memory array to be subsequently provided").
Regarding claim 7, Ogawa and Nosaka combined disclose the limitations of claim 1.
As applied, Ogawa further discloses wherein the first pillar further includes a first selection transistor coupled in series with the first memory cell and having a gate coupled to the row decoder via a first select gate line (Abstr. "a first alternating stack of first insulating layers and first electrically conductive layers containing first word lines and first select lines, and first memory stack structures vertically extending through the first alternating stack", "a second alternating stack of second insulating layers and second electrically conductive layers containing second word lines and second select lines, and second memory stack structures vertically extending through the second alternating stack." See also para. 51; "the first select line driver circuit 720S can comprise first select line driver output nodes (e.g., source and/or drain electrodes of driver circuit transistors) that are configured to be electrically connected to a second subset of the first electrically conductive layers." See also para. 52; "first source-side select line driver output nodes that are configured to be electrically connected to source-side select lines (i.e., source-side select gate electrodes)". And finally, para. 53; "first drain-side select line driver output nodes that are configured to be electrically connected to drain-side select lines". It is noted that the select transistors are coupled in series within the vertical NAND strings, and their gates are connected to the row decoder / driver circuitry via the select lines thus fully satisfying the requirements of the claim for all four pillars).,
the second pillar further includes a second selection transistor coupled in series with the second memory cell and having a gate coupled to the row decoder via a second select gate line (id. and for the same reason),
the third pillar further includes a third selection transistor coupled in series with the third memory cell and having a gate coupled to the row decoder via a third select gate line (id. and for the same reason),
and the fourth pillar further includes a fourth selection transistor coupled in series with the fourth memory cell and having a gate coupled to the row decoder via a fourth select gate line (id. and for the same reason).
Regarding claim 8, Ogawa and Nosaka combined disclose the limitations of claim 1.
As applied, Ogawa further discloses wherein the first pillar and the third pillar extend in a first direction and are arranged side by side in the first direction (Fig. 27A. See also para. 132; "each of the first memory stack structures 55 comprises a respective first vertical semiconductor channel 60 and a respective first vertical stack of memory elements"... "each of the second memory stack structures 55 comprises a respective second vertical semiconductor channel 60 and a respective second vertical stack of memory elements")
Regarding claim 9, Ogawa and Nosaka combined disclose the limitations of claim 1.
As applied, Ogawa further discloses wherein the first pillar includes a semiconductor layer and a charge storage layer (Fig. 4C. See also para. 68; "a stack of layers including a blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and an optional semiconductor channel layer 601 can be sequentially deposited in the memory openings 49.").
Regarding claim 10, Ogawa and Nosaka combined disclose the limitations of claim 1.
As applied, Ogawa further discloses wherein the second chip is bonded to a first surface of the first chip (Fig. 22B. See also para. 122; "the bonding pads 98 of each respective semiconductor die (800, 901) are bonded to each other to electrically connect the respective bit lines 92 of both semiconductor die (800, 901) to each other and to the bit line driver circuit 720B of the semiconductor die 901.").
and the third chip is bonded to a second surface of the first chip facing the first surface (para. 123; "the respective word lines 46W in each semiconductor die (800, 901) are electrically connected to each other through contact via structures 86 and bonding pads 98 and are connected in common to the same word line driver circuit". It is noted that Ogawa teaches face to face bonding of the first and second chips and the connection of both to the peripheral circuitry analogous to the instant application).
Regarding claim 11, Ogawa and Nosaka combined disclose the limitations of claim 1.
As applied, Ogawa further discloses wherein the first pillar further includes a fifth memory cell coupled in series with the first memory cell (para. 132; "each of the first memory stack structures 55 comprises a respective first vertical semiconductor channel 60 and a respective first vertical stack of memory elements", "each of the second memory stack structures 55 comprises a respective second vertical semiconductor channel 60 and a respective second vertical stack of memory elements". It is noted that the same reasoning applies to the corresponding sixth, seventh, and eighth memory cells in the other pillars because multiple memory cells stacked in series along each vertical pillar is inherent in the 3D NAND memory structures of Ogawa.),
the second pillar further includes a sixth memory cell coupled in series with the second memory cell (id. and for the same reason),
the third pillar further includes a seventh memory cell coupled in series with the third memory cell (id. and for the same reason),
the fourth pillar further includes an eighth memory cell coupled in series with the fourth memory cell (id. and for the same reason),
a gate of each of the fifth to the eighth memory cells is coupled to the row decoder via a second word line (Abstr. "first electrically conductive layers containing first word lines… second electrically conductive layers containing second word lines". See also para. 129; "first word line driver output nodes 724 electrically connected to at least some of the first word lines 46W and at least some of the second word lines… each first word line is electrically connected to a respective second word line."),
Ogawa discloses a muti-chip semiconductor memory device comprising first and second three-dimensional memory arrays bonded to a peripheral circuit die connecting corresponding word lines on both array dies, but is silent with respect to applying different initial program voltages on the shared word lines.
However, Nosaka teaches in a first time of the program operation of the write operation of the fifth memory cell, the row decoder applies a fifth program voltage to the second word line, in a first time of the program operation of the write operation of the sixth memory cell, the row decoder applies a sixth program voltage higher than the fifth program voltage to the second word line (para. 68; "The normal mode is an operation mode of executing a write operation using a voltage VPGM set in advance as a program voltage of a first program loop.". See also para. 69; "The smart verify mode is an operation mode of executing a write operation using a voltage VPGMS… The voltage VPGMS is a voltage higher than the voltage VPGM.". It is noted that this limitation is the same differential initial voltage scheme already mapped for claim 1, now applied to a second word line.),
in a first time of the program operation of the write operation of the seventh memory cell, the row decoder applies the sixth program voltage to the second word line, and in a first time of the program operation of the write operation of the eighth memory cell, the row decoder applies the sixth program voltage to the second word line (para. 69; "The voltage VPGMS is a voltage higher than the voltage VPGM.". Id. and for the same reason. It is further noted that the limitations of claim 11 are merely the natural extension of the claim 1 structure (multiple series cells + second shared word line from Ogawa) combined with the same differential initial program voltage scheme (Nosaka)).
Regarding claim 12, Ogawa and Nosaka combined disclose the limitations of claim 11.
As applied, Nosaka further discloses wherein the controller sets the sixth program voltage based on a result of the write operation of the fifth memory cell (para. 12; "a program voltage used in the second operation mode being determined on the basis of first information obtained in the first operation mode." Nosaka expressly teaches that the higher initial program voltage of the subsequent write is set based on the result / program parameter information obtained from a prior (normal-mode) write. When this teaching is applied to the second word line and the fifth/sixth memory cells of claim 11 (via the multi-chip shared word line structure of Ogawa), the sixth program voltage is set based on the result of the fifth memory cell.).
Regarding claim 13, Ogawa and Nosaka combined disclose the limitations of claim 11.
As applied, Nosaka further discloses wherein the first program voltage, the third program voltage, and the fifth program voltage are identical (para. 68; "The normal mode is an operation mode of executing a write operation using a voltage VPGM set in advance as a program voltage of a first program loop.". Nosaka teaches a single predetermined initial program voltage (VPGM) used as a starting voltage in the normal mode. When this teaching is applied across the first word line (first and third memory cells) and the second word line (fifth memory cell) via the shared word line multi-chip structure of Ogawa, the same predetermined initial voltage is applied in each case. The identity of the first, third, and fifth program voltages is therefore the clear and predictable result of the combination.)
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Ogawa et al. (US 20220139441), in view of Nosaka et al. (US 20200026346), and further in view of Hemink (US 20100103733).
Regarding claim 14, Ogawa and Nosaka combined disclose the limitations of claim 1.
As applied, Nosaka further discloses wherein the controller sets: the second program voltage based on a result of the write operation of the first memory cell (Abstr. "a program voltage used in the second operation mode being determined on the basis of first information obtained in the first operation mode". See also para. 69; "The smart verify mode is an operation mode of executing a write operation using a voltage VPGMS set on the basis of the program parameter information as a program voltage of a first program loop.".
and the fourth program voltage based on a result of the write operation of the third memory cell (para. 69; "a voltage VPGMS set on the basis of the program parameter information" See also para. 71; "According to this result, the first program voltage VPGMS of the smart verify mode is determined."); .
Nosaka discloses a controller that sets a higher initial program voltage (VPGMS) for a subsequent write operation based on a result (program parameter information) obtained from a prior write operation (normal mode), and applies the differential initial voltages through a word line, but is silent with respect to seeing a third program voltage based on the second program voltage itself (i.e., using the magnitude or value of the already determined higher second program voltage as the basis for determining the starting voltage of a further subsequent write operation).
However, Hemink teaches the third program voltage based on the second program voltage (Fig. 18 where it illustrates the adaptive starting voltage concept. See also Abstr. "the identified programming pulse is used to adjust a starting programming voltage for a subsequent programming process". See also para 14; "The second set of programming pulses includes a first pulse having a magnitude based on the stored indication". See also para. 15; "store an indication based on the nth programming pulse". And further see para. 16; "The method further includes performing an additional stage of the multi-stage programming process including applying a second set of programming pulses having an initial pulse with a magnitude set based on the stored indication.");
Ogawa, Nosaka and Hemink are from the same field of endeavor as applicant' s invention directed to optimized programming operations in non-volatile memory devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the multi-chip memory device of Ogawa (as already modified by Nosaka's differential initial program voltage) by incorporating the teaching of Hemink of using an identified program pulse magnitude (or a stored indication thereof) from one programming process to set or adjust the starting program voltage of a subsequent programming process. Applying Hemink's known technique to the sequential write operations performed on the shared word line of the Ogawa/Nosaka combination would have yielded the predictable benefit of further refining the initial program voltage for subsequent cells, thereby further reducing the number of program loops and improving programming efficiency.
Regarding claim 15, Ogawa and Nosaka combined disclose the limitations of claim 1.
Ogawa and Nosaka combined are silent with respect to the magnitude of the third voltage.
However, Hemink teaches wherein the third program voltage is higher than the first program voltage and lower than the second program voltage (Fig. 16. See also para 86; "In step 660 of FIG. 16, the system will read a stored identification of a magnitude for an initial programming pulse (hereinafter referred to as "Vpgm_vstart"), which can be based on previous programming or a default value"… "the magnitude will be determined from one or more previous programming processes. If this is the first time that programming is being performed, a default value for Vpgm_vstart can be read from a register.").
Ogawa, Nosaka and Hemink are from the same field of endeavor as applicant' s invention directed to optimized programming operations in non-volatile memory devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the multi-chip memory device of Ogawa (as already modified by Nosaka's differential initial program voltage) by incorporating Hemink's teaching of deriving a starting program voltage for a subsequent programming process from a stored indication of a pulse magnitude determined in a prior programming process (or from a default value when no prior result is available). Doing so would achieve a more refined control of the initial program voltages across successive write operations, thereby further improving programming efficiency and accuracy in the multi-chip architecture.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yip (US 20110007562) – Determining an optimal program voltage from a lower-page write and applying an offset to set the starting program voltage for a subsequent upper-page write.
Liu et al. (WO 2020000392) – Multi-chip bonded 3D NAND architecture with memory array dies stacked with a peripheral circuit die.
Hara et al. (US 20220157387) – Multi-level cell programming schemes with adaptive or mode-based program voltage control in NAND memory.
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/James S. Wells/Examiner, Art Unit 2825
/Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825
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