DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statements (IDS) submitted on March 8, 2025 and March 17, 2025 have been fully considered by the examiner.
Specification
3. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Semiconductor Memory Device with Shared Word Lines between Memory Chips”
Claim Rejections - 35 USC § 112
4. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation “the write operation of the first memory cell” in line 3. There is insufficient antecedent basis for this limitation in the claim. For the purposes of this action, the aforementioned limitation shall be interpreted as “[[the]] a write operation of the first memory cell.”
Claim 10 recites the limitation “the write operation” in line 3. There is insufficient antecedent basis for this limitation in the claim. For the purposes of this action, the aforementioned limitation shall be interpreted as “[[the]] a write operation,” which shall provide antecedent basis for “the write operation” in lines 5-6.
Claim 11 recites the limitation “the write operation” in line 3. There is insufficient antecedent basis for this limitation in the claim. For the purposes of this action, the aforementioned limitation shall be interpreted as “[[the]] a write operation.”
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. Claims 1, 8, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Ogawa, et al (US 20220139878 A1), hereinafter Ogawa, in view of Liu, et al (US 20200006299 A1), hereinafter Liu.
Regarding independent claim 1, Ogawa teaches a semiconductor memory device (FIG. 14) comprising:
a first chip (FIG. 14, 901) including:
a first pillar (FIGS. 14 and 4H, 58 in chip 901) including a first memory cell (FIG. 4H, see alternating stack of insulating (FIG. 4H, 32) and conductive (FIG. 4H, 42) layers around pillar 58).
and a second memory cell coupled in series (FIG. 4H, a second memory cell adjacent to the first memory cell in the same pillar in chip 901);
a first bit line coupled to one end of the first pillar (FIG. 14, 92 in chip 901; ¶[0095]); and
a first source line coupled to another end of the first pillar (¶[0089] teaches “a respective source region embedded in the semiconductor material layer 912,” which is shown in FIG. 14 at the opposite end of the pillars from the bit line end in chip 901);
a second chip (FIG. 14, 902) including:
a second pillar (FIGS. 14 and 4H, 58 in chip 902) including a third memory cell and a fourth memory cell coupled in series (FIG. 4H, any two memory cells in the same pillar in chip 902);
a second bit line coupled to one end of the second pillar (FIG.14, 92 in chip 902; ¶[0095]); and
a second source line coupled to another end of the second pillar (¶[0089] teaches “a respective source region embedded in the semiconductor material layer 912,” which is shown in FIG. 14 at the opposite end of the pillars from the bit line end in chip 902).
A sense amplifier to which the first bit line and the second bit line are commonly coupled (FIG. 1, 720B; ¶[0054] teaches “the first bit line driver circuit 720B includes sense amplifiers”).
Ogawa does not teach the sense amplifier is in a third chip.
Liu teaches the sense amplifier is in a third chip (FIG. 1, peripheral chip 102, ¶[0037-0039]; ¶[0039] teaches “peripheral device 106 can include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier…”).
Ogawa as modified by Liu further teaches a row decoder (Liu ¶[0039] teaches “peripheral device 106 can include one or more of…a decoder (e.g., a row decoder and a column decoder)…a driver…”) to which a first word line, a second word line, and a third word line are coupled (Ogawa Abstract teaches “The peripheral circuit includes a first word line driver circuit having first word line driver output nodes electrically connected to at least some of the first word lines and at least some of the second word lines…”, and “a first alternating stack of first insulating layers and first electrically conductive layers containing first word lines” (e.g., the memory stack of chip 901), and “a second alternating stack of second insulating layers and second electrically conductive layers containing second word lines” (e.g., the memory stack of chip 902)), the first word line being coupled to a gate of the first memory cell, the second word line being coupled to a gate of the third memory cell, and the third word line being coupled to gates of the second memory cell and the fourth memory cell (Ogawa ¶[0050] teaches “first word lines which function as first control gate electrodes” (i.e., word lines in chip 901) and “second word lines which function as second control gate electrodes” (i.e., word lines in chip 902). The intent of the claim is a first word line is coupled to a cell in the first chip, a second word line is coupled to a cell in a second chip, and a third word line is coupled to cells in both first and second chips. Ogawa Abstract teaches “a first word line driver circuit having first word line driver output nodes electrically connected to at least some of the first word lines and at least some of the second word lines.” This is illustrated in FIG. 16A, in which some contact via structures 86 are connected to only word lines in chip 902, some are connected only to word lines in chip 901, and some are connected to word lines in both chips.).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Liu into the method of Ogawa to include placing peripheral circuits (decoder, sense amps) on a separate (“third”) chip. The ordinary artisan would have been motivated to modify Ogawa in the above manner for the purpose of optimizing processes for the peripheral and memory chips (Liu ¶[0039], [0058], [0068], [0074]).
Regarding claim 8, Ogawa as modified by Liu teaches the limitations of claim 1.
Ogawa further teaches the first pillar further includes a first selection transistor coupled in series with the first memory cell and the second memory cell, and having a gate coupled to the row decoder via a first select gate line (¶[0051] teaches “the first select line driver circuit 720S can comprise first select line driver output nodes (e.g., source and/or drain electrodes of driver circuit transistors) that are configured to be electrically connected to a second subset of the first electrically conductive layers (e.g., source side and/or drain side select gate electrodes) of the first three-dimensional memory array”; ¶[0092] teaches “first electrically conductive layers 46 (which function as word lines and select lines),” indicating memory cells and select transistors are in series; ¶[0050] teaches “a word line refers to an electrically conductive line that can activate or deactivate access to a selected memory cell,” indicating coupling to a decoder to enable such selections, e.g., the decoder of Liu ¶[0039]), and
the second pillar further includes a second selection transistor coupled in series with the third memory cell and the fourth memory cell, and having a gate coupled to the row decoder via a second select gate line (Ogawa ¶[0101] teaches “second source-side select line driver output nodes that are electrically connected to source-side select lines among the second electrically conductive layers 46 of the second three-dimensional memory array”).
Regarding claim 12, Ogawa as modified by Liu teaches the limitations of claim 1.
Ogawa further teaches the first pillar and the second pillar extend in a first direction, and are arranged side by side in the first direction (FIG. 14, “first” pillars are in chip 901 and “second” pillars are in chip 902. Both first and second pillars are shown arranged side-by-side horizontally (second direction) and extending vertically (first direction)).
7. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ogawa, et al (US 20220139878 A1), hereinafter Ogawa, in view of Liu, et al (US 20200006299 A1), hereinafter Liu, and further in view of Kutsukake (US 20230292519 A1).
Regarding claim 7, Ogawa as modified by Liu teaches the limitations of claim 1.
Liu further teaches the third chip (FIG. 1, 102; ¶[0038]) further includes a driver circuit (FIG. 1, 106; ¶[0039] teaches “peripheral device 106 can include one or more of…a decoder (e.g., a row decoder and a column decoder),…a driver…”).
Ogawa does not teach the driver circuit supplies a voltage to the row decoder, and the row decoder includes:
a first switch circuit coupled between the first word line and the driver circuit;
a second switch circuit coupled between the second word line and the driver circuit; and
a third switch circuit coupled between the third word line and the driver circuit (note Ogawa teaches a driver and switches (¶[0050]), and Liu teaches a row decoder and driver (¶[0039]), but neither teaches the order in which the driver and decoder are coupled to one another).
Kutsukake teaches the driver circuit (FIG. 4, 14) supplies a voltage to the row decoder (FIG. 4, driver module 14 precedes row decoder RD0; ¶[0060] teaches “the driver module 14 applies a generated voltage to the signal line corresponding to the selected word line,” which would be through the row decoder), and the row decoder includes:
a first switch circuit coupled between the first word line and the driver circuit (FIG. 4, e.g., TW0);
a second switch circuit coupled between the second word line and the driver circuit (FIG. 4, e.g., TW1); and
a third switch circuit coupled between the third word line and the driver circuit (FIG. 4, e.g., TW2).
Because Ogawa together with Liu and Kutsukake each teach the common design elements of row decoders and row drivers, it would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the row decoder and row driver of Kutsukake with the row decoder and row driver of Ogawa as modified by Liu to yield predictable results. See MPEP § 2143(I)(B).
8. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Ogawa, et al (US 20220139878 A1), hereinafter Ogawa, in view of Liu, et al (US 20200006299 A1), hereinafter Liu, and further in view of Yang, et al (US 20210217760 A1), hereinafter Yang.
Regarding claim 13, Ogawa as modified by Liu teaches the limitations of claim 1.
Ogawa further teaches the second chip is bonded to a first surface of the first chip (FIG. 10; ¶[0103]; first surface is opposite the first chip substrate).
Ogawa does not teach the third chip is bonded to a second surface of the first chip facing the first surface (note Liu FIG. 1 teaches the third chip is bonded to a second surface of the first chip facing the first surface, but through an interposer).
Yang teaches in FIG. 3C the second chip (300) is bonded (¶[0122]) to a first surface (surface of substrate 201; ¶[0098]) of the first chip (200), and the third chip (100) is bonded to a second surface of the first chip facing the first surface (surface opposite substrate 201; ¶[0098]).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Yang into the method of Ogawa to include directly bonding a plurality of chips (e.g., without the interposer of Liu). The ordinary artisan would have been motivated to modify Ogawa in the above manner for the purpose of reducing a total resistance of each of the bit lines and to decrease parasitic capacitance between the bit lines, which may result in an improvement in performance of the semiconductor memory device (Yang ¶[0205]).
9. Claims 2, 5, 9, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Ogawa, et al (US 20220139878 A1), hereinafter Ogawa, in view of Liu, et al (US 20200006299 A1), hereinafter Liu, and further in view of Wang, et al (US 20220068390 A1), hereinafter Wang.
Regarding claim 2, Ogawa as modified by Liu teaches the limitations of claim 1.
Ogawa does not teach in a write operation of the first memory cell, the row decoder applies a first voltage to the first word line, a second voltage to the second word line, and a third voltage to the third word line, the second voltage being lower than the first voltage, the third voltage being lower than the first voltage.
Wang teaches in a write operation of the first memory cell, the row decoder applies a first voltage to the first word line (FIG. 16, WLn, Vpgm), a second voltage to the second word line (FIG. 16, WLn+1, Vpass), and a third voltage to the third word line (FIG. 16, WLn+2, VpassL-), the second voltage being lower than the first voltage, the third voltage being lower than the first voltage (¶[0198] teaches “VpassL−, VpassL and VpassL+ (where VpassL-<VpassL<VpassL+) refer to example pass voltages which are less than Vpass,” and all of which are less than Vpgm; see FIG. 23).
Regarding claim 5, Ogawa as modified by Liu teaches the limitations of claim 1.
Ogawa does not teach in a write operation of the second memory cell, the row decoder applies an eighth voltage to the third word line, a ninth voltage to the first word line, and a tenth voltage to the second word line, the ninth voltage being lower than the eighth voltage, the tenth voltage being higher than the ninth voltage and lower than the eighth voltage.
Wang teaches in a write operation of the second memory cell, the row decoder applies an eighth voltage to the third word line (FIG. 16, WLn, Vpgm), a ninth voltage to the first word line (FIG. 16, WLn-2, VpassL-), and a tenth voltage to the second word line (FIG. 16, WLn-1, Vpass), the ninth voltage being lower than the eighth voltage, the tenth voltage being higher than the ninth voltage and lower than the eighth voltage (¶[0198] teaches “VpassL−, VpassL and VpassL+ (where VpassL-<VpassL<VpassL+) refer to example pass voltages which are less than Vpass,” and all of which are less than Vpgm; see FIG. 23).
Regarding claims 2 and 5, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Wang into the method of Ogawa to include a low pass voltage to designated word lines and a normal pass voltage to other word lines. The ordinary artisan would have been motivated to modify Ogawa in the above manner for the purpose of creating barriers to the movement of electrons in the channel toward the selected word line, to prevent the electrons from pulling down the voltage at the channel region which is adjacent to the selected word line (Wang, Abstract).
Regarding claim 9, Ogawa as modified by Liu teaches the limitations of claim 8.
Ogawa does not teach in the write operation of the first memory cell, the row decoder applies a twelfth voltage to the first select gate line and a thirteenth voltage to the second select gate line, the thirteenth voltage being lower than the twelfth voltage.
Wang teaches in the write operation of the first memory cell, the row decoder applies a twelfth voltage to the first select gate line (FIG. 23, Vsgd_sel to Vsgd (waveform 2322)) and a thirteenth voltage to the second select gate line (FIG. 23, 0V to Vsgs (waveform 2334)), the thirteenth voltage being lower than the twelfth voltage (FIG. 23, Vsgd_sel = 2.5V > 0V).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Wang into the method of Ogawa to set the first select gate line to an elevated level with respect to the second select gate line during a write operation. The ordinary artisan would have been motivated to modify Ogawa in the above manner for the purpose of putting the associated SGD transistors in a conductive state for the selected NAND strings in a program phase of a write operation (Wang, ¶[0234]).
Regarding claim 11, Ogawa as modified by Liu teaches the limitations of claim 1.
Ogawa does not teach the write operation includes a program operation and a program verify operation.
Wang teaches the write operation includes a program operation (¶[0050]) and a program verify operation (¶[0091]).
Wang further teaches in the program verify operation in the write operation of the second memory cell, the row decoder applies a seventeenth voltage to the third word line (FIG. 23, e.g., VvE applied to selected word line WLn) and an eighteenth voltage to the first word line and the second word line (FIG. 23, Vread applied to unselected word lines WL_unsel), the eighteenth voltage being higher than the seventeenth voltage (FIG. 23, e.g., Vread > VvE).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Wang into the method of Ogawa to include a verify test in a program loop. The ordinary artisan would have been motivated to modify Ogawa in the above manner for the purpose of sensing a memory cell to determine whether it has completed programming by reaching an assigned data state (Wang, ¶[0091]).
10. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ogawa, et al (US 20220139878 A1), hereinafter Ogawa, in view of Liu, et al (US 20200006299 A1), hereinafter Liu, and further in view of Zainuddin, et al (US 11205493 B1), hereinafter Zainuddin.
Regarding claim 10, Ogawa as modified by Liu teaches the limitations of claim 1.
Ogawa does not teach the write operation includes a program operation and a program verify operation.
Zainuddin teaches the write operation includes a program operation and a program verify operation (Col. 3, ll. 1-5).
Zainuddin further teaches in the program verify operation in the write operation of the first memory cell, the row decoder applies a fourteenth voltage to the first word line (FIG. 13A, e.g., VrA applied to selected word line WLn), a fifteenth voltage to the second word line (FIG. 13A, Vread applied to non-adjacent unselected word lines WL_unsel (waveform 1313); Col. 25, ll. 13-16), and a sixteenth voltage to the third word line (FIG. 13A, VreadK applied to unselected word lines adjacent to the selected word line (waveform 1316); Col. 25, ll. 17-18), the fifteenth voltage being higher than the fourteenth voltage (FIG. 13A, Vread > VrA), the sixteenth voltage being higher than the fourteenth voltage (FIG. 13A, VreadK > VrA).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Zainuddin into the method of Ogawa to include a verify test of a program operation. The ordinary artisan would have been motivated to modify Ogawa in the above manner for the purpose of determining if the programming of the memory cell is completed (Zainuddin, Col. 3, ll. 1-5).
Allowable Subject Matter
11. Claims 3-4 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
12. The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 3, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of the fifth voltage being higher than the fourth voltage. Claim 4 depends on claim 3.
Regarding claim 6, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of the eleventh voltage being lower than the tenth voltage.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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