DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on 06/11/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
3. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
4. Claims 1, 2, 5-13 and 16-19 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-7 of Patent No. 12,254,554. Although the conflicting claims are not identical, they are not patentably distinct from each other because they are essentially the same except that claims 1, 2, 5-13 and 16-19 of the instant application recites a current state of the computing system. However, Wilt (US 10,423,463 B1) teaches this limitation, as discussed below. Thus, claims 1, 2, 5-13 and 16-19 of the instant application is obvious in view of claims 1-7 of Patent No. 12,254,554.
5. Regarding claim 1, the application claim discloses A method comprising: detecting a set of shader programs to be compiled for an application executing using a first set of one or more processing devices of a computing system; obtaining a set of compiled shader programs by providing, based on a current state of the computing system, the set of shader programs to a second set of one or more processing devices for compilation; and causing the set of compiled shader programs to be executed using the first set of one or more processing devices. Claim 8 discloses The method of claim 1, further comprising: determining a first processing state associated with the first set of one or more processing devices in view of one or more characteristics associated with the set of shader programs; and determining whether the first processing state satisfies a processing state criterion associated with the application, wherein the second set of processing devices is identified to compile the set of shader programs responsive to determining that the determined first processing state does not satisfy the processing state criterion. Claim 1 of Patent No. 12,254,554 discloses A method comprising: detecting that a set of shader programs are to be compiled for an application executing at a computing system using a first set of processing devices; determining a first processing state associated with the first set of processing devices in view of one or more characteristics associated with the set of shader programs; determining whether the first processing state satisfies a processing state criterion associated with the application; responsive to determining that the first processing state satisfies the processing state criterion, identifying a second set of processing devices to compile the set of shader programs, wherein each of the second set of processing devices is different from any processing device of the first set of processing devices; providing the set of shader programs for compilation using the second set of processing devices in view of state data associated with the computing system to obtain a set of complied shader programs; and causing the set of compiled shader programs to be executed using the first set of processing devices. Regarding claims 1 and 8, the only difference is that claims 1 and 8 of the instant application recite “a current state of the computing system” and do not recite “each of the second set of processing devices is different from any processing device of the first set of processing devices;” and “state data associated with the computing system” while claim 1 of Patent No. 12,254,554 recites. For the additionally limitation, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wilt into Patent No. 12,254,554, in order to allow a single physical computing device to be shared among multiple users. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention by applicant to modify claim 1 of Patent No. 12,254,554 to include a current state of the computing system. (col. 17, lines 51-59) Therefore, the claims in the present application disclosing similar limitations with the claims in the Patent No. 12,254,554 recite.
6. The following table shows the claims of the current application being examined and the conflicting claims of Patent No. 12,254,554.
Current Application No.
19/075,010
Patent No.
12,254,554
1+8
1
2
7
5
4
6
2
7
3
9-11
4-6
12
1
13
7
16
4
17
2
18
1
19
7
The following table shows an example of the corresponding conflicting claims of the current application and Patent No. 12,254,554.
Current Application No.
18/917,192
Claims 1+8
Patent No.
12,254,554
Claim 1
A method comprising: detecting a set of shader programs to be compiled for an application executing using a first set of one or more processing devices of a computing system; (claim 1)
A method comprising: detecting that a set of shader programs are to be compiled for an application executing at a computing system using a first set of processing devices;
determining a first processing state associated with the first set of one or more processing devices in view of one or more characteristics associated with the set of shader programs; (claim 8)
determining a first processing state associated with the first set of processing devices in view of one or more characteristics associated with the set of shader programs;
and determining whether the first processing state satisfies a processing state criterion associated with the application, (claim 8)
determining whether the first processing state satisfies a processing state criterion associated with the application;
wherein the second set of processing devices is identified to compile the set of shader programs responsive to determining that the determined first processing state does not satisfy the processing state criterion. (claim 8)
responsive to determining that the first processing state satisfies the processing state criterion, identifying a second set of processing devices to compile the set of shader programs, wherein each of the second set of processing devices is different from any processing device of the first set of processing devices;
obtaining a set of compiled shader programs by providing, based on a current state of the computing system, the set of shader programs to a second set of one or more processing devices for compilation; (claim 1)
providing the set of shader programs for compilation using the second set of processing devices in view of state data associated with the computing system to obtain a set of complied shader programs;
and causing the set of compiled shader programs to be executed using the first set of one or more processing devices. (claim 1)
and causing the set of compiled shader programs to be executed using the first set of processing devices.
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
10. Claim(s) 1-5 10-16 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Munshi et al. (US 2017/0308364 A1) in view of Wilt (US 10,423,463 B1).
11. With reference to claim 1, Munshi teaches A method comprising: detecting a set of shader programs to be compiled for an application executing using a first set of one or more processing devices of a computing system; (“A method comprising: receiving a pre-compiled library, wherein the pre-compiled library is a post-compilation intermediate representation of code, the intermediate representation of code being suitable for a subsequent compilation into machine language for a plurality of different processing devices, and wherein the pre-compiled library comprises both graphics operations and non-graphics operations; compiling at least a portion of the pre-compiled library from the intermediate representation into a first binary file comprising both one or more kernels and one or more shaders that are directly executable by a first target processor; … responsive to detecting a request for the first kernel, retrieving the first kernel from the first binary file for execution by the first target processor;” claim 8 “AIR 522 may be compiled by separate compilers into binaries 526A-N. A first compiler (not shown) executing on CPU 520 may compile the AIR 522 into a binary 526A. Binary 526A may be targeted to GPU 530A, which may have a first type of micro-architecture. … Binaries 526A-N are representative of any number of binaries that may be generated and GPUs 530A-N are representative of any number of GPUs that may be included in the computing system 500. Binaries 526A-N may also include any number of kernels and shaders, and different kernels and shaders from source code 510 may be included within different binaries. For example, source code 510 may include a plurality of kernels and shaders. A first kernel or shader may be intended for execution on GPU 530A, and so the first kernel or shader may be compiled into binary 526A which targets GPU 530A.” [0046-0047]) Munshi also teaches obtaining a set of compiled shader programs by providing, the set of shader programs to a second set of one or more processing devices for compilation; (“compiling at least a portion of the pre-compiled library from the intermediate representation into a second binary file comprising both one or more kernels and one or more shaders that are directly executable by a second target processor, which is different from the first target processor, … responsive to detecting a request for the second kernel, retrieving the second kernel from the second binary file for execution by the second target processor.” claim 8 “a second compiler (not shown) executing on CPU 520 may compile the same AIR 522 into binary 526N. Binary 526N may be targeted to GPU 530N, which may have a second type of micro-architecture different from the first type of micro-architecture of GPU 530A. … A second kernel or shader from source code 510 may be intended for execution on GPU 530N, and so the second kernel or shader may be compiled into binary 526N which targets GPU 530N.” [0046-0047]) Munshi further teaches causing the set of compiled shader programs to be executed using the first set of one or more processing devices. (“Binary file 406 may be targeted to a specific target device, such as the GPU 420, and kernels and shaders may be retrieved from the binary and executed by the GPU 420. In some embodiments, at least some of the kernels and shaders may be executed by the CPU 410. Where multiple CPUs 410 or GPUs 420 are present in the end-user device, they may be of different types, and the kernels and shaders from a binary file 406 compiled for a first target device may not be executable on a second target device.” [0038])
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Munshi does not explicitly teach based on a current state of the computing system. This is what Wilt teaches (“FIG. 7 illustrates further aspects of the example system environment for computational task offloading for virtualized graphics processing, according to one embodiment. … the graphics driver 621 may determine if and/or when to offload one or more tasks based on the request 701 to the service 600. For example, the graphics driver 621 may offload particular types of tasks (e.g., shader or kernel compilation) that tend to be computationally intensive while not offloading other types of tasks. As another example, the graphics driver 621 may schedule the offloading and/or performing of tasks based on current or anticipated resource (e.g., CPU) usage.” col. 17, lines 6-59) Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wilt into Munshi, in order to allow a single physical computing device to be shared among multiple users.
12. With reference to claim 2, Munshi does not explicitly teach the current state of the computing system comprises at least one of a current pipeline state of the computing system, a current hardware state of the computing system, or a current driver state of the computing system. This is what Wilt teaches (“FIG. 7 illustrates further aspects of the example system environment for computational task offloading for virtualized graphics processing, according to one embodiment. … the graphics driver 621 may determine if and/or when to offload one or more tasks based on the request 701 to the service 600. For example, the graphics driver 621 may offload particular types of tasks (e.g., shader or kernel compilation) that tend to be computationally intensive while not offloading other types of tasks. As another example, the graphics driver 621 may schedule the offloading and/or performing of tasks based on current or anticipated resource (e.g., CPU) usage.” col. 17, lines 6-59) Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wilt into Munshi, in order to allow a single physical computing device to be shared among multiple users.
13. With reference to claim 3, Munshi does not explicitly teach retrieving information pertaining to the current state of the computing system from a memory associated with the computing system. This is what Wilt teaches (“FIG. 7 illustrates further aspects of the example system environment for computational task offloading for virtualized graphics processing, according to one embodiment. … the graphics driver 621 may determine if and/or when to offload one or more tasks based on the request 701 to the service 600. For example, the graphics driver 621 may offload particular types of tasks (e.g., shader or kernel compilation) that tend to be computationally intensive while not offloading other types of tasks. As another example, the graphics driver 621 may schedule the offloading and/or performing of tasks based on current or anticipated resource (e.g., CPU) usage.” col. 17, lines 6-59 “When a request to compile a shader or kernel into microcode is received by the service 900, it may determine whether suitable compiled microcode is stored in the cache 950. The cache 950 may be implemented using any suitable memory or storage technologies and may be locally accessible or remote relative to the compute instances that implement the microcode compilation service 900. … If the requested microcode is available in the cache 950 (e.g., if the cache contains microcode whose hash matches the hash of the requested program code and target GPU type), then that microcode may be retrieved from the cache and provided by the microcode compilation service 900 to the graphics server 420 for execution on the virtual GPU 151B.” col. 20, lines 38-64) Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wilt into Munshi, in order to allow a single physical computing device to be shared among multiple users.
14. With reference to claim 4, Munshi does not explicitly teach the information pertaining to the current state of the computing system is updated according to at least one of a state update protocol associated with the computing system or in response to receiving a request to access the application. This is what Wilt teaches (“FIG. 7 illustrates further aspects of the example system environment for computational task offloading for virtualized graphics processing, according to one embodiment. … the graphics driver 621 may determine if and/or when to offload one or more tasks based on the request 701 to the service 600. For example, the graphics driver 621 may offload particular types of tasks (e.g., shader or kernel compilation) that tend to be computationally intensive while not offloading other types of tasks. As another example, the graphics driver 621 may schedule the offloading and/or performing of tasks based on current or anticipated resource (e.g., CPU) usage. A task may be offloaded to a service 600 to which the graphics driver 621 sends a task request 702 to perform the task. The service 600 may generally represent a computational offload service or, in the case of microcode compilation, a microcode compilation service. The service 600 may be implemented using computing resources (e.g., servers) of the same multi-tenant provider network 100 that includes the virtual compute instance 141B and virtual GPU 151B. In one embodiment, the computing resources that perform the service 600 may be located close to the graphics server 420 (e.g., in the same data center or rack) in order to reduce latency between the two components. By offloading computationally intensive tasks from a graphics server 420 that implements the virtual GPU 151B, the graphics server may be optimized for processing using the GPU (e.g., graphics processing and/or GPGPU computing) and not for the offloaded tasks. For example, the graphics server 420 may be configured or selected with less capable and less expensive CPU resources than would otherwise be used to perform the offloaded tasks. Additionally, the graphics driver 621 and the external service 600 may be updated independently of one another.” col. 17, line 6-col. 18, line 14) Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wilt into Munshi, in order to allow a single physical computing device to be shared among multiple users.
15. With reference to claim 5, Munshi teaches providing the set of shader programs to the second set of processing devices for compilation is further based on one or more characteristics of the set of shader programs. (“compiling at least a portion of the pre-compiled library from the intermediate representation into a second binary file comprising both one or more kernels and one or more shaders that are directly executable by a second target processor, which is different from the first target processor, … responsive to detecting a request for the second kernel, retrieving the second kernel from the second binary file for execution by the second target processor.” claim 8 “The source code for application 210 is compiled on developer system 220 into a form (described in more detail below) that can be executed on either of end-user device 230A or 230B, even though end-user device 230A contains multiple processors 240, each of which has multiple parallel processing elements 250, while end-user device 230B contains only a single processor 240 with a different number of parallel processing elements 250. In this embodiment, the processors 240 on which the application 210 eventually executes may have different architectures and operating characteristics. The processors 240 may be any desired type of processor, e.g., CPUs, GPUs, field programmable gate arrays, or application-specific integrated circuits, as long as an appropriate driver is available for that type of processor 240.” [0029] “a second compiler (not shown) executing on CPU 520 may compile the same AIR 522 into binary 526N. Binary 526N may be targeted to GPU 530N, which may have a second type of micro-architecture different from the first type of micro-architecture of GPU 530A. … A second kernel or shader from source code 510 may be intended for execution on GPU 530N, and so the second kernel or shader may be compiled into binary 526N which targets GPU 530N.” [0046-0047])
16. With reference to claim 10, Munshi teaches the first set of one or more processing devices comprises a first processing unit of the computing system and the second set of one or more processing devices comprises at least one of a second processing unit of the computing system that is separate from the first processing unit or a third processing unit of a processing system that is remote from the computing system. (“the pre-compiled library comprises both graphics operations and non-graphics operations; compiling at least a portion of the pre-compiled library from the intermediate representation into a first binary file comprising both one or more kernels and one or more shaders that are directly executable by a first target processor; compiling at least a portion of the pre-compiled library from the intermediate representation into a second binary file comprising both one or more kernels and one or more shaders that are directly executable by a second target processor, which is different from the first target processor, …responsive to detecting a request for the first kernel, retrieving the first kernel from the first binary file for execution by the first target processor; and responsive to detecting a request for the second kernel, retrieving the second kernel from the second binary file for execution by the second target processor” claim 8 “A first compiler (not shown) executing on CPU 520 may compile the AIR 522 into a binary 526A. Binary 526A may be targeted to GPU 530A, which may have a first type of micro-architecture. Similarly, a second compiler (not shown) executing on CPU 520 may compile the same AIR 522 into binary 526N. Binary 526N may be targeted to GPU 530N, which may have a second type of micro-architecture different from the first type of micro-architecture of GPU 530A.” [0046])
17. With reference to claim 11, Munshi does not explicitly teach the third processing unit comprises a data processing unit of a data center. This is what Wilt teaches (“FIG. 1 illustrates an example system environment for virtualizing graphics processing in a provider network, according to one embodiment. Clients of a provider network 100 may use computing devices such as client devices 180A-180N to access an elastic graphics service 110 and other resources offered by the provider network. The client devices 180A-180N may be coupled to the provider network 100 via one or more networks 190. The provider network 100 may provide compute virtualization 140 such that a plurality of virtual compute instances 141A-141Z may be implemented using a plurality of physical compute instances 142A-142N. The virtual compute instances 141A-141Z may also be referred to herein as virtual machines (VMs). Similarly, the provider network 100 may provide GPU virtualization 150 such that a plurality of virtual GPUs 151A-151Z may be implemented using a plurality of physical GPUs 152A-152N.” col. 3, lines 13-29 “Provider network 100 may include numerous data centers hosting various resource pools, such as collections of physical and/or virtualized computer servers, storage devices, networking equipment and the like (e.g., implemented using computing system 3000 described below with regard to FIG. 12), needed to implement and distribute the infrastructure and services offered by the provider network 100.” col. 4, lines 44-51) Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wilt into Munshi, in order to allow a single physical computing device to be shared among multiple users.
18. Claim 12 is similar in scope to the claim 1, and thus is rejected under similar rationale. Munshi additionally teaches A system comprising: a processing device to perform operations (“computing system 100 also includes a system memory 140 that may be accessed by CPU 110 and GPU 130. In various embodiments, computing system 100 may comprise a supercomputer, a desktop computer, a laptop computer, a video-game console, an embedded device, a handheld device (e.g., a mobile telephone, smart phone, MP3 player, a camera, a GPS device, or other mobile device), or any other device that includes or is configured to include a GPU.” [0023] “Source code 510 may represent any number of libraries and kernels and shaders that may be utilized by system 500. In one embodiment, source code 510 may be compiled into AIR 522. AIR 522 may be the same for GPUs 530A-N.” [0046])
19. Claims 13-16 are similar in scope to the claims 2-5, and they are rejected under similar rationale.
20. Claim 18 is similar in scope to the claim 1, and thus is rejected under similar rationale. Munshi additionally teaches One or more processors comprising processing circuitry (“computing system 100 also includes a system memory 140 that may be accessed by CPU 110 and GPU 130. In various embodiments, computing system 100 may comprise a supercomputer, a desktop computer, a laptop computer, a video-game console, an embedded device, a handheld device (e.g., a mobile telephone, smart phone, MP3 player, a camera, a GPS device, or other mobile device), or any other device that includes or is configured to include a GPU.” [0023] “Host application 210 may be programmed to execute on any of end-user devices 230A/230B. The source code for application 210 is compiled on developer system 220 into a form (described in more detail below) that can be executed on either of end-user device 230A or 230B, even though end-user device 230A contains multiple processors 240, each of which has multiple parallel processing elements 250, while end-user device 230B contains only a single processor 240 with a different number of parallel processing elements 250. In this embodiment, the processors 240 on which the application 210 eventually executes may have different architectures and operating characteristics. The processors 240 may be any desired type of processor, e.g., CPUs, GPUs, field programmable gate arrays, or application-specific integrated circuits, as long as an appropriate driver is available for that type of processor 240.” [0029] “Source code 510 may represent any number of libraries and kernels and shaders that may be utilized by system 500. In one embodiment, source code 510 may be compiled into AIR 522. AIR 522 may be the same for GPUs 530A-N.” [0046])
21. Claims 19 and 20 are similar in scope to the claims 2 and 3, and they are rejected under similar rationale.
22. Claim(s) 6, 7, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Munshi et al. (US 2017/0308364 A1) and Wilt (US 10,423,463 B1), as applied to claims 1 and 12 above, and further in view of Panneer et al. (US 2018/0286008 A1).
23. With reference to claim 6, Munshi teaches prior to detecting that the set of shader programs are to be compiled for the application executing using the first set of one or more processing devices of the computing system, compiling the set of shader programs using the first set of one or more processing devices to generate an initial set of compiled shader programs, (“front-end phase 310 may be configured to allow multiple source languages, such as Language A 312, Language B 314, Metal 316, or any other language 318 to be compiled into the IR and optimized by the optimizer 320. In some embodiments, separate front-end phases 310 are provided for each source code language; in other embodiments, a single front-end phase 310 may be used to compile multiple source code languages into the IR 322.” [0034])
The combination of Munshi and Wilt does not explicitly teach the set of compiled shader programs obtained by providing the set of shader programs to the second set of one or more processing devices for compilation is an optimized version of the initial set of compiled shader programs. This is what Panneer teaches (“the system 100 may use a pipeline (e.g., refer to FIGS. 2, 8, and 9) to process the shader 152. As such, the shader 152 may be patched (resulting in the patched shader 156) while the shader 152 is in the pipeline. In executing the instructions 121, the processor 102 and/or the external graphics processor 112 further determine whether portions of the shader 152 can be optimized and either (1) patches the shader 152 based on the determination that portions of the shader 152 can be optimized, resulting in the patched shader 156; or (2) does not patch the shader 152 based on the determination that portions of the shader 152 can not be optimized. In general, the processor 102 and/or the external graphics processor 112 generates the patched shader 156 by replacing portions of the shader 152 with one or more optimized portions. In general, the shader 152 is patched after it has been compiled. With some examples, the shader 152 may be patched while the shader 152 is in a pipeline. In some examples, the shader 152 is patched after it has been executed. As such, the patched shader 156 may be used on subsequent executions (e.g., draw calls, or the like).” [0028-0029]) Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Panneer into the combination of Munshi and Wilt, in order to cap frame rates to increase power efficiency or to upcap frame rates to increase performance.
24. With reference to claim 7, the combination of Munshi and Wilt does not explicitly teach providing a set of optimization parameters associated with the application with the set of shader programs for compilation using the second set of one or more processing devices, wherein the set of compiled shader programs is generated based on the set of optimization parameters. This is what Panneer teaches (“the system 100 may use a pipeline (e.g., refer to FIGS. 2, 8, and 9) to process the shader 152. As such, the shader 152 may be patched (resulting in the patched shader 156) while the shader 152 is in the pipeline. In executing the instructions 121, the processor 102 and/or the external graphics processor 112 further determine whether portions of the shader 152 can be optimized and either (1) patches the shader 152 based on the determination that portions of the shader 152 can be optimized, resulting in the patched shader 156;” [0028] “a processor (e.g., the processor 102, the graphics processor 108, or the external graphics processor 112, or the like) determines whether portions of a compiled shader can be optimized based on a global constant buffer and one or more patching parameters. For example, the shader patcher 1212 may determine whether portions of the shader 152 can be optimized based on the global constant buffer 154 and a patching parameter.” [0056]) Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Panneer into the combination of Munshi and Wilt, in order to cap frame rates to increase power efficiency or to upcap frame rates to increase performance.
25. Claim 17 is similar in scope to the claim 6, and thus is rejected under similar rationale.
Conclusion
26. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michelle Chin whose telephone number is (571)270-3697. The examiner can normally be reached on Monday-Friday 8:00 AM-4:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Kent Chang can be reached on (571)272-7667. The fax phone number for the organization where this application or proceeding is assigned is (571)273-8300.
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/MICHELLE CHIN/
Primary Examiner, Art Unit 2614
Prosecution Insights