DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application filed 03/10/2025. Claims 1-25 are pending in the Application, of which Claims 1, 12 and 18 are independent.
Continuity Priority information
The present Application 19075572 filed 03/10/2025 Claims Priority from Provisional Application 63568100, filed 03/21/2024.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature “switching the register” as recited in the claims must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. The drawings show switching component 430 that may be configured as or otherwise support a means for switching the register, however the drawings fail to show the functional relation between the register and the switching component.
According to the specification, para. [0103] A switching component (e.g., a transistor) discussed herein may be a field-effect transistor (FET), and may include a source (e.g., a source terminal), a drain (e.g., a drain terminal), a channel between the source and drain, and a gate (e.g., a gate terminal). However, the drawings do not show the (FET) with respect to switching the register.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cook et al. (U.S. Patent No. 5,872,794) Pub. Date:1999-02-16.
Regarding independent Claims 1, 12 and 18, Cook discloses Flash EPROM Control With Embedded Pulse Timer And With Built-in Signature Analysis, comprising:
FIG. 5 is a diagram illustrating the Built-In-Logic-Block-Observation registers of FIG. 4; Depending on the state of the control inputs LOAD, RLOAD, SCAN, FEED.sub.--, RESET, HOLD.sub.-- and LFSR.sub.-- TIMER of FIG. 5; the Built-In-Logic-Block-Observation registers BILBO operate in one of eight modes as listed in TABLE 2.
operating a register comprising a plurality of flip-flops as a shift register circuit; TABLE 2. Scan-Shift 0 X 1 0 0 0 X. In the Scan-Shift Mode of operation, scan data SCAN.sub.-- IN is clocked through the registers REG and exits the last master/slave latch M/SL at terminal SCAN.sub.-- OUT. The data stored in the shadow latch SHL is held constant, as illustrated in FIG. 5.
switching the register to operate as a multiple-input signal register (MISR) circuit associated with data received from a host device;
TABLE 2. LFSR Signature 1 1 0 0 0 0 0. In the Linear-Feedback-Shift-Register Signature Mode of operation, the registers REG are configured as an Multiple-Input-Shift-Register MISR while the data stored in the shadow latches SHL are held constant.
switching the register to operate as a linear-feedback shift register (LFSR) circuit, associated with data read from a memory device; TABLE 2. LFSR Timer 0 X 0 0 0 0 1. In the Linear-Feedback-Shift-Register LFSR Timer Mode of operation, the registers REG are configured to count in a pseudo-random manner while the data stored in the shadow latches SHL are held constant. Each register REG includes a multiplexer MUX, an AND circuit AND, a NOR circuit NOR, an exclusive OR circuit XOR and a master/slave latch M/SL connected as shown in FIG. 5.
Regarding Claims 2, 13, 19, Cook discloses wherein the first data input comprises a seed for the plurality of flip-flops. In the Scan-Shift Mode of operation, scan data SCAN.sub.-- IN is clocked through the registers, FIG. 5.
Regarding Claims 3, 6, 20, 23, Cook discloses switching the register to operate as the shift register circuit; In the Scan-Shift Mode of operation, scan data SCAN.sub.-- IN is clocked through the registers REG and exits the last master/slave latch M/SL at terminal SCAN.sub.-- OUT. The data stored in the shadow latch SHL is held constant.
Regarding Claims 4, 5, 21, Cook discloses switching the register to operate as the LFSR circuit comprises disabling the second data input to the register; TABLE 2. LFSR Timer 0 X 0 0 0 0 1. In the Linear-Feedback-Shift-Register LFSR Timer Mode of operation, the registers REG are configured to count in a pseudo-random manner while the data stored in the shadow latches SHL are held constant. Each register REG includes a multiplexer MUX, an AND circuit AND, a NOR circuit NOR, an exclusive OR circuit XOR and a master/slave latch M/SL connected as shown in FIG. 5.
Regarding Claims 7 and 24, Cook discloses operating the memory system as the MISR circuit; In the Linear-Feedback-Shift-Register LFSR Signature Mode of operation, the registers REG are configured as an Multiple-Input-Shift-Register MISR while the data stored in the shadow latches SHL are held constant.
Regarding Claims 8, 22, 25, Cook discloses receive the first data input according to the first clock signal at the first frequency. In the Parallel-Load-Hold Mode of operation, data from the Control-Read-Only-Memory CROM are loaded into the master/slave latches M/SL at terminals ROM1-ROMN of FIG. 5 while the data in the shadow latches SHL are held constant.
Regarding Claims 9, 10, 11, Cook discloses switching the register to operate as the LFSR circuit; In the Linear-Feedback-Shift-Register LFSR Timer Mode of operation, the registers REG are configured to count in a pseudo-random manner while the data stored in the shadow latches SHL are held constant. Each register REG includes a multiplexer MUX, an AND circuit AND, a NOR circuit NOR, an exclusive OR circuit XOR and a master/slave latch M/SL connected as shown in FIG. 5.
Regarding Claims 14, 16, 17, Cook discloses the MISR circuit is associated with a first testing operation associated with data received from a host device, and the LFSR circuit is associated with a second testing operation associated with data read from a memory device. In order to verify the contents of the Control-Read-Only-Memory CROM, the Built-In-Logic-Block-Observation registers BILBO are placed in the Linear-Feedback-Shift-Register LFSR Signature Mode. While configured as an Multiple-Input-Shift-Register MISR, the Control-Read-Only-Memory CROM is sequenced through all addresses and data from the Control-Read-Only-Memory CROM are exclusive OR'd with data from the prior master/slave latch. Once the entire Control-Read-Only-Memory CROM has been loaded, the Built-In-Logic-Block-Observation registers BILBO are placed in the Scan-Shift Mode and the contents of the Built-In-Logic-Block-Observation registers BILBO are scanned out for verification.
Regarding Claim 15, Cook discloses wherein a first flip-flop of is cascaded with a second flip-flop. As illustrated in FIG. 3, prior-art scannable registers SCRG includes a scan input SCAN.sub.-- IN and inputs SCAN, RESET and HOLD.sub.-- that provide instructions to the scannable registers SCRG from the control-Read-Only-Memory CROM. Also, output Shift-Register-Latches SRL are used for scanning out the contents of the Control-Read-Only-Memory CROM. Each output Shift-Register-Latch SRL includes a multiplexer MUX and a master/slave latch M/SL, as shown in FIG. 3.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: August 26, 2026
Non-Final Rejection 20260825
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
Prosecution Insights