DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is the initial Office Action based on the application filed 03/11/2025. Claims 1-20 are presented for examination and have been considered below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1–5, 8, 10-14, 17, 19 and 20 are rejected under 35 U.S.C. §103 as being unpatentable over Kudekar et al., WO 2017/218667 A1 (“Kudekar”).
Claim 1: Kudekar teaches a method of encoding, comprising:
performing low-density parity-check (LDPC) encoding on a bit sequence to obtain an encoded sequence (e.g., Kudekar teaches that the transmitting device generates lifted LDPC codes and “encodes a set of information bits” based on a first or second lifted LDPC code to produce a codeword. See ¶[0112]), the check matrix set comprising a first check matrix and a second check matrix (e.g., ¶[0112] teaches a “first lifted PCM corresponding to the first lifted LDPC code”; and a “second lifted PCM corresponding to a second lifted LDPC code.” Thus, the first and second lifted PCMs reasonably correspond to the claimed first and second check matrices), wherein a first expansion factor corresponding to the first check matrix is different from a second expansion factor corresponding to the second check matrix (e.g., Kudekar identifies Z as the lifting size and explains that different values of Z may be used for the same base graph to achieve different block lengths. See ¶¶[0106]–[0107]. For example, Kudekar discloses families containing different lifting sizes such as: {16, 20, 24, 28}, {32, 40, 48, 56}, … {512, 640, 768, 896}. See ¶¶[0116]–[0118]. Thus, Kudekar teaches different expansion/lifting factors for matrices derived from the same base matrix.), the first check matrix is a check matrix obtained by expanding a base matrix using a first set of circular shift values (e.g., Paragraph [0106] explains that LDPC codes are lifted by taking Z copies of a base PCM and assigning permutations according to integer lifting values, where the permutation is a cyclic permutation and the integer represents the corresponding cyclic shift. More specifically, ¶[0112] teaches generating the first lifted LDPC code by applying the first set of lifting values to interconnect edges in Z copies of a base PCM to obtain the first lifted PCM. Accordingly, Kudekar’s “lifting values” correspond to the claimed circular shift values.), the second check matrix is a check matrix obtained by expanding the base matrix using a second set of circular shift values (e.g., Paragraph [0112] expressly determines a second set of lifting values for generating a second lifted PCM corresponding to a second lifting size. ), and the second set of circular shift values are circular shift values obtained by using the first set of circular shift values (e.g., Paragraph [0112] determines the second set of lifting values: “based on the first lifted PCM and the first set of lifting values.” Kudekar further explains that the PCM for another lifting size can be obtained by performing an operation on the lifting values associated with the PCM for the largest lifting size, including a modulo operation with respect to the desired lifting size.); and
transmitting a data packet obtained based on the encoded sequence (e.g., Paragraph [0112] states that the transmitting device produces a codeword and transmits the codeword via a wireless medium).
Kudekar indisputably teaches multiple lifted PCMs corresponding to multiple lifting sizes, but it does not appear to use the exact concept/terminology of selecting a matrix from a stored “check matrix set” as claimed. However, Kudekar expressly teaches a family of LDPC codes obtained from a single base graph/PCM using a plurality of lifting sizes and corresponding lifting values. See ¶¶[0114]–[0118]. Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to organize or maintain Kudekar’s multiple lifted PCMs as a check-matrix set from which an appropriate PCM is selected according to the desired block length. Kudekar itself explains that different Z values are used to achieve different block lengths.
Claim 2: Kudekar teaches the method according to claim 1, wherein respective circular shift values of the first set of circular shift values and the second set of circular shift values meet a same modulo operation relationship. For instance, Kudekar teaches that respective circular shift values of the first and second sets meet the same modulo-operation relationship, wherein PCMs for other members of a family are obtained based on the lifting values of a PCM having a different lifting size by performing a modulo operation with respect to the desired lifting size (¶¶[0119]–[0121]; see also ¶[0124]). Kudekar identifies the lifting values as integer values representing cyclic shifts (¶[0106]).
Claim 3: Kudekar teaches the method according to claim 2, wherein the second set of circular shift values are circular shift values obtained by performing modulo processing on the first set of circular shift values and the second expansion factor. For instance, Kudekar teaches obtaining the second set of circular shift values by performing modulo processing using the first set of circular shift values and the second expansion factor, wherein an original lifting value s is reduced modulo the desired lifting size Z; for example, Kudekar expressly teaches 678 mod 128 = 38, with 38 specifying the cyclic shift of the corresponding 128×128 circulant matrix (¶[0121]; see also ¶¶[0119], [0124]).
Claim 8: Kudekar teaches the method according to claim 1, wherein the method is applied to a wireless local area network system and/or an ultra-wideband UWB-based wireless personal local area network system. For instance, Kudekar teaches wherein the method is applied to a wireless local area network system, wherein Kudekar expressly teaches quasi-cyclic IEEE 802.11 LDPC codes (¶¶[0031], [0091]) and further teaches that, in 802.11n, a unique PCM is defined for each code rate and blocklength, including twelve PCMs corresponding to combinations of four code rates and three codeblock lengths (¶[0107]).
As per claim 4, Kudekar teaches the method according to claim 1, wherein the check-matrix arrangement may comprise more than two lifted parity-check matrices. Kudekar describes a family of LDPC codes generated from a single base graph or PCM using a plurality of lifting sizes. For example, ¶[0132] teaches “a set [of] liftings Z for a single base graph or PCM” to obtain a family of LDPC codes, and ¶[0133] teaches using a base graph together with an increasing series of lifting sizes Z1, Z2, … Zn. Thus, Kudekar teaches generating at least first, second, and third lifted check matrices from a common base matrix. Kudekar further teaches that the respective lifted matrices are obtained from the same base graph using corresponding integer lifting values, which represent cyclic shifts. Paragraph [0127] explains that a base PCM may be copied and interconnected using cyclic permutations or circulant permutation matrices, and that each edge is associated with an integer lifting value representing the cyclic shift of an identity matrix. Kudekar further teaches that associated lifting values may be reused among different liftings in a cluster. ¶[0135]. Kudekar also teaches deriving lifting values for one lifted PCM from lifting values associated with another lifted PCM. Paragraph [0119] teaches that PCMs for other members of a family may be obtained based on the PCM for the largest lifting and by performing an operation involving the lifting values and the desired lifting size. The disclosed operations include a modulo operation. Paragraph [0121] provides a specific example in which an integer lifting value of 678 associated with a larger lifting is converted for a lifting size Z=128 by performing 678 mod 128 = 38, with the resulting value 38 defining the cyclic shift for the corresponding circulant matrix. Accordingly, Kudekar teaches obtaining a further set of circular shift values using another set of circular shift values.
Kudekar, however, does not expressly teach in its common-base-matrix embodiment that the first expansion factor is K times the third expansion factor, where K is specifically an odd integer greater than one. Kudekar nevertheless expressly discloses lifting sizes having precisely such a relationship. In particular, Kudekar teaches lifting sizes Z = 27, 54, and 81 in the context of 802.11 LDPC codes. ¶¶[0108], [0129]. Thus, Kudekar expressly teaches lifting sizes 81 and 27 satisfying: 81 = 3 × 27, where K = 3, which is an odd integer greater than one. Kudekar does not expressly state that the disclosed 81 and 27 lifting sizes are applied to the same base PCM in the particular 802.11 example. Indeed, ¶[0129] explains that the conventional 802.11 arrangement defines a unique base PCM for each code-rate/lift-value tuple. However, Kudekar separately teaches replacing such an arrangement with a more compact construction in which the same base graph is reused across multiple lifting sizes. Paragraph [0128] expressly teaches that, when the base graph is reused without alteration, different lifting values provide a family of codes having different blocklengths. Paragraphs [0131]–[0133] similarly teach associating a single base matrix with a cluster or series of different lifting sizes. It therefore would have been obvious to one of ordinary skill in the art, in view of Kudekar’s own teachings, to employ lifting sizes having the disclosed 81-to-27 relationship when generating multiple lifted PCMs from the same base graph. Kudekar expressly teaches both: (1) using multiple lifting sizes with a common base graph to obtain a family of LDPC codes, and (2) lifting sizes 27, 54, and 81, including the relationship 81 = 3×27. See ¶¶[0129]. Applying the known lifting-size relationship to Kudekar’s common-base-graph technique would have amounted to using a known parameter relationship in the expressly taught multi-lifting architecture, predictably producing corresponding lifted parity-check matrices having different blocklengths. The motivation for doing so is also supplied by Kudekar. Kudekar explains that defining a separate PCM for each code rate and blocklength results in increased description complexity and memory requirements, and that techniques for compactly describing multiple PCMs are therefore desirable. See ¶¶[0109]–[0111], [0129]–[0132]. Reusing the same base graph across the known lifting sizes would therefore have furthered Kudekar’s expressly stated objective of reducing PCM description complexity while supporting multiple blocklengths. Accordingly, it would have been obvious to modify Kudekar’s common-base-matrix embodiment to use a first lifting/expansion factor of 81 and a third lifting/expansion factor of 27, such that the first expansion factor is K times the third expansion factor, where K=3 is an odd integer greater than one, thereby arriving at the subject matter of claim 4.
Claim 5: Kudekar teaches the method according to claim 4, wherein the second expansion factor is F times the third expansion factor, and F is an even number greater than 1. For instance, Kudekar further teaches lifting sizes 27, 54, and 81, thereby teaching a second lifting/expansion factor of 54 that is twice a third lifting/expansion factor of 27, such that F=2 is an even number greater than one. See ¶¶[0129].
Claims 10-14, 17, 19 and 20 recite apparatus that substantially correspond to the device limitations of claims 1-5, and 8 above. Accordingly, claims 10-14, 17, 19 and 20 are rejected under 35 U.S.C. § 103 for substantially the same reasons set forth above with respect to the corresponding device claims.
Claim(s) 6, 7, 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kudekar as applied to claim 5 above, and further in view of IEEE C802.20-05/73.
Claim 6: Kudekar teaches the method according to claim 5, but fails to teach that the first expansion factor is 102, the second expansion factor is 68, and the third expansion factor is 34. However, IEEE C802.20-05/73 teaches QC-LDPC parity-check matrices expanded from a base matrix using z×z circular permutation matrices, where z is a positive integer. See Section 4.3.1. It further expressly teaches that different block sizes are flexibly supported through selection of the expansion factor and that expansion by a factor n expands the z×z circular-shift matrices into nz×nz circular-shift matrices while conserving the shift values, thereby expanding the code length by the same factor n. EE C802.20-05/73, however, teaches that LDPC codes may flexibly support different block sizes by varying the expansion factor and expressly teaches that increasing the expansion factor predictably increases the code length by the corresponding factor. C802.20-05-73.pdf IEEE further teaches that various block sizes are accommodated using the fundamental LDPC codes, with matrix dimension n representing the length of the code. C802.20-05-73.pdf IEEE additionally expressly identifies 2040 bits as a suitable LDPC block size, together with numerous neighboring block sizes, evidencing that codeword/block length was a selectable system parameter. Thus, the prior art recognized the expansion factor as a parameter that may be varied to obtain a desired LDPC block size and recognized the predictable relationship between expansion factor and resulting code length. Accordingly, the expansion factor constitutes a known result-effective variable. It therefore would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to select a different workable base lifting/expansion factor in Kudekar’s disclosed 3:2:1 family in accordance with the desired block size. Selecting a third expansion factor of 34, instead of Kudekar’s exemplary 27, would predictably result, using Kudekar’s respective odd and even multiplication relationships, in: 3 × 34 = 102, and 2 × 34 = 68. Such selection would have amounted to routine optimization of the known expansion-factor parameter to obtain a desired code/block size, with a reasonable expectation of success because IEEE expressly teaches that z may be a positive integer and that changing the expansion factor predictably scales the expanded matrix and corresponding code length while retaining the circular-shift structure.
Claim 7: Kudekar teaches the method according to claim 5, but fails to teach that an encoded sequence corresponding to the first check matrix comprises a code word with a code length of 2040 bits, an encoded sequence corresponding to the second check matrix comprises a code word with a code length of 1360 bits, and an encoded sequence corresponding to the third check matrix comprises a code word with a code length of 680 bits. However, EE C802.20-05/73, however, teaches that LDPC codes may flexibly support different block sizes by varying the expansion factor and expressly teaches that increasing the expansion factor predictably increases the code length by the corresponding factor. See Section 4.3.1. It further teaches that various block sizes are accommodated using the fundamental LDPC codes, with matrix dimension n representing the length of the code. It additionally expressly identifies 2040 bits as a suitable LDPC block size, together with numerous neighboring block sizes, evidencing that codeword/block length was a selectable system parameter. See Table 4-5. It therefore would have been obvious to one of ordinary skill in the art to select the lifting factors and corresponding codeword lengths according to the desired supported packet/block size. Upon selecting the 3:2:1 lifting factors 102, 68, and 34 as discussed with respect to claim 6, the POSITA would have predictably selected corresponding code lengths maintaining the same proportional relationship, including 2040, 1360, and 680 bits, where each code length is twenty times its corresponding expansion factor. The selection of those particular numerical code lengths would have constituted routine optimization of a known result-effective parameter because the prior art expressly teaches both (1) varying LDPC expansion factors to accommodate different block sizes and (2) a predictable proportional relationship between expansion factor and resulting code length. No different operating principle results from the claimed numerical values.
Claims 15 and 16 recite apparatus that substantially correspond to the device limitations of claims 6, and 7 respectively. Accordingly, claims 15 and 16 are rejected under 35 U.S.C. § 103 for substantially the same reasons set forth above with respect to the corresponding device claims.
Claim(s) 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kudekar as applied to claim 5 above, and further in view of Vila Casado et al. “Multiple Rate Low-Density Parity-Check Codes with Constant Blocklength.”
Claim 9: Kudekar teaches the method according to claim 1, but fails to teach that the base matrix comprises H rows or M columns of the following (12x22) matrix:101001000110000000000001110110011000000000110001011001100000000111111001100110000000110110111000011000000001000100100001000000100000000000000100000101000001011000010000100000010000000001000000100010000010000100101000000010001000010101110000000000000001 is an integer from 1 to 12, and M is an integer from 1 to 22.
However, Vila Casado teaches specific binary LDPC parity-check matrix structures and expressly teaches deriving higher-rate LDPC matrices from a common “mother” LDPC matrix. Section II explains that higher-rate codes are generated by reducing the number of rows in the parity-check matrix of the mother code and by linearly combining rows. More particularly, Equation (3) of Vila Casado discloses the following two 12-element binary LDPC vectors: 111011101110 and 101110111011. These binary vectors correspond exactly to the first and second 12-element column patterns of the matrix recited in claim 9:
claimed column 1 = 111011101110
claimed column 2 = 101110111011
Vila Casado further teaches that LDPC matrices are deliberately designed by selecting matrix connectivity patterns to achieve suitable graph properties. Section III states that an LDPC matrix is constructed column by column, with each generated column required to satisfy specified graph constraints for the mother code and effective codes. More specifically, Vila Casado explains that a column is generated and evaluated with respect to cycle and stopping-set constraints, and that this process is performed for all columns, beginning with columns having the lowest degree. Accordingly, Vila Casado demonstrates that the particular placement of 1s and 0s in an LDPC matrix was a known design variable selected according to known graph-conditioning criteria, rather than a fixed or unique matrix topology. It therefore would have been obvious to one of ordinary skill in the art to employ known LDPC connectivity patterns, such as the expressly disclosed 12-element patterns of Vila Casado, in selecting the corresponding rows/columns of Kudekar’s base matrix, in order to obtain an LDPC matrix having desirable graph properties such as reduced harmful cycles, larger stopping sets, and improved error-floor behavior. Vila Casado expressly identifies such graph properties as design objectives for LDPC matrices.
Claim 18 recites apparatus that substantially correspond to the device limitations of claim 9. Accordingly, claim 18 is rejected under 35 U.S.C. § 103 for substantially the same reasons set forth above with respect to the corresponding device claims.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 8/17/2026
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