DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, 6-10, 12-13, 15, and 17-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Iwayama (US 20240145001 A1).
The applied reference has a common applicant/assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1, Iwayama discloses:
A storage device comprising (Claim 1: A memory device):
a first wire extending in a first direction (Claim 1);
a second wire extending in a second direction that intersects the first direction (Claim 1);
a memory cell connected between the first wire and the second wire, wherein the memory cell includes a variable resistance memory element capable of exhibiting both a first resistance state and a second resistance state having a greater resistance than the first resistance state, and the memory cell further includes a switching element connected in series to the variable resistance memory element, the switching element having characteristics of transitioning from an OFF state to an ON state when a voltage applied between two terminals of the switching element increases to a first voltage, and of transitioning from the ON state to the OFF state when the voltage applied between the two terminals decreases to a second voltage lower than the first voltage (Claim 1); and
a determination operation controller configured to (Claim 1):
change a voltage of the first wire at a first ON state setting time point during a first read period, to set the switching element to the ON state while the second wire is set to a floating state, and obtain a voltage to be determined that is applied between the first wire and the second wire when a first time period elapses since the first ON state setting time point (Claim 1);
set the variable resistance memory element to one of the first resistance state and the second resistance state as a reference resistance state during a write period after the first read period (Claim 1);
change the voltage of the first wire at a second ON state setting time point during a second read period after the write period, to set the switching element to the ON state while the second wire is set to the floating state, and obtain a reference voltage applied between the first wire and the second wire when a second time period, which is different from the first time period, elapses since the second ON state setting time point (Claim 1); and
determine, based on a voltage difference between the voltage to be determined and the reference voltage, a resistance state to be determined that the variable resistance memory element was set to before the first read period (Claim 1).
Claim 12 is a method claim with limitations correlating with the limitations associated with apparatus in claim 1. Thereby, Iwayama discloses the limitations of claim 12 as set forth in the anticipation rejection of claim 1 above.
Regarding claims 2 and 13, Iwayama discloses:
in a case where the reference resistance state is the first resistance state (para. [0083]: “In the present example, the low resistance state is set as the reference resistance state (S18, S19).”; FIGs. 8-9):
determine that the resistance state to be determined is the second resistance state if the voltage difference between the voltage to be determined and the reference voltage is larger than a predetermined voltage difference, and determine that the resistance state to be determined is the first resistance state if the voltage difference between the voltage to be determined and the reference voltage is smaller than the predetermined voltage difference (para. [0092-0093]; FIG. 8: steps S22-S24).
Regarding claims 4 and 15, Iwayama discloses:
in a case where the reference resistance state is the first resistance state, the first time period and the second time period are set so that the first time period is shorter than the second time period (para. [0119], FIG. 10: step S42; FIG. 11: the determination target votlage V11B is sampled at t1 and the reference voltage V22B is sampled at t2; see also para. [0131]).
Regarding claims 6 and 17, Iwayama discloses:
a resistance of the switching element in the OFF state is higher than the resistance of the variable resistance memory element in the second resistance state, and the resistance of the switching element in the ON state is lower than the resistance of the variable resistance memory element in the first resistance state (para. [0042]).
Regarding claims 7 and 18, Iwayama discloses:
the determination operation controller includes a timer that measures the first time period and the second time period (FIG. 7: time control section 53; see para. [0074-0075] with respect to time point t1 and t2).
Regarding claims 8 and 19, Iwayama discloses:
the variable resistance memory element is a magnetoresistance effect element (FIG. 3: magnetoresistance effect element 101; para. [0031]).
Regarding claims 9 and 20, Iwayama discloses:
the magnetoresistance effect element includes a first magnetic layer with a variable magnetization direction (FIG. 3, para. [0033]: storage layer 101a),
a second magnetic layer with a fixed magnetization direction (FIG. 3, para. [0033]: the reference layer 101b), and
a non-magnetic layer provided between the first magnetic layer and the second magnetic layer (FIG. 3, para. [0033]: tunnel barrier layer 101c).
Regarding claim 10, Iwayama discloses:
the magnetoresistance effect element exhibits the first resistance state when the magnetization direction of the first magnetic layer is parallel to the magnetization direction of the second magnetic layer, and exhibits the second resistance state when the magnetization direction of the first magnetic layer is antiparallel to the magnetization direction of the second magnetic layer (para. [0033]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iwayama (US 20240145001 A1) in view of Osada et al. (US 20210295888 A1; hereinafter "Osada").
The applied reference has a common Applicant/Assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
Regarding claims 3 and 14, Iwayama teaches the respective storage device and method as forth in the anticipation rejections above.
However, Iwayama does not teach the determination operation controller is further configured to: in a case where the reference resistance state is the second resistance state: determine that the resistance state to be determined is the first resistance state if the voltage difference between the voltage to be determined and the reference voltage is larger than a predetermined voltage difference, and determine that the resistance state to be determined is the second resistance state if the voltage difference between the voltage to be determined and the reference voltage is smaller than the predetermined voltage difference.
Osada, in the same field of endeavor, discloses, “in the case where the reference resistive state is the high-resistance state, when the voltage difference is less than the criterion voltage difference, it is determined that the determination object resistive state is the high-resistance state and, when the voltage difference is greater than the criterion voltage difference, it is determined that the determination object resistive state is the low-resistance state.” (para. [0094])
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the self reference read operation of Iwayama with the teachings of Osada, wherein the reference resistive state is in a high-resistance state and the determination target resistance state of the memory cell is compared to the high-resistance reference state. One of ordinary skill in the art would have been motivated to make this modification for the benefit of determining the determination object resistive state of a memory cell (Osada para. [0094]).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Claim 11 is/are rejected under 35 U.S.C. 103 as being obvious over Iwayama (US 20240145001 A1) in view of Takizawa (US 12230322 B2).
The applied reference has a common applicant/assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
Regarding claim 11, Iwayama teaches the storage device as set forth in the anticipation rejection of claim 1 above. Iwayama discloses a switching element 102 in FIG. 2 and para. [0028].
However, Iwayama is silent with respect to the material properties of the switching element.
Takizawa, in the same field of endeavor, discloses a switching element comprising a variable resistance material 32 including, “an insulator and a dopant introduced into the insulator by ion injection. The insulator includes, for example, an oxide, which may be SiO2, or a material consisting substantially of SiO2.” (para. [0065])
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the switching element of Iwayama with a switching element including a switching material formed of silicon oxide containing a predetermined element as taught by Takizawa. One of ordinary skill in the art would have been motivated to make this modification for the benefit of including a dynamically variable resistance material in a memory cell switching element (Takizawa at para. [0065]).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 12 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,400,711 (Iwayama). Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of Iwayama discloses the subject matter found claims 1 and 12 in a semantically identical style.
Allowable Subject Matter
Claims 5 and 16 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 5 and 16, the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed limitation(s) of "in a case where the reference resistance state is the second resistance state, the first time period and the second time period are set so that the first time period is longer than the second time period," in combination with the other limitations recited in the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUSTIN BRYCE HEISTERKAMP whose telephone number is (703)756-1095. The examiner can normally be reached M-F 0800-1700.
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/JUSTIN BRYCE HEISTERKAMP/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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