CTNF 19/077,840 CTNF 95020 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority This application is a continuation of 18/658,311 filed on 05/8/2024, now patented US 12,301,505. 18/658,311 is a continuation of 17/144,476 filed on 1/8/2021, now patented US 12,003,454. 17/144,476 is a continuation of PCT/CN2019/076921 filed on 03/5/2019. 02-27 Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. CHINA 201810746392.4 07/09/2018. Information Disclosure Statement The information disclosure statements (IDS) were submitted on 3/12/2025, 4/3/2025, and 2/12/2026. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements have been considered by the examiner. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to refer to www.uspto.gov/TerminalDisclaimer. Claims 1-20 are rejected on the ground of nonstatutory double patenting over of Claims 1-3, 6, and 7 of U.S. Patent No. 12,003,454 B2 . Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application would have been obvious over, the reference claims of US 12,003,454 B2 . The following table shows a mapping of the respective claims of the instant application against the claims of US 12,003,454 B2 . Instant Application 19/077,840 Patent US 12,003,454 B2 1. A chip, comprising: at least one processor, the at least one processor being configured to execute instructions stored in a memory to: generate a physical layer protocol data unit (PPDU), wherein the PPDU comprises a signal field comprising a first field indicating a number of extremely high throughput (EHT)-signal (SIG)-A (EHT-SIG-A) symbols and a second field indicating the PPDU is an EHT PPDU; and send the PPDU. 1. An apparatus, comprising: a memory storing program instructions that are executable by at least one processor; and the at least one processor coupled to the memory, the at least one processor being configured to execute the instructions to: generate a physical layer protocol data unit (PPDU), wherein the PPDU comprises a signal field comprising a first field indicating a number of EHT-SIG-A symbols and a second field indicating the PPDU is an extremely high throughput (EHT) PPDU; and send the PPDU. 2. The chip according to claim 1, wherein the signal field is located in the PPDU after a legacy signal field (L-SIG) field and before an EHT-SIG-A field. 2. The apparatus according to claim 1, wherein the signal field is located after a legacy signal field (L-SIG) field and before an EHT-SIG-A field in the PPDU. 3. The chip according to claim 1, wherein the signal field further comprises a third field indicating a modulation and coding scheme (MCS) of an EHT-SIG-A field in the PPDU. 3. The apparatus according to claim 1, wherein the signal field further comprises a third field indicating a modulation and coding scheme (MCS) of an EHT-SIG-A field. 4. The chip according to claim 1, wherein the signal field further comprises a cyclic redundancy code (CRC) field. 6. The apparatus according to claim 1, wherein the signal field further comprises a cyclic redundancy code (CRC) field. 5. The chip according to claim 1, wherein an EHT-SIG-A field of the PPDU is transmitted in a basic unit of 80 MHz. 7. The apparatus according to claim 1, wherein an EHT-SIG-A field is transmitted in a basic unit of 80 MHz. 6. The chip according to claim 2, wherein the signal field further comprises a third field indicating a MCS of an EHT-SIG-A field in the PPDU. 3. The apparatus according to claim 1, wherein the signal field further comprises a third field indicating a modulation and coding scheme (MCS) of an EHT-SIG-A field. 7. The chip according to claim 2, wherein the signal field further comprises a CRC field. 6. The apparatus according to claim 1, wherein the signal field further comprises a cyclic redundancy code (CRC) field. 8. A system, comprising: a first device, configured to: generate a physical layer protocol data unit (PPDU), wherein the PPDU comprises a signal field comprising a first field indicating a number of extremely high throughput (EHT)-signal (SIG)-A (EHT-SIG-A) symbols and a second field indicating the PPDU is an EHT PPDU; and send the PPDU; and a second device, configured to: receive the PPDU; and read the signal field. 1. An apparatus, comprising: a memory storing program instructions that are executable by at least one processor; and the at least one processor coupled to the memory, the at least one processor being configured to execute the instructions to: generate a physical layer protocol data unit (PPDU), wherein the PPDU comprises a signal field comprising a first field indicating a number of EHT-SIG-A symbols and a second field indicating the PPDU is an extremely high throughput (EHT) PPDU; and send the PPDU. 9. The system according to claim 8, wherein the signal field is located in the PPDU after a legacy signal field (L-SIG) field and before an EHT-SIG-A field. 2. The apparatus according to claim 1, wherein the signal field is located after a legacy signal field (L-SIG) field and before an EHT-SIG-A field in the PPDU. 10. The system according to claim 8, wherein the signal field further comprises a third field indicating a modulation and coding scheme (MCS) of an EHT-SIG-A field in the PPDU. 3. The apparatus according to claim 1, wherein the signal field further comprises a third field indicating a modulation and coding scheme (MCS) of an EHT-SIG-A field. 11. The system according to claim 8, wherein the signal field further comprises a cyclic redundancy code (CRC) field. 6. The apparatus according to claim 1, wherein the signal field further comprises a cyclic redundancy code (CRC) field. 12. The system according to claim 8, wherein an EHT-SIG-A field of the PPDU is transmitted in a basic unit of 80 MHz. 7. The apparatus according to claim 1, wherein an EHT-SIG-A field is transmitted in a basic unit of 80 MHz. 13. The system according to claim 9, wherein the signal field further comprises a third field indicating a MCS of an EHT-SIG-A field in the PPDU. 3. The apparatus according to claim 1, wherein the signal field further comprises a third field indicating a modulation and coding scheme (MCS) of an EHT-SIG-A field. 14. A chip, comprising: at least one processor, the at least one processor being configured to execute instructions stored in a memory to: receive a physical layer protocol data unit (PPDU), wherein the PPDU comprises a signal field comprising a first field indicating a number of extremely high throughput (EHT)-signal (SIG)-A (EHT-SIG-A) symbols and a second field indicating the PPDU is an EHT PPDU; and read the signal field. 1. An apparatus, comprising: a memory storing program instructions that are executable by at least one processor; and the at least one processor coupled to the memory, the at least one processor being configured to execute the instructions to: generate a physical layer protocol data unit (PPDU), wherein the PPDU comprises a signal field comprising a first field indicating a number of EHT-SIG-A symbols and a second field indicating the PPDU is an extremely high throughput (EHT) PPDU; and send the PPDU. 15. The chip according to claim 14, wherein the signal field is located after a legacy signal (L-SIG) field and before a EHT-SIG-A field in the PPDU. 2. The apparatus according to claim 1, wherein the signal field is located after a legacy signal field (L-SIG) field and before an EHT-SIG-A field in the PPDU. 16. The chip according to claim 14, wherein the signal field further comprises a third field indicating a modulation and coding scheme (MCS) of an EHT-SIG-A field. 3. The apparatus according to claim 1, wherein the signal field further comprises a third field indicating a modulation and coding scheme (MCS) of an EHT-SIG-A field. 17. The chip according to claim 14, wherein the signal field further comprises a cyclic redundancy code (CRC) field. 6. The apparatus according to claim 1, wherein the signal field further comprises a cyclic redundancy code (CRC) field. 18. The chip according to claim 14, wherein an EHT-SIG-A field of the PPDU is transmitted in a basic unit of 80 MHz. 7. The apparatus according to claim 1, wherein an EHT-SIG-A field is transmitted in a basic unit of 80 MHz. 19. The chip according to claim 15, wherein the signal field further comprises a third field indicating a MCS of an EHT-SIG-A field in the PPDU. 3. The apparatus according to claim 1, wherein the signal field further comprises a third field indicating a modulation and coding scheme (MCS) of an EHT-SIG-A field. 20. The chip according to claim 15, wherein the signal field further comprises a CRC field. 6. The apparatus according to claim 1, wherein the signal field further comprises a cyclic redundancy code (CRC) field. Claims 1-20 of the instant application merely broadens the scope of Claims 1-3, 6, and 7 of US 12,003,454 B2 . It is well settled that broadening the scope of claims would have been obvious to one of ordinary skill in the art in view of the narrower issued claims. In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982) and In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993). Claims 1-20 are rejected on the ground of nonstatutory double patenting over claims 10-20 of U.S. Patent No. 12,301,505 B2 . Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application would have been obvious over, the reference claims of US 12,301,505 B2 . The following table shows a mapping of the respective claims of the instant application against the claims of US 12,301,505 B2 . Instant Application 19/077,840 Patent US 12,301,505 B2 1. A chip, comprising: at least one processor, the at least one processor being configured to execute instructions stored in a memory to: generate a physical layer protocol data unit (PPDU), wherein the PPDU comprises a signal field comprising a first field indicating a number of extremely high throughput (EHT)-signal (SIG)-A (EHT-SIG-A) symbols and a second field indicating the PPDU is an EHT PPDU; and send the PPDU. 8. An apparatus, comprising: a memory storing program instructions that are executable by at least one processor; and the at least one processor coupled to the memory, the at least one processor being configured to execute the instructions to: receive a physical layer protocol data unit (PPDU), wherein the PPDU comprises a signal field comprising a first field indicating a number of extremely high throughput (EHT)-signal (SIG)-A (EHT-SIG-A) symbols and a second field indicating the PPDU is an EHT PPDU; and read the signal field. 2. The chip according to claim 1, wherein the signal field is located in the PPDU after a legacy signal field (L-SIG) field and before an EHT-SIG-A field. 9. The apparatus according to claim 8, wherein the signal field is located after a legacy signal field (L-SIG) field and before an EHT-SIG-A field in the PPDU. 3. The chip according to claim 1, wherein the signal field further comprises a third field indicating a modulation and coding scheme (MCS) of an EHT-SIG-A field in the PPDU. 10. The apparatus according to claim 8, wherein the signal field further comprises a third field indicating a modulation and coding scheme (MCS) of an EHT-SIG-A field. 4. The chip according to claim 1, wherein the signal field further comprises a cyclic redundancy code (CRC) field. 13. The apparatus according to claim 8, wherein the signal field further comprises a cyclic redundancy code (CRC) field. 5. The chip according to claim 1, wherein an EHT-SIG-A field of the PPDU is transmitted in a basic unit of 80 MHz. 14. The apparatus according to claim 8, wherein an EHT-SIG-A field of the PPDU is transmitted in a basic unit of 80 MHz. 6. The chip according to claim 2, wherein the signal field further comprises a third field indicating a MCS of an EHT-SIG-A field in the PPDU. 10. The apparatus according to claim 8, wherein the signal field further comprises a third field indicating a modulation and coding scheme (MCS) of an EHT-SIG-A field. 7. The chip according to claim 2, wherein the signal field further comprises a CRC field. 13. The apparatus according to claim 8, wherein the signal field further comprises a cyclic redundancy code (CRC) field. 8. A system, comprising: a first device, configured to: generate a physical layer protocol data unit (PPDU), wherein the PPDU comprises a signal field comprising a first field indicating a number of extremely high throughput (EHT)-signal (SIG)-A (EHT-SIG-A) symbols and a second field indicating the PPDU is an EHT PPDU; and send the PPDU; and a second device, configured to: receive the PPDU; and read the signal field. 8. An apparatus, comprising: a memory storing program instructions that are executable by at least one processor; and the at least one processor coupled to the memory, the at least one processor being configured to execute the instructions to: receive a physical layer protocol data unit (PPDU), wherein the PPDU comprises a signal field comprising a first field indicating a number of extremely high throughput (EHT)-signal (SIG)-A (EHT-SIG-A) symbols and a second field indicating the PPDU is an EHT PPDU; and read the signal field. 9. The system according to claim 8, wherein the signal field is located in the PPDU after a legacy signal field (L-SIG) field and before an EHT-SIG-A field. 9. The apparatus according to claim 8, wherein the signal field is located after a legacy signal field (L-SIG) field and before an EHT-SIG-A field in the PPDU. 10. The system according to claim 8, wherein the signal field further comprises a third field indicating a modulation and coding scheme (MCS) of an EHT-SIG-A field in the PPDU. 10. The apparatus according to claim 8, wherein the signal field further comprises a third field indicating a modulation and coding scheme (MCS) of an EHT-SIG-A field. 11. The system according to claim 8, wherein the signal field further comprises a cyclic redundancy code (CRC) field. 13. The apparatus according to claim 8, wherein the signal field further comprises a cyclic redundancy code (CRC) field. 12. The system according to claim 8, wherein an EHT-SIG-A field of the PPDU is transmitted in a basic unit of 80 MHz. 14. The apparatus according to claim 8, wherein an EHT-SIG-A field of the PPDU is transmitted in a basic unit of 80 MHz. 13. The system according to claim 9, wherein the signal field further comprises a third field indicating a MCS of an EHT-SIG-A field in the PPDU. 10. The apparatus according to claim 8, wherein the signal field further comprises a third field indicating a modulation and coding scheme (MCS) of an EHT-SIG-A field. 14. A chip, comprising: at least one processor, the at least one processor being configured to execute instructions stored in a memory to: receive a physical layer protocol data unit (PPDU), wherein the PPDU comprises a signal field comprising a first field indicating a number of extremely high throughput (EHT)-signal (SIG)-A (EHT-SIG-A) symbols and a second field indicating the PPDU is an EHT PPDU; and read the signal field. 8. An apparatus, comprising: a memory storing program instructions that are executable by at least one processor; and the at least one processor coupled to the memory, the at least one processor being configured to execute the instructions to: receive a physical layer protocol data unit (PPDU), wherein the PPDU comprises a signal field comprising a first field indicating a number of extremely high throughput (EHT)-signal (SIG)-A (EHT-SIG-A) symbols and a second field indicating the PPDU is an EHT PPDU; and read the signal field. 15. The chip according to claim 14, wherein the signal field is located after a legacy signal (L-SIG) field and before a EHT-SIG-A field in the PPDU. 9. The apparatus according to claim 8, wherein the signal field is located after a legacy signal field (L-SIG) field and before an EHT-SIG-A field in the PPDU. 16. The chip according to claim 14, wherein the signal field further comprises a third field indicating a modulation and coding scheme (MCS) of an EHT-SIG-A field. 10. The apparatus according to claim 8, wherein the signal field further comprises a third field indicating a modulation and coding scheme (MCS) of an EHT-SIG-A field. 17. The chip according to claim 14, wherein the signal field further comprises a cyclic redundancy code (CRC) field. 13. The apparatus according to claim 8, wherein the signal field further comprises a cyclic redundancy code (CRC) field. 18. The chip according to claim 14, wherein an EHT-SIG-A field of the PPDU is transmitted in a basic unit of 80 MHz. 14. The apparatus according to claim 8, wherein an EHT-SIG-A field of the PPDU is transmitted in a basic unit of 80 MHz. 19. The chip according to claim 15, wherein the signal field further comprises a third field indicating a MCS of an EHT-SIG-A field in the PPDU. 10. The apparatus according to claim 8, wherein the signal field further comprises a third field indicating a modulation and coding scheme (MCS) of an EHT-SIG-A field. 20. The chip according to claim 15, wherein the signal field further comprises a CRC field. 13. The apparatus according to claim 8, wherein the signal field further comprises a cyclic redundancy code (CRC) field. Claims 1-20 of the instant application merely broadens the scope of Claims 8-10, 13, and 14 of US 12,301,505 B2 . It is well settled that broadening the scope of claims would have been obvious to one of ordinary skill in the art in view of the narrower issued claims. In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982) and In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993). Allowable Subject Matter Claims 1-20 would be allowable if the nonstatutory double patenting rejections to these claims set forth in this Office action are overcome and to include all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JI-HAE YEA whose telephone number is (571) 270-3310. The examiner can normally be reached on MON-FRI, 7am-3pm, ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, SUJOY K KUNDU can be reached on (571) 272-8586. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JI-HAE YEA/Primary Examiner, Art Unit 2471 Application/Control Number: 19/077,840 Page 2 Art Unit: 2471 Application/Control Number: 19/077,840 Page 3 Art Unit: 2471 Application/Control Number: 19/077,840 Page 4 Art Unit: 2471 Application/Control Number: 19/077,840 Page 5 Art Unit: 2471 Application/Control Number: 19/077,840 Page 6 Art Unit: 2471 Application/Control Number: 19/077,840 Page 7 Art Unit: 2471 Application/Control Number: 19/077,840 Page 8 Art Unit: 2471 Application/Control Number: 19/077,840 Page 9 Art Unit: 2471 Application/Control Number: 19/077,840 Page 10 Art Unit: 2471 Application/Control Number: 19/077,840 Page 11 Art Unit: 2471 Application/Control Number: 19/077,840 Page 12 Art Unit: 2471 Application/Control Number: 19/077,840 Page 13 Art Unit: 2471 Application/Control Number: 19/077,840 Page 14 Art Unit: 2471 Application/Control Number: 19/077,840 Page 15 Art Unit: 2471 Application/Control Number: 19/077,840 Page 16 Art Unit: 2471 Application/Control Number: 19/077,840 Page 17 Art Unit: 2471 Application/Control Number: 19/077,840 Page 18 Art Unit: 2471 Application/Control Number: 19/077,840 Page 19 Art Unit: 2471
Prosecution Insights