Prosecution Insights
Last updated: September 17, 2026
Application No. 19/078,475

ALIGNMENT SYSTEM AND ALIGNMENT METHOD FOR SEMICONDUCTOR LITHOGRAPHY PROCESSES

Non-Final OA §103
Filed
Mar 13, 2025
Priority
Mar 15, 2024 — TW 113109828
Examiner
ASFAW, MESFIN T
Art Unit
Tech Center
Assignee
Lids Semiconductor Technology Co. Ltd.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
1y 1m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
820 granted / 988 resolved
+23.0% vs TC avg
Moderate +14% lift
Without
With
+13.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
25 currently pending
Career history
1010
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
57.6%
+17.6% vs TC avg
§102
33.2%
-6.8% vs TC avg
§112
3.0%
-37.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 988 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 4-8 and 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato [US 20040227925 A1] in view of Kawadahara [US 20190221461 A1]. As per Claims 1 and 8, Sato teaches an alignment system for semiconductor lithography (Para 50), comprising: a first alignment module (the coarse alignment unit 110) including a first carrier (stage 73) configured to support a wafer 60, the first carrier being movable to perform coarse alignment of said wafer based on a particular mark on the wafer such that the wafer is brought within a first alignment tolerance (See fig. 3, Para 86-87); a second alignment module (the measurement fine adjustment) including a second carrier (stage 72) and a first camera system (an alignment scope), the second carrier being configured to support and move the wafer, and the first camera system being arranged to further refine movement of the wafer to a narrower second alignment tolerance (first fine adjustment), based on two alignment marks on the wafer, wherein the second alignment tolerance is tighter than the first alignment tolerance (Para 90); and a third alignment module (the exposure fine adjustment) including a third carrier (stage 62), a second camera system (exposure focus detection system), and a photomask carrier (a reticle stage 2 for caring a reticle 1), the third carrier being configured to support and move the wafer, the photomask carrier being configured to carry a photomask, and the second camera system being configured to align the wafer within a third alignment tolerance, which is tighter than the second alignment tolerance, based on two alignment marks on the wafer corresponding to two mask marks on the photomask (Para 91 and 96); Sato does not explicitly teach a dual-camera system; and wherein a first field of view of the first dual-camera system is greater than a second field of view of the second dual-camera system, so that after alignment in the second alignment module, the wafer's two alignment marks fall within the second field of view of the second dual-camera system for fine alignment. Kawadahara teaches a position detecting unit 60e serving as an imaging element such as a CCD or a CMOS sensor is provided inside each of the through holes 156t. The imaging element of each position detecting unit 60e has a field of view of, for example, 200 µm square or more and 800 µm square or less. Each position detecting unit 60e is operated at least from when a wafer W is transferred into the exposure unit 50 until exposure processing for the wafer W is finished, thereby detecting an edge of the wafer W (Para 57). Therefore, it would have been obvious to one of ordinary skill in the art at time the invention was made to incorporate the detection system as claimed in order to increase the measurement precision of a detection system. As per Claims 4 and 10, Sato in view of Kawadahara teaches the alignment system of claim 1. Sato further disclosed a robotic arm configured to transfer the wafer among the first carrier, the second carrier, and the third carrier (See fig. 3, Para 86). As per Claims 5 and 12, Sato in view of Kawadahara teaches the alignment system of claim 1. Sato further disclosed wherein the first carrier and the second carrier are the same carrier (See fig. 2 and 3). As per Claims 6 and 13, Sato in view of Kawadahara teaches the alignment system of claim 1. Kawadahara further disclosed wherein the alignment marks on the wafer are cross-shaped, and the mask marks on the photomask are square-shaped, and the third alignment module is configured to complete alignment within the third alignment tolerance when the second camera system observes that the cross-shaped wafer marks are positioned within the square-shaped mask marks (See fig. 5, Para 46). Therefore, it would have been obvious to one of ordinary skill in the art at time the invention was made to incorporate the detection system as claimed in order to increase the measurement precision of a detection system. As per Claims 7 and 14, Sato in view of Kawadahara teaches the alignment system of claim 1. Kawadahara further disclosed wherein the first dual-camera system is configured to simultaneously capture images of the two alignment marks on the wafer (See fig. 6). Therefore, it would have been obvious to one of ordinary skill in the art at time the invention was made to incorporate the detection system as claimed in order to increase the measurement precision of a detection system. As per Claim 11, Sato in view of Kawadahara teaches the method of claim 8. Sato further disclosed transferring the wafer among the first carrier, the second carrier, and the third carrier using a robotic arm 105 (Para 86). Claim(s) 2, 3, 9 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato in view of Kawadahara as applied above, further in view of Krol [US 20230018538 A1]. As per Claims 2, 3, 9 and 10, Sato in view of Kawadahara teaches the alignment system of claim 1. Sato further disclosed a multichannel detection system or improve a detection optical system to increase the measurement precision of the focus measurement system (Para 10); and, Kawadahara teaches alignment here is a high-precision fine alignment performed by detecting the more number of marks Mk than in TV pre-alignment (Para 51). Sato in view of Kawadahara does not explicitly teach wherein the first alignment module is configured to position the wafer within about 50 micrometers of tolerance. Krol teaches the open-loop and/or closed-loop control of movement devices according to the invention for (lateral) alignment (fine adjustment) is carried out in particular on the basis of x-y positions and/or alignment locations detected using other measuring means. The accuracy of these movement devices is preferably smaller than 200 nm, further preferably smaller than 100 nm, particularly preferably smaller than 50 nm, very particularly preferably smaller than 20 nm, further preferably smaller than 10 nm, in the ideal case smaller than 1 nm (Para 117). Therefore, it would have been obvious to one of ordinary skill in the art at time the invention was made to incorporate the alignment module as claimed in order to increase the measurement precision of a detection system. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MESFIN ASFAW whose telephone number is (571)270-5247. The examiner can normally be reached Monday - Friday 8 am - 4 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Toan Ton can be reached at 571-272-2303. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MESFIN T ASFAW/Primary Examiner, Art Unit 2882
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Prosecution Timeline

Mar 13, 2025
Application Filed
Sep 10, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
97%
With Interview (+13.8%)
2y 8m (~1y 1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 988 resolved cases by this examiner. Grant probability derived from career allowance rate.

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