DETAILED ACTION
1. Claims 1-20 are pending in this application filed on March 13, 2025.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claims 1-2, 4, 6-10, and 14-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US Pat. 11,328,763 (“Im”).
5. With respect to claim 1, Im discloses a semiconductor device (FIG. 1), comprising:
a first power line (RTO) to which a first voltage (VDD, 8:18-20, “The overdrive circuit 54 provides the source voltage VDD to the pull-up power line RTO) is supplied;
a second power line (VSS) to which a second voltage lower than the first voltage is supplied;
a first logic circuit (54) including a first electrode, and electrically connected to the first power line;
a second logic circuit (58) including a second electrode provided separately from the first electrode, and electrically connected to the first power line and the first logic circuit;
a voltage supplying circuit (25M, 25S, and 52) configured to control, based on a first control signal, whether or not to supply a third voltage (VCORE) to the first electrode, the third voltage being lower than the first voltage and higher than the second voltage (see FIG. 3, VCORE is lower than VDD and higher than VSS); and
a first transistor (56, PD_D1) including a gate electrode to which a second control signal (SAN) is input, and electrically connected between the second electrode (56 is electrically connected to 58) and the second power line (56 is connected to VSS).
6. With respect to claim 2, Im discloses the semiconductor device of claim 1, further comprising a control circuit configured to output the first control signal and the second control signal (circuits that generate SAP1, SAP2, and SAN signals).
7. With respect to claim 4, Im discloses the semiconductor device of claim 1, wherein the first transistor is an n-channel MOS transistor (7:29-31).
8. With respect to claim 6, Hagiwara discloses the semiconductor device of claim 2, wherein the control circuit outputs the first control signal to the voltage supplying circuit (see FIG. 2).
9. With respect to claim 7, Im discloses the semiconductor device of claim 2, wherein the control circuit outputs the second control signal to the gate electrode (see FIG. 2, SAN is output to the gate electrode of PD_D1).
10. With respect to claim 8, Im discloses a semiconductor device, comprising:
a first power line to which a first voltage is supplied;
a second power line to which a second voltage lower than the first voltage is supplied;
a first logic circuit including a first electrode, and electrically connected to the first power line; a second logic circuit including a second electrode provided separately from the first electrode, and electrically connected to the first power line and the first logic circuit;
a voltage supplying circuit configured to control, based on a first control signal, whether or not to supply a third voltage to the first electrode, the third voltage being lower than the first voltage and higher than the second voltage;
a first transistor including a gate electrode to which a second control signal is input, and electrically connected between the second electrode and the second power line; (see the rejection of claim 1 above)
a second transistor (FIG. 2, MN1) including a gate electrode to which a third control signal is input (BLQ), and electrically connected between the first electrode (RTO) and the second power line (VSS);
a first switch (PU_D2) which is controlled by a fourth control signal (MSEL0), and which is electrically connected between the voltage supplying circuit and the first electrode; and
a second switch (PU_D2) which is controlled by the fourth control signal (MSEL0), and which is electrically connected between the voltage supplying circuit and the second electrode.
11. With respect to claim 9, Im discloses the semiconductor device of claim 8, wherein the first transistor (7:29-31) and the second transistor (see FIG. 2, MN1 and PD_D1 are shown as the same type of transistors) are n-channel MOS transistors.
12. With respect to claim 10, Im discloses the semiconductor device of claim 9, further comprising a control circuit (circuits that supply control signals) configured to output the first control signal, the second control signal, the third control signal, and the fourth control signal.
13. With respect to claim 14, Im discloses the semiconductor device of claim 10, wherein the control circuit outputs the second control signal to the first transistor (see the rejection of claim 1 above).
14. With respect to claim 15, Im discloses the semiconductor device of claim 10, wherein the control circuit outputs the third control signal to the second transistor (see the rejection of claim 8 above).
15. With respect to claim 16, see the rejection of claim 1 above.
16. With respect to claim 17, see the rejection of claim 2 above.
17. Claims 1-2, 4, 6-10, and 14-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US Pub. 2021/0174882 (“Hagiwara”).
18. With respect to claim 1, Hagiwara discloses a semiconductor device (FIG. 10), comprising:
a first power line (N1) to which a first voltage (VDD1) is supplied;
a second power line (VSS) to which a second voltage lower than the first voltage is supplied (paragraph [0105]);
a first logic circuit (TR4) including a first electrode, and electrically connected to the first power line;
a second logic circuit (TR2) including a second electrode provided separately from the first electrode, and electrically connected to the first power line and the first logic circuit;
a voltage supplying circuit (TR1, TR2, TR3) configured to control, based on a first control signal, whether or not to supply a third voltage (VCCQ) to the first electrode, the third voltage being lower than the first voltage and higher than the second voltage (paragraph [0096]); and
a first transistor (TR3) including a gate electrode to which a second control signal (N2) is input, and electrically connected between the second electrode and the second power line (TR3 is electrically connected to TR2 and VSS).
19. With respect to claim 2, Hagiwara discloses the semiconductor device of claim 1, further comprising a control circuit configured to output the first control signal and the second control signal (logic section 60 and control circuit 40 shown in FIG. 6).
20. With respect to claim 4, Hagiwara discloses the semiconductor device of claim 1, wherein the first transistor is an n-channel MOS transistor (paragraph [0065]).
21. With respect to claim 6, Hagiwara discloses the semiconductor device of claim 2 wherein the control circuit outputs the first control signal to the voltage supplying circuit (see FIG. 10).
22. With respect to claim 7, Hagiwara discloses the semiconductor device of claim 2, wherein the control circuit outputs the second control signal to the gate electrode (see FIG. 10).
23. With respect to claim 8, Hagiwara discloses a semiconductor device (FIG 27) comprising:
a first power line (N1) to which a first voltage (VDD1, see FIG. 10) is supplied;
a second power line to which a second voltage (VSS) lower than the first voltage is supplied;
a first logic circuit (TR4) including a first electrode (N1), and electrically connected to the first power line (VDD1);
a second logic circuit (62) including a second electrode (N4) provided separately from the first electrode, and electrically connected to the first power line and the first logic circuit (all circuit elements are electrically connected to all other elements in the circuit of FIG. 27);
a voltage supplying circuit (TR31, TR32) configured to control, based on a first control signal, whether or not to supply a third voltage (VCCQ) to the first electrode, the third voltage being lower than the first voltage and higher than the second voltage (paragraph [0096]);
a first transistor (TR8) including a gate electrode to which a second control signal is input, and electrically connected between the second electrode and the second power line (TR8 is between N4 and VSS);
a second transistor (TR3) including a gate electrode to which a third control signal is input, and electrically connected between the first electrode (N1) and the second power line (VSS);
a first switch (TR33) which is controlled by a fourth control signal (N2), and which is electrically connected between the voltage supplying circuit and the first electrode (TR33 is between TR31+TR32 and N1); and
a second switch (TR34) which is controlled by the fourth control signal (N2), and which is electrically connected between the voltage supplying circuit and the second electrode (TR34 is between TR31+TR32 and N4).
3. The semiconductor device of claim 2, wherein when the second voltage is input to the first logic circuit, the control circuit is configured to:
control the voltage supplying circuit to supply a high-level voltage to the first control signal, and supply the third voltage to the first electrode; and
control the first transistor to supply a high-level voltage to the second control signal, and supply the second voltage to the second electrode.
24. With respect to claim 9, Hagiwara discloses the semiconductor device of claim 8, wherein the first transistor (TR8) and the second transistor (TR3) are n-channel MOS transistors (paragraphs [0065] and [0081]).
25. With respect to claim 10, Hagiwara discloses the semiconductor device of claim 9, further comprising: a control circuit (circuits that supply control signals) configured to output the first control signal, the second control signal, the third control signal, and the fourth control signal.
26. With respect to claim 14, Hagiwara discloses the semiconductor device of claim 10, wherein the control circuit outputs the second control signal to the first transistor (see the rejection of claim 1 above).
27. With respect to claim 15, Hagiwara discloses the semiconductor device of claim 10, wherein the control circuit outputs the third control signal to the second transistor (see the rejection of claim 8 above).
28. With respect to claim 16, see the rejection of claim 1 above.
29. With respect to claim 17, see the rejection of claim 2 above.
Allowable Subject Matter
30. Claims 3, 5, 11-13, and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
31. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Woo H Choi whose telephone number is (571)272-4179. The examiner can normally be reached 9 am - 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hetul Patel can be reached on (571) 272-4184. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Woo H Choi/
Primary Examiner, Art Unit 3002
Prosecution Insights