Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 and 11 have been amended. No claims have been added. Claims 18-19 are cancelled. Claims 1-17 and 20 are currently under review.
Response to Arguments
Applicant’s arguments with respect to claims 1-17 and 20 have been considered but are moot because the new ground of rejection does not rely on the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9-11, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (Pub. No.: US 2022/0415250 A1) hereinafter referred to as Choi in view of Hong et al. (Pub. No.: US 2022/0199033 A1) hereinafter referred to as Hong1.
With respect to Claim 1, Choi teaches a display apparatus (fig. 1, item 100; ¶35) comprising: a substrate (a display comprises a substrate) comprising a display area (fig. 1, item 104; ¶35) and a non-display area (fig. 1, item 108;area outside of item 104; ¶36) surrounding the display area; a plurality of pixels disposed on the substrate in the display area (¶35); a plurality of driver sets (figs. 3B and 5, item 320: item 502b and 504b = set) spaced apart from each other in the non-display area (fig. 3B, items 320); and a dummy driver (fig. 3B, item dummy) located between two adjacent driver sets among the plurality of driver sets, wherein, one driver set among the plurality of driver sets comprises at least one first driver (fig. 5, item 502b; ¶70) and at least one second driver (fig. 5, item 504b; ¶70).
Choi does not mention the at least one first driver is connected to m output lines connected to some of the plurality of pixels, and the at least one second driver is connected to n output lines connected to some of the plurality of pixels, wherein m is not equal to n.
Hong1 teaches a display apparatus (fig. 1, item 100; ¶79) comprising: a substrate (fig. 1, item SUB; ¶82) comprising a display area (fig. 1, item DA; ¶85) and a non-display area (fig. 1, item NDA; ¶85) surrounding the display area; a plurality of pixels (fig. 1, item SP; ¶84) disposed on the substrate in the display area; and a plurality of driver sets (figs. 1-2 and 3B, item 130) spaced apart from each other in the non-display area; one driver set (figs. 2 and 3B; ¶135) among the plurality of driver sets comprises at least one first driver (fig. 3B, item 320; ¶142) and at least one second driver (fig. 3B, item 310; ¶137), the at least one first driver is connected to m output lines connected to some of the plurality of pixels (¶136, “a m-th gate driving circuit 320 corresponding to the m-th subpixel SP(m)”), and the at least one second driver is connected to n output lines connected to some of the plurality of pixels (¶136, “a n-th gate driving circuit 310 corresponding to the n-th subpixel SP(n)”), wherein m is not equal to n (¶133; ¶355, “a n-th first scan line corresponding to the n-th subpixel row and a m-th first scan line corresponding to a m-th subpixel row which is identical to or different from the n-th subpixel row”; claim 1, “a n-th second scan line corresponding to the n-th subpixel row and a m-th second scan line corresponding to the m-th subpixel row, and the plurality of the light emission lines includes a n-th light emission line corresponding to the n-th subpixel row and m-th light emission line corresponding to the m-th subpixel row, wherein n is a natural number and m is a natural number that is either equal to or different from n”).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display apparatus of Choi, such that the at least one first driver is connected to m output lines and is connected to some of the plurality of pixels, and the at least one second driver is connected to n output lines and is connected to some of the plurality of pixels, wherein m is not equal to n, as taught by Hong1, so as to provide a design alternatives since the output lines of each driver may vary in any number (¶133, “m is n or a number different from n”).
Choi does not teach wherein, when a least common multiple of m and n is o, the one driver set comprises: o/m first drivers and o/n second drivers.
Although Hong does not explicitly mention wherein, when a least common multiple of m and n is o, the one driver set comprises: o/m first drivers and o/n second drivers, Hong teaches that m and n are different (¶133; ¶355; claim 1) where the number m and n are 1 or greater and not equal to each other, therefore any number combination not equal to each other is a least common multiple of m and n is o, the one driver set comprises: o/m first drivers and o/n second drivers
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display apparatus of Choi, wherein, when a least common multiple of m and n is o, the one driver set comprises: o/m first drivers and o/n second drivers, as taught by Hong1 so as to provide design alternatives.
With respect to Claim 9, claim 1 is incorporated, Choi teaches wherein the non-display area comprises a corner area on a corner of the substrate (fig. 3A, item 132), and the plurality of driver sets are arranged in the corner area (fig. 3B).
With respect to Claim 10, claim 1 is incorporated, Choi teaches wherein at least one of the m output lines connected to the first driver (fig. 5, item 502b) and at least one of the n output lines connected to the second driver (fig. 5, item 504b) are connected to a same pixel (fig. 3B; fig. 4B; fig. 5).
With respect to Claim 11, Choi teaches a display apparatus (fig. 1, item 100; ¶35) comprising: a substrate (a display comprises a substrate) comprising a display area (fig. 1, item 104; ¶35) and a non-display area (fig. 1, item 108;area outside of item 104; ¶36) surrounding the display area; a plurality of pixels disposed on the substrate in the display area (¶35); and a driver set (figs. 3B and 5, item 320: item 502b and 504b = set) arranged in the non-display area and connected to at least one of the plurality of pixels (fig. 3B, item 302; ¶52), wherein the driver set comprises a first driver (fig. 5, item 502b; ¶70) the driver sets are spaced apart from each other at regular intervals.
Choi does not mention wherein, a first driver of the driver set comprises: a control stage and m output stages sharing the control stage, and at least some of the m output stages are spaced apart from each other at regular intervals, wherein, the driver set comprises at least one second driver connected to n output lines connected to some of the plurality of pixels, wherein m is not equal to n, wherein, when a least common multiple of m and n is o, the driver set comprises: o/m first drivers; and o/n second drivers.
Hong1 teaches a display apparatus (fig. 1, item 100; ¶79) comprising: a substrate (fig. 1, item SUB; ¶82) comprising a display area (fig. 1, item DA; ¶85) and a non-display area (fig. 1, item NDA; ¶85) surrounding the display area; a plurality of pixels (fig. 1, item SP; ¶84) disposed on the substrate in the display area; and a driver set (figs. 1-2 and 3B, item 130) spaced apart from each other in the non-display area; a first driver set (figs. 2 and 3B; ¶135) comprises: a control stage (fig. 3B, item 323; ¶143) and m output stages (fig. 3B, item EML(m); ¶126; ¶143) sharing the control stage, and at least some of the m output stages are spaced apart from each other at regular intervals (fig. 3B), wherein, the driver set comprises at least one second driver (fig. 3B, item 311/312/313; ¶138) connected to n output lines (fig. 3B, item SCL1(n), SCL2(n), EML(n); ¶138) connected to some of the plurality of pixels, wherein m is not equal to n (¶133; ¶355, “a n-th first scan line corresponding to the n-th subpixel row and a m-th first scan line corresponding to a m-th subpixel row which is identical to or different from the n-th subpixel row”; claim 1, “a n-th second scan line corresponding to the n-th subpixel row and a m-th second scan line corresponding to the m-th subpixel row, and the plurality of the light emission lines includes a n-th light emission line corresponding to the n-th subpixel row and m-th light emission line corresponding to the m-th subpixel row, wherein n is a natural number and m is a natural number that is either equal to or different from n”).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display apparatus of Choi, wherein, a first driver of the driver set comprises: a control stage and m output stages sharing the control stage, and at least some of the m output stages are spaced apart from each other at regular intervals, wherein, the driver set comprises at least one second driver connected to n output lines connected to some of the plurality of pixels, wherein m is not equal to n, wherein, when a least common multiple of m and n is o, the driver set comprises: o/m first drivers; and o/n second drivers, as taught by Hong1, so as to provide a design alternatives since the output lines of each driver may vary in any number (¶133, “m is n or a number different from n”).
Choi does not teach wherein, when a least common multiple of m and n is o, the one driver set comprises: o/m first drivers and o/n second drivers.
Although Hong does not explicitly mention wherein, when a least common multiple of m and n is o, the one driver set comprises: o/m first drivers and o/n second drivers, Hong teaches that m and n are different (¶133; ¶355; claim 1) where the number m and n are 1 or greater and not equal to each other, therefore any number combination not equal to each other is a least common multiple of m and n is o, the one driver set comprises: o/m first drivers and o/n second drivers
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display apparatus of Choi, wherein, when a least common multiple of m and n is o, the one driver set comprises: o/m first drivers and o/n second drivers, as taught by Hong1 so as to provide design alternatives.
With respect to Claim 17, claim 11 is incorporated, Choi teaches wherein, the non-display area comprises a corner area on a corner of the substrate, and the driver set is arranged in the corner area (fig. 3B, item 132; ¶37; ¶51).
With respect to Claim 20, claim 11 is incorporated, Choi teaches comprising: a plurality of driver sets comprising the driver set (fig. 3B, item 320: plurality of driver sets and fig. 5 item 502b and 504b = driver set); and a dummy driver (figs. 3B and 5, item dummy) located between adjacent two of the plurality of driver sets.
Claims 2-3 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Choi and Hong1 as applied to claim 1 above, and further in view of Hong et al. (Pub. No.: US 2023/0197011 A1) hereinafter referred to as Hong2.
With respect to Claim 2, claim 1 is incorporated, Choi and Hong1 combined do not teach wherein the at least one first driver comprises a control stage and m output stages, the control stage is connected to an input terminal to which a start signal is input, a first voltage input terminal to which a first voltage is input, and a second voltage input terminal to which a second voltage is input, and controls voltages of a first node and a second node, each of the m output stages is connected to an output terminal connected to a corresponding output line among the m output lines, and the m output stages are connected to the first node and the second node and share the control stage.
Hong2 teaches a display apparatus (fig. 1, item 100; ¶47; ¶61, mobile device) comprising: a substrate (a display device comprises a substrate) comprising a display area (fig. 1, item 110 and a non-display area (fig. 1, area surrounding item 110) surrounding the display area; a plurality of pixels disposed on the substrate in the display area (¶50); a plurality of drivers (fig. 2, items GDIC or SDIC; ¶55; ¶57), at least one first driver (fig. 5; fig. 6; fig. 7) of the plurality of drivers comprises a control stage (fig. 5, item 122; fig. 7, items 502, 504, 506, 508, 510, 512; ¶115; ¶144) and m output stages (fig. 6, SCAN (1)… SCAN(4); fig. 7, items SCAN(i), SCAN(i+1), SCAN(i+2), SCAN(i+3), the control stage is connected to an input terminal to which a start signal is input (fig. 6, via item GSP; fig. 7, previous carry signal = start signal; ¶63; ¶135), a first voltage input terminal to which a first voltage is input (fig. 7, item GVDD1; ¶146, “In response to the input of the reset signal RESET, the line selection unit 502 charges the Q node to the level of the first high-potential gate voltage GVDD1 based on the charging voltage of the M node”), and a second voltage input terminal to which a second voltage is input (fig. 7, item GVSS3), and controls voltages of a first node and a second node (¶183, “The second transistor T32 is turned on when the voltage of the QB node is at a high level to supply the third low-potential gate voltage GVSS3 to the shared node of the first transistor T31 and the second transistor T32”; ¶184), each of the m output stages is connected to an output terminal connected to a corresponding output line among the m output lines (fig. 7), and the m output stages are connected to the first node and the second node and share the control stage (fig. 7, via item gates of T71, T73, T75, and T77 and via gates of T72, T74, T76, and T78).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined display apparatus of Choi and Hong1, wherein the at least one first driver comprises a control stage and m output stages, the control stage is connected to an input terminal to which a start signal is input, a first voltage input terminal to which a first voltage is input, and a second voltage input terminal to which a second voltage is input, and controls voltages of a first node and a second node, each of the m output stages is connected to an output terminal connected to a corresponding output line among the m output lines, and the m output stages are connected to the first node and the second node and share the control stage, as taught by Hong2 so as to provide a driving circuit capable of effectively detecting an error in the gate driving circuit and compensating for changes that occur in the gate driving circuit over time (¶10).
With respect to Claim 3, claim 2 is incorporated, Choi teaches wherein the m output stages are spaced apart from each other at regular intervals (fig. 3B).
With respect to Claim 12, claim 11 is incorporated, Choi does not teach wherein the control stage is connected to an input terminal to which a start signal is input, a first voltage input terminal to which a first voltage is input, and a second voltage input terminal to which a second voltage is input, and controls voltages of a first node and a second node, and each of the m output stages is connected to an output terminal configured to output an output signal to a corresponding output line, and the m output stages are connected to the first node and the second node and share the control stage.
Hong2 teaches a display apparatus (fig. 1, item 100; ¶47; ¶61, mobile device) comprising: a substrate (a display device comprises a substrate) comprising a display area (fig. 1, item 110 and a non-display area (fig. 1, area surrounding item 110) surrounding the display area; a plurality of pixels disposed on the substrate in the display area (¶50); a plurality of drivers (fig. 2, items GDIC or SDIC; ¶55; ¶57), at least one first driver (fig. 5; fig. 6; fig. 7) of the plurality of drivers comprises a control stage (fig. 5, item 122; fig. 7, items 502, 504, 506, 508, 510, 512; ¶115; ¶144) and m output stages (fig. 6, SCAN (1)… SCAN(4); fig. 7, items SCAN(i), SCAN(i+1), SCAN(i+2), SCAN(i+3)) sharing the control stage; wherein the control stage is connected to an input terminal to which a start signal is input (fig. 6, via item GSP; fig. 7, previous carry signal = start signal; ¶63; ¶135), a first voltage input terminal to which a first voltage is input (fig. 7, item GVDD1; ¶146, “In response to the input of the reset signal RESET, the line selection unit 502 charges the Q node to the level of the first high-potential gate voltage GVDD1 based on the charging voltage of the M node”), and a second voltage input terminal to which a second voltage is input (fig. 7, item GVSS3), and controls voltages of a first node and a second node (¶183, “The second transistor T32 is turned on when the voltage of the QB node is at a high level to supply the third low-potential gate voltage GVSS3 to the shared node of the first transistor T31 and the second transistor T32”; ¶184), each of the m output stages is connected to an output terminal connected to an output terminal configured to output an output signal to a corresponding output line (fig. 7), and the m output stages are connected to the first node and the second node and share the control stage (fig. 7, via item gates of T71, T73, T75, and T77 and via gates of T72, T74, T76, and T78).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined display apparatus of Choi and Hong1, wherein the control stage is connected to an input terminal to which a start signal is input, a first voltage input terminal to which a first voltage is input, and a second voltage input terminal to which a second voltage is input, and controls voltages of a first node and a second node, and each of the m output stages is connected to an output terminal configured to output an output signal to a corresponding output line, and the m output stages are connected to the first node and the second node and share the control stage, as taught by Hong2 so as to provide a driving circuit capable of effectively detecting an error in the gate driving circuit and compensating for changes that occur in the gate driving circuit over time (¶10).
Claims 4, 6-7, and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Choi, Hong1, and Hong2 as applied to claim 2 above, and further in view of Lee et al. (Pub. No.: US 2017/0338295 A1) hereinafter referred to as Lee.
With respect to Claim 4, claim 2 is incorporated, Choi, Hong1, and Hong2 combined do not teach wherein the control stage comprises: a first transistor connected to the input terminal and the first node, and comprising a gate connected to a first clock terminal to which one of a plurality of clock signals is input; a second transistor connected to the second node and the first clock terminal, and comprising a gate connected to the first node; and a third transistor connected to the second voltage input terminal and the second node, and comprising a gate connected to the first clock terminal.
Lee teaches a display device (fig. 1, item 100; ¶37) comprising: a substrate (fig. 1, item 101, display devices comprise a substrate) comprising a display area (fig. 1, item AA; ¶37) and a non-display area (fig. 1, item NA; ¶37) surrounding the display area; a plurality of pixels (fig. 1, item 102; ¶37) disposed on the substrate in the display area; a plurality of drivers (fig. 1, item 110, 120, 130) in the non-display area; wherein, at least one first driver of the plurality of drivers comprises a control stage (fig. 1, items 1210 and 1220; ¶83) and an output stage (fig. 7, item 1230; ¶83), the control stage is connected to an input terminal to which a start signal is input (fig. 7, item SSP1: start signal; ¶79), a first voltage input terminal to which a first voltage is input (fig. 7, item VDD) and a second voltage input terminal to which a second voltage is input (fig. 7, item VSS), and controls voltages of a first node (fig. 7, item N3: first node) and a second node (fig. 7, item N1 = second node); wherein the control stage (fig. 7, item 1210 and 1220; ¶83) comprises: a first transistor (fig. 7, item M2) connected to the input terminal and the first node (fig. 7, item N3: first node), and comprising a gate connected to a first clock terminal (fig. 7, item CLK1) to which one of a plurality of clock signals is input; a second transistor (fig. 7, item M7) connected to the second node (fig. 7, item N1 = second node) and the first clock terminal, and comprising a gate connected to the first node (fig. 7); and a third transistor (fig. 7, item M8) connected to the second voltage input terminal (fig. 7, item VSS) and the second node (fig. 7, N1 = second node), and comprising a gate connected to the first clock terminal (fig. 7).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined display apparatus of Choi, Hong1, and Hong2, to replace items 502, 504, 506, 508, 510, and 512 of Hong2 with the control stage of Lee such that the gates of transistors T71, T73, T75, and T77 of Hong2 are connected to N1 of Lee and the gates of transistors T72, T74, T76, and T78 of Hong2 are connected to N2 of Lee resulting in wherein the control stage comprises: a first transistor connected to the input terminal and the first node, and comprising a gate connected to a first clock terminal to which one of a plurality of clock signals is input; a second transistor connected to the second node and the first clock terminal, and comprising a gate connected to the first node; and a third transistor connected to the second voltage input terminal and the second node, and comprising a gate connected to the first clock terminal, as taught by Lee so as to efficiently utilize the space of the non-display area (¶55).
With respect to Claim 6, claim 4 is incorporated, Choi, Hong1, and Hong2 combined do not teach wherein each of the m output stages comprises: a fourth transistor connected to the first voltage input terminal and the output terminal, and comprising a gate connected to the second node; a fifth transistor connected to the output terminal and a second clock terminal to which another one of the plurality of clock signals is input, and comprising a gate connected to a third node; and a sixth transistor connected to the first node and the third node, and comprising a gate connected to the second voltage input terminal.
Lee teaches a display device (fig. 1, item 100; ¶37) comprising: a substrate (fig. 1, item 101, display devices comprise a substrate) comprising a display area (fig. 1, item AA; ¶37) and a non-display area (fig. 1, item NA; ¶37) surrounding the display area; a plurality of pixels (fig. 1, item 102; ¶37) disposed on the substrate in the display area; a plurality of drivers (fig. 1, item 110, 120, 130) in the non-display area; wherein, at least one first driver of the plurality of drivers comprises a control stage (fig. 1, items 1210 and 1220; ¶83) and an output stage (fig. 7, item 1230; ¶83), the control stage is connected to an input terminal to which a start signal is input (fig. 7, item SSP1: start signal; ¶79), a first voltage input terminal to which a first voltage is input (fig. 7, item VDD) and a second voltage input terminal to which a second voltage is input (fig. 7, item VSS), and controls voltages of a first node (fig. 7, item N3: first node) and a second node (fig. 7, item N1 = second node); wherein the control stage (fig. 7, item 1210 and 1220; ¶83) comprises: a first transistor (fig. 7, item M2) connected to the input terminal and the first node (fig. 7, item N3: first node), and comprising a gate connected to a first clock terminal (fig. 7, item CLK1) to which one of a plurality of clock signals is input; a second transistor (fig. 7, item M7) connected to the second node (fig. 7, item N1 = second node) and the first clock terminal, and comprising a gate connected to the first node (fig. 7); and a third transistor (fig. 7, item M8) connected to the second voltage input terminal (fig. 7, item VSS) and the second node (fig. 7, N1 = second node), and comprising a gate connected to the first clock terminal (fig. 7); wherein each of the m output stages comprises: a fourth transistor (fig. 7, item M5) connected to the first voltage input terminal (fig. 7, item VDD) and the output terminal (fig. 7), and comprising a gate connected to the second node (fig. 7, item N1 = second node); a fifth transistor (fig. 7, item M6) connected to the output terminal (fig. 7, item S1) and a second clock terminal (fig. 7, item CLK2) to which another one of the plurality of clock signals is input, and comprising a gate connected to a third node (fig. 7, item N2: third node); and a sixth transistor (fig. 7, item M1) connected to the first node (fig. 7, item N3: first node) and the third node (fig. 7, item N2: third node), and comprising a gate connected to the second voltage input terminal (fig. 7, item VSS).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined display apparatus of Choi, Hong1, and Hong2, to replace items 502, 504, 506, 508, 510, and 512 of Hong with the control stage of Lee such that the gates of transistors T71, T73, T75, and T77 of Hong2 are connected to N1 of Lee and the gates of transistors T72, T74, T76, and T78 of Hong2 are connected to N2 of Lee resulting in wherein each of the m output stages comprises: a fourth transistor connected to the first voltage input terminal and the output terminal, and comprising a gate connected to the second node; a fifth transistor connected to the output terminal and a second clock terminal to which another one of the plurality of clock signals is input, and comprising a gate connected to a third node; and a sixth transistor connected to the first node and the third node, and comprising a gate connected to the second voltage input terminal, as taught by Lee so as to efficiently utilize the space of the non-display area (¶55).
With respect to Claim 7, claim 6 is incorporated, Choi, Hong1, and Hong2 combined do not teach wherein at least one of the m output stages further comprises at least one of: a first capacitor connected to the first voltage input terminal and the second node; and a second capacitor connected to the output terminal and the third node.
Lee teaches a display device (fig. 1, item 100; ¶37) comprising: a substrate (fig. 1, item 101, display devices comprise a substrate) comprising a display area (fig. 1, item AA; ¶37) and a non-display area (fig. 1, item NA; ¶37) surrounding the display area; a plurality of pixels (fig. 1, item 102; ¶37) disposed on the substrate in the display area; a plurality of drivers (fig. 1, item 110, 120, 130) in the non-display area; wherein, at least one first driver of the plurality of drivers comprises a control stage (fig. 1, items 1210 and 1220; ¶83) and an output stage (fig. 7, item 1230; ¶83), the control stage is connected to an input terminal to which a start signal is input (fig. 7, item SSP1: start signal; ¶79), a first voltage input terminal to which a first voltage is input (fig. 7, item VDD) and a second voltage input terminal to which a second voltage is input (fig. 7, item VSS), and controls voltages of a first node (fig. 7, item N3: first node) and a second node (fig. 7, item N1 = second node); wherein the control stage (fig. 7, item 1210 and 1220; ¶83) comprises: a first transistor (fig. 7, item M2) connected to the input terminal and the first node (fig. 7, item N3: first node), and comprising a gate connected to a first clock terminal (fig. 7, item CLK1) to which one of a plurality of clock signals is input; a second transistor (fig. 7, item M7) connected to the second node (fig. 7, item N1 = second node) and the first clock terminal, and comprising a gate connected to the first node (fig. 7); and a third transistor (fig. 7, item M8) connected to the second voltage input terminal (fig. 7, item VSS) and the second node (fig. 7, N1 = second node), and comprising a gate connected to the first clock terminal (fig. 7); wherein each of the m output stages comprises: a fourth transistor (fig. 7, item M5) connected to the first voltage input terminal (fig. 7, item VDD) and the output terminal (fig. 7), and comprising a gate connected to the second node (fig. 7, item N1 = second node); a fifth transistor (fig. 7, item M6) connected to the output terminal (fig. 7, item S1) and a second clock terminal (fig. 7, item CLK2) to which another one of the plurality of clock signals is input, and comprising a gate connected to a third node (fig. 7, item N2: third node); and a sixth transistor (fig. 7, item M1) connected to the first node (fig. 7, item N3: first node) and the third node (fig. 7, item N2: third node), and comprising a gate connected to the second voltage input terminal (fig. 7, item VSS); wherein at least one of the m output stages further comprises at least one of: a first capacitor (fig. 1, item C2) connected to the first voltage input terminal (fig. 7, item VDD) and the second node (fig. 7, item N1 = second node); and a second capacitor (fig. 7, item C1) connected to the output terminal (fig. 7, item S1) and the third node (fig. 7, item N2: third node).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined display apparatus of Choi, Hong1, and Hong2, to replace items 502, 504, 506, 508, 510, and 512 of Hong2 with the control stage of Lee such that the gates of transistors T71, T73, T75, and T77 of Hong2 are connected to N1 of Lee and the gates of transistors T72, T74, T76, and T78 of Hong2 are connected to N2 of Lee resulting in wherein at least one of the m output stages further comprises at least one of: a first capacitor connected to the first voltage input terminal and the second node; and a second capacitor connected to the output terminal and the third node, as taught by Lee so as to efficiently utilize the space of the non-display area (¶55).
With respect to Claim 13, claim 12 is incorporated, Choi, Hong1, and Hong2combined do not teach wherein the control stage comprises: a first transistor connected to the input terminal and the first node, and comprising a gate connected to a first clock terminal to which one of a plurality of clock signals is input; a second transistor connected to the second node and the first clock terminal, and comprising a gate connected to the first node; and a third transistor connected to the second voltage input terminal and the second node, and comprising a gate connected to the first clock terminal.
Lee teaches a display device (fig. 1, item 100; ¶37) comprising: a substrate (fig. 1, item 101, display devices comprise a substrate) comprising a display area (fig. 1, item AA; ¶37) and a non-display area (fig. 1, item NA; ¶37) surrounding the display area; a plurality of pixels (fig. 1, item 102; ¶37) disposed on the substrate in the display area; a plurality of drivers (fig. 1, item 110, 120, 130) in the non-display area; wherein, at least one first driver of the plurality of drivers comprises a control stage (fig. 1, items 1210 and 1220; ¶83) and an output stage (fig. 7, item 1230; ¶83), the control stage is connected to an input terminal to which a start signal is input (fig. 7, item SSP1: start signal; ¶79), a first voltage input terminal to which a first voltage is input (fig. 7, item VDD) and a second voltage input terminal to which a second voltage is input (fig. 7, item VSS), and controls voltages of a first node (fig. 7, item N3: first node) and a second node (fig. 7, item N1 = second node); wherein the control stage (fig. 7, item 1210 and 1220; ¶83) comprises: a first transistor (fig. 7, item M2) connected to the input terminal and the first node (fig. 7, item N3: first node), and comprising a gate connected to a first clock terminal (fig. 7, item CLK1) to which one of a plurality of clock signals is input; a second transistor (fig. 7, item M7) connected to the second node (fig. 7, item N1 = second node) and the first clock terminal, and comprising a gate connected to the first node (fig. 7); and a third transistor (fig. 7, item M8) connected to the second voltage input terminal (fig. 7, item VSS) and the second node (fig. 7, N1 = second node), and comprising a gate connected to the first clock terminal (fig. 7).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined display apparatus of Choi, Hong1, and Hong2, to replace items 502, 504, 506, 508, 510, and 512 of Hong2 with the control stage of Lee such that the gates of transistors T71, T73, T75, and T77 of Hong2 are connected to N1 of Lee and the gates of transistors T72, T74, T76, and T78 of Hong2 are connected to N2 of Lee resulting in wherein the control stage comprises: a first transistor connected to the input terminal and the first node, and comprising a gate connected to a first clock terminal to which one of a plurality of clock signals is input; a second transistor connected to the second node and the first clock terminal, and comprising a gate connected to the first node; and a third transistor connected to the second voltage input terminal and the second node, and comprising a gate connected to the first clock terminal, as taught by Lee so as to efficiently utilize the space of the non-display area (¶55).
With respect to Claim 14, claim 13 is incorporated, Choi, Hong1, and Hong2 combined do not teach wherein each of the m output stages comprises: a fourth transistor connected to the first voltage input terminal and the output terminal, and comprising a gate connected to the second node; a fifth transistor connected to the output terminal and a second clock terminal to which another one of the plurality of clock signals is input, and comprising a gate connected to a third node; and a sixth transistor connected to the first node and the third node, and comprising a gate connected to the second voltage input terminal.
Lee teaches a display device (fig. 1, item 100; ¶37) comprising: a substrate (fig. 1, item 101, display devices comprise a substrate) comprising a display area (fig. 1, item AA; ¶37) and a non-display area (fig. 1, item NA; ¶37) surrounding the display area; a plurality of pixels (fig. 1, item 102; ¶37) disposed on the substrate in the display area; a plurality of drivers (fig. 1, item 110, 120, 130) in the non-display area; wherein, at least one first driver of the plurality of drivers comprises a control stage (fig. 1, items 1210 and 1220; ¶83) and an output stage (fig. 7, item 1230; ¶83), the control stage is connected to an input terminal to which a start signal is input (fig. 7, item SSP1: start signal; ¶79), a first voltage input terminal to which a first voltage is input (fig. 7, item VDD) and a second voltage input terminal to which a second voltage is input (fig. 7, item VSS), and controls voltages of a first node (fig. 7, item N3: first node) and a second node (fig. 7, item N1 = second node); wherein the control stage (fig. 7, item 1210 and 1220; ¶83) comprises: a first transistor (fig. 7, item M2) connected to the input terminal and the first node (fig. 7, item N3: first node), and comprising a gate connected to a first clock terminal (fig. 7, item CLK1) to which one of a plurality of clock signals is input; a second transistor (fig. 7, item M7) connected to the second node (fig. 7, item N1 = second node) and the first clock terminal, and comprising a gate connected to the first node (fig. 7); and a third transistor (fig. 7, item M8) connected to the second voltage input terminal (fig. 7, item VSS) and the second node (fig. 7, N1 = second node), and comprising a gate connected to the first clock terminal (fig. 7); wherein each of the m output stages comprises: a fourth transistor (fig. 7, item M5) connected to the first voltage input terminal (fig. 7, item VDD) and the output terminal (fig. 7), and comprising a gate connected to the second node (fig. 7, item N1 = second node); a fifth transistor (fig. 7, item M6) connected to the output terminal (fig. 7, item S1) and a second clock terminal (fig. 7, item CLK2) to which another one of the plurality of clock signals is input, and comprising a gate connected to a third node (fig. 7, item N2: third node); and a sixth transistor (fig. 7, item M1) connected to the first node (fig. 7, item N3: first node) and the third node (fig. 7, item N2: third node), and comprising a gate connected to the second voltage input terminal (fig. 7, item VSS).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined display apparatus of Choi, Hong1, and Hong2, to replace items 502, 504, 506, 508, 510, and 512 of Hong2 with the control stage of Lee such that the gates of transistors T71, T73, T75, and T77 of Hong2 are connected to N1 of Lee and the gates of transistors T72, T74, T76, and T78 of Hong2 are connected to N2 of Lee resulting in wherein each of the m output stages comprises: a fourth transistor connected to the first voltage input terminal and the output terminal, and comprising a gate connected to the second node; a fifth transistor connected to the output terminal and a second clock terminal to which another one of the plurality of clock signals is input, and comprising a gate connected to a third node; and a sixth transistor connected to the first node and the third node, and comprising a gate connected to the second voltage input terminal, as taught by Lee so as to efficiently utilize the space of the non-display area (¶55).
With respect to Claim 15, claim 14 is incorporated, Choi, Hong1, and Hong2 combined do not teach wherein, at least one of the m output stages further comprises at least one of: a first capacitor connected to the first voltage input terminal and the second node; and a second capacitor connected to the output terminal and the third node.
Lee teaches a display device (fig. 1, item 100; ¶37) comprising: a substrate (fig. 1, item 101, display devices comprise a substrate) comprising a display area (fig. 1, item AA; ¶37) and a non-display area (fig. 1, item NA; ¶37) surrounding the display area; a plurality of pixels (fig. 1, item 102; ¶37) disposed on the substrate in the display area; a plurality of drivers (fig. 1, item 110, 120, 130) in the non-display area; wherein, at least one first driver of the plurality of drivers comprises a control stage (fig. 1, items 1210 and 1220; ¶83) and an output stage (fig. 7, item 1230; ¶83), the control stage is connected to an input terminal to which a start signal is input (fig. 7, item SSP1: start signal; ¶79), a first voltage input terminal to which a first voltage is input (fig. 7, item VDD) and a second voltage input terminal to which a second voltage is input (fig. 7, item VSS), and controls voltages of a first node (fig. 7, item N3: first node) and a second node (fig. 7, item N1 = second node); wherein the control stage (fig. 7, item 1210 and 1220; ¶83) comprises: a first transistor (fig. 7, item M2) connected to the input terminal and the first node (fig. 7, item N3: first node), and comprising a gate connected to a first clock terminal (fig. 7, item CLK1) to which one of a plurality of clock signals is input; a second transistor (fig. 7, item M7) connected to the second node (fig. 7, item N1 = second node) and the first clock terminal, and comprising a gate connected to the first node (fig. 7); and a third transistor (fig. 7, item M8) connected to the second voltage input terminal (fig. 7, item VSS) and the second node (fig. 7, N1 = second node), and comprising a gate connected to the first clock terminal (fig. 7); wherein each of the m output stages comprises: a fourth transistor (fig. 7, item M5) connected to the first voltage input terminal (fig. 7, item VDD) and the output terminal (fig. 7), and comprising a gate connected to the second node (fig. 7, item N1 = second node); a fifth transistor (fig. 7, item M6) connected to the output terminal (fig. 7, item S1) and a second clock terminal (fig. 7, item CLK2) to which another one of the plurality of clock signals is input, and comprising a gate connected to a third node (fig. 7, item N2: third node); and a sixth transistor (fig. 7, item M1) connected to the first node (fig. 7, item N3: first node) and the third node (fig. 7, item N2: third node), and comprising a gate connected to the second voltage input terminal (fig. 7, item VSS); wherein at least one of the m output stages further comprises at least one of: a first capacitor (fig. 1, item C2) connected to the first voltage input terminal (fig. 7, item VDD) and the second node (fig. 7, item N1 = second node); and a second capacitor (fig. 7, item C1) connected to the output terminal (fig. 7, item S1) and the third node (fig. 7, item N2: third node).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined display apparatus of Choi, Hong1, and Hong2, to replace items 502, 504, 506, 508, 510, and 512 of Hong2 with the control stage of Lee such that the gates of transistors T71, T73, T75, and T77 of Hong2 are connected to N1 of Lee and the gates of transistors T72, T74, T76, and T78 of Hong2 are connected to N2 of Lee resulting in wherein, at least one of the m output stages further comprises at least one of: a first capacitor connected to the first voltage input terminal and the second node; and a second capacitor connected to the output terminal and the third node, as taught by Lee so as to efficiently utilize the space of the non-display area (¶55).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Choi, Hong1, Hong2, and Lee as applied to claim 4 above, and further in view of Kim et al. (Pub. No.: US 2023/0096265 A1) hereinafter referred to as Lee.
With respect to Claim 5, claim 4 is incorporated, Choi, Hong1, Hong2, and Lee combined do not teach wherein the first transistor comprises a 1-1 transistor and a 1-2 transistor, the 1-1 transistor is connected to the input terminal and the 1-2 transistor, the 1-2 transistor is connected to the first node and the 1-1 transistor, and a gate of the 1-1 transistor and a gate of the 1-2 transistor are connected to the first clock terminal.
Kim teaches a display device (fig. 1, item 100; ¶37) comprising: a substrate (¶42) comprising a display area (fig. 1, item AA) and a non-display area (fig. 1, area surrounding item AA) surrounding the display area; a plurality of pixels (fig. 1, item 101; ¶39-40) disposed on the substrate in the display area; a plurality of drivers (fig. 1, items 121, 122, and 112; ¶62) in the non-display area; the at least one first driver comprises a control stage (fig. 6, item 62; ¶102) and m output stages (fig. 6, items 72 and 74), the control stage is connected to an input terminal (fig. 6, input terminal of item 62 is where GVST is input) to which a start signal is input (figs. 6 and 8, item GVST; ¶115), a first voltage input terminal to which a first voltage is input (fig. 8, item VGH1: first voltage), and a second voltage input terminal to which a second voltage is input (fig. 8, item VGL: second voltage), and controls voltages of a first node and a second node (fig. 8, item Q’ = first node and item Q = second node), wherein, the control stage comprises: a first transistor (fig. 8, item T1; ¶116) connected to the input terminal (fig. 6, input terminal of item 62 is where GVST is input) and the first node (fig. 8, item Q’ = first node), and comprising a gate connected to a first clock terminal (fig. 8, item GCLK2) to which one of a plurality of clock signals is input; wherein the first transistor (fig. 8, item T1; ¶116) comprises a 1-1 transistor (fig. 8, item T1A; ¶116) and a 1-2 transistor (fig. 8, item T1B; ¶116), the 1-1 transistor is connected to the input terminal (fig. 8, item GVST; ¶115) and the 1-2 transistor (fig. 8, item T1B), the 1-2 transistor (fig. 8, item T1B) is connected to the first node (fig. 8, item Q’ = first node) and the 1-1 transistor (fig. 8, item T1A), and a gate of the 1-1 transistor (fig. 8, item T1A) and a gate of the 1-2 (fig. 8, item T1B) transistor are connected to the first clock terminal (fig. 8, item CGCLK2).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined display apparatus of Choi, Hong1, Hong2, and Lee, wherein the first transistor comprises a 1-1 transistor and a 1-2 transistor, the 1-1 transistor is connected to the input terminal and the 1-2 transistor, the 1-2 transistor is connected to the first node and the 1-1 transistor, and a gate of the 1-1 transistor and a gate of the 1-2 transistor are connected to the first clock terminal, as taught by Lee so as to suppress leakage current (¶90).
Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Choi, Hong1, and Hong2 as applied to claims 2 above, and further in view of Kim et al. (Pub. No.: US 2022/0198974 A1) hereinafter referred to as Kim.
With respect to Claim 8, claim 2 is incorporated, Choi does not teach wherein o/m is a natural number greater than or equal to 2.
Hong1 teaches a display apparatus (fig. 1, item 100; ¶79) comprising: a substrate (fig. 1, item SUB; ¶82) comprising a display area (fig. 1, item DA; ¶85) and a non-display area (fig. 1, item NDA; ¶85) surrounding the display area; a plurality of pixels (fig. 1, item SP; ¶84) disposed on the substrate in the display area; and a plurality of driver sets (figs. 1-2 and 3B, item 130) spaced apart from each other in the non-display area; one driver set (figs. 2 and 3B; ¶135) among the plurality of driver sets comprises at least one first driver (fig. 3B, item 320; ¶142) and at least one second driver (fig. 3B, item 310; ¶137), the at least one first driver is connected to m output lines connected to some of the plurality of pixels (¶136, “a m-th gate driving circuit 320 corresponding to the m-th subpixel SP(m)”), and the at least one second driver is connected to n output lines connected to some of the plurality of pixels (¶136, “a n-th gate driving circuit 310 corresponding to the n-th subpixel SP(n)”), wherein m is not equal to n (¶133; ¶355, “a n-th first scan line corresponding to the n-th subpixel row and a m-th first scan line corresponding to a m-th subpixel row which is identical to or different from the n-th subpixel row”; claim 1, “a n-th second scan line corresponding to the n-th subpixel row and a m-th second scan line corresponding to the m-th subpixel row, and the plurality of the light emission lines includes a n-th light emission line corresponding to the n-th subpixel row and m-th light emission line corresponding to the m-th subpixel row, wherein n is a natural number and m is a natural number that is either equal to or different from n”).
Although Hong1 does not explicitly teach wherein o/m is a natural number greater than or equal to 2, Hong1 teaches that m and n are different (¶133; ¶355; claim 1) where the number m and n are 1 or greater and not equal to each other, therefore many number combinations exist where m and n are not equal to each other and there exists a least common multiple of m and n being o, such that o/m is a natural number greater than or equal to 2.
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display apparatus of Choi and Hong2, wherein o/m is a natural number greater than or equal to 2, as taught by Hong1, so as to provide a design alternatives since the output lines of each driver may vary in any number (¶133, “m is n or a number different from n”).
Hong1 teaches the first driver comprises a control stage (fig. 3B, item 323) and scan stage (fig. 3B, item 311/312). Choi, Hong1, and Hong2 combined do not explicitly mention and one of the m output stages of one of the o/m first drivers is connected to the control stage of another one of the o/m first drivers.
Kim teaches a display apparatus (figs. 1-5; ¶42; ¶65) comprising: a substrate (¶40-41) comprising a display area (fig. 1, item 120; ¶44) and a non-display area (fig. 1, area surrounding item 120; ¶44) surrounding the display area; a plurality of pixels disposed on the substrate in the display area (¶44); and a driver set (fig. 1, item 110a and 110; ¶66) spaced apart from each other in the non-display area; wherein, one driver set among the plurality of driver sets comprises at least one first driver (fig. 1, item 110a) and at least one second driver (fig. 1, item 110b), the at least one first driver is connected to m output lines connected to some of the plurality of pixels (fig. 6, EM(n-2)), and one of the m output stages of one of the o/m first drivers is connected to the control stage of another one of the o/m first drivers (fig. 6, EM(n-1)).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined display apparatus of Choi, Hong1, and Hong2, such that one of the output stages of one of the drivers is connected to the control stage of another one of the drivers, resulting in one of the m output stages of one of the o/m first drivers is connected to the control stage of another one of the o/m first drivers, as taught by Kim so as to provide emission control driving.
With respect to Claim 16, claim 12 is incorporated, Choi, Hong1, and Hong2 combined do not explicitly mention wherein, the driver set comprises at least two first drivers and the output terminal of one of the m output stages of one of the at least two first drivers is connected to the input terminal of the control stage of another one of the at least two first drivers.
Kim teaches a display apparatus (figs. 1-5; ¶42; ¶65) comprising: a substrate (¶40-41) comprising a display area (fig. 1, item 120; ¶44) and a non-display area (fig. 1, area surrounding item 120; ¶44) surrounding the display area; a plurality of pixels disposed on the substrate in the display area (¶44); and a driver set (fig. 5, item GIP close to display: first and GIP close to external border: second); wherein, the driver set comprises at least two first driver (fig. 6, item EM(n-2), EM(n-1), EM(n), and EM(n+1)) and the output terminal of one of the m output stages of one of the at least two first drivers (fig. 6, item EM(n-2) is connected to the input terminal of the control stage (fig. 6, item EM(n-1)) of another one of the at least two first drivers.
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined display apparatus of Choi, Hong1, and Hong2, wherein, the driver set comprises at least two first drivers and the output terminal of one of the m output stages of one of the at least two first drivers is connected to the input terminal of the control stage of another one of the at least two first drivers, as taught by Kim so as to provide emission control driving.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DONNA V Bocar/ Primary Examiner, Art Unit 2621
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