Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 6/24/2026 have been fully considered but they are not persuasive. The applicant arguments, see pages 8-11 of the remarks, fail to consider that the Office is required to give the claims their broadest reasonable interpretation, of which terms such as “operational rule”, “operations” and “parameters” are incredibly broad, and easily open themselves up to being covered by inherent properties of the prior art. For example the claim term “operational rule”, if something happens essentially automatically in the prior art then it is an “operational rule”. In the prior art, if an operation request is within a certain address range it indicates that processing should be done in an operating processing mode (i.e. that IS the “operational rule”). The operating processing mode of the prior art includes a plurality of (“second”) operations to be performed based on the original operation request, all operations require operands (i.e. “operation parameters” such as data or addresses).
It should also be noted that simply breaking down a complex task (operation request) into a plurality of smaller operations to complete the overall task is a ubiquitous concept practiced throughout history. The Pharoah’s of Egypt just demanded pyramids be built, they didn’t directly specify how each stone was to be carved and placed, nor does an operating system tell a disk drive exactly how to do it’s thing to read/write data.
Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
Applicant's arguments do not comply with 37 CFR 1.111(c) because they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. Further, they do not show how the amendments avoid such references or objections.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 8-13, 17-20 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Lee (US 2020/0293319).
In regards to claims 1 and 13, Lee teaches
A method implemented by a storage device, wherein the method comprises: (fig. 1, memory device 200)
receiving, from a processing device, an operation request requesting to perform a first operation; (¶73-76, fig. 6, the host may transmit to the memory device a command in a second range address)
obtaining, based on the operation request, an operation rule of the first operation and a first operation parameter required by the first operation, wherein the operation rule describes a plurality of second operations obtained after splitting the first operation and a performing sequence of the plurality of second operations, (¶73-76, fig. 6, the host may transmit to the memory device a command in a second range address, the second address range indicating that processing should be done in an operating processing mode, using indicated instructions that were previously sent (i.e. a plurality of second operations)
wherein the first operation parameter comprises second operation parameters required by the plurality of second operations; and sequentially invoking, based on the performing sequence, hardware operators of the plurality of second operations and the second operation parameters to perform the plurality of second operations. (¶73-85, fig. 6-8, the command received may include an address for data to be read and acted upon or may include the data itself (i.e. second operation parameters), and the PIM circuit may perform a series of operations (i.e. sequentially invoking the plurality of second operations)
In regards to claim 8, Lee teaches
A device, comprising: at least one medium chip comprising: a medium array configured to store data; and computing circuit logic configured to: (fig. 3, memory device 320 (medium chip) comprises memory 321 (medium array) and PIM circuits 322 (computing circuit logic)
obtain an operation rule of a first operation and a first operation parameter required by the first operation (¶73-76, fig. 6, the host may transmit to the memory device a command in a second range address)
wherein the operation rule describes a plurality of second operations obtained after splitting the first operation and a performing sequence of the plurality of second operations, (¶73-76, fig. 6, the host may transmit to the memory device a command in a second range address, the second address range indicating that processing should be done in an operating processing mode, using indicated instructions that were previously sent (i.e. a plurality of second operations)
wherein the first operation parameter comprises second operation parameters required by the plurality of second operations; and perform, based on the operation rule and the first operation parameter, the first operation on the data. (¶73-85, fig. 6-8, the command received may include an address for data to be read and acted upon or may include the data itself (i.e. second operation parameters), and the PIM circuit may perform a series of operations (i.e. sequentially invoking the plurality of second operations)
In regards to claim 9, Lee teaches
wherein the computing circuit logic comprises hardware operators of the plurality of second operations and a cache, wherein the cache is configured to store the operation rule and the first operation parameter, (fig. 2, ¶49, the instruction memory 224 (cache) stores the instructions in a circular queue (i.e. cache), ¶46 the PIM circuit may also include registers to temporarily store operating paramters/results)
wherein the computing circuit logic is further configured to: obtain, from the cache, the operation rule and the first operation parameter; and sequentially invoke, based on the performing sequence, the hardware operators and the second operation parameters to perform the plurality of second operations on the data. (¶73-85, fig. 6-8, the command received may include an address for data to be read and acted upon or may include the data itself (i.e. second operation parameters), and the PIM circuit may perform a series of operations according to the instructions stored in the instruction memory (cache) (i.e. sequentially invoking the plurality of second operations)
In regards to claim 10, Lee further teaches
wherein the medium array and the computing circuit logic are disposed in a stacked manner. (fig. 5 shows that the memory and logic circuitry can be stacked)
In regards to claim 11, Lee further teaches
receive, from a processing device, a rule configuration request requesting to configure the operation rule and configure the operation rule for the computing circuit logic; and receive, from the processing device, a parameter configuration request requesting to configure the first operation parameter and configure the first operation parameter for the computing circuit logic. (¶35-36 the controller can transmit a series of instructions to be loaded into the memory 200 such that the series of instructions can later be commanded to be executed by a processing element, see fig. 6, where the instructions are transmitted and stored and then later executed in the operation processing mode when the host sends the correct command/address. ¶54 teaches that an address map may store the address mappings to the processing element sets of instructions/parameters.)
In regards to claim 12, Lee further teaches
wherein the medium controller is further configured to: receive, from the processing device, an operation request requesting to perform the first operation; and send, to the computing circuit logic, an operation indication instructing the computing circuit logic to perform the first operation. (¶35-36 the controller can transmit a series of instructions to be loaded into the memory 200 such that the series of instructions can later be commanded to be executed by a processing element, see fig. 6, where the instructions are transmitted and stored and then later executed in the operation processing mode when the host sends the correct command/address. ¶54 teaches that an address map may store the address mappings to the processing element sets of instructions/parameters.)
In regards to claim 17, Lee further teaches
wherein the hardware operators are hardware logics built in the storage device. (¶99 teaches that dedicated hardware can be used to implement specific operations optimized for particular software.)
In regards to claim 18, Lee further teaches
wherein the storage device comprises a medium chip, wherein the medium chip comprises a medium array and a computing circuit logic (fig. 3, memory device 320 (medium chip) comprises memory 321 (medium array) and PIM circuits 322 (computing circuit logic
wherein the medium array is configured to store first data, wherein the computing circuit logic is configured to perform the first operation on second data in the medium array or third data to be written into the medium array, (¶73-85, fig. 6-8, the command received may include an address for data (i.e. first or second data stored in the array) to be read and acted upon or may include the data itself (i.e. third data), and the PIM circuit may perform a series of operations (i.e. sequentially invoking the plurality of second operations) and either store the data in the array or send the data to the host depending on if the command was a write or read command.
wherein the medium array and the computing circuit logic are located in the storage device in a stacked form. (fig. 5 shows that the memory and logic circuitry can be stacked)
In regards to claim 19, Lee further teaches
wherein the computing circuit logic comprises a cache and the hardware operators, and wherein the cache stores the operation rule and the first operation parameter. (fig. 2, ¶49, the instruction memory 224 (cache) stores the instructions in a circular queue (i.e. cache), ¶46 the PIM circuit may also include registers to temporarily store operating paramters/results)
In regards to claim 20, Lee further teaches
wherein the storage device and the processing device are connected through a system bus. (¶29 the memory controller/host/processing device can be connected to the memory device via PCI-E (i.e. a system bus)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-7, 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2020/0293319) in view of Official Notice.
In regards to claims 2 and 14, Lee further teaches
wherein before receiving the operation request, the method further comprises: receiving, from the processing device, a rule configuration request requesting to configure the operation rule, wherein the rule configuration request carries the operation rule and a [logical] address of the operation rule; and storing, in a storage location indicated by the [logical] address, the operation rule. (¶35-36 the controller can transmit a series of instructions to be loaded into the memory 200 such that the series of instructions can later be commanded to be executed by a processing element, see fig. 6, where the instructions are transmitted and stored and then later executed in the operation processing mode when the host sends the correct command/address. ¶54 teaches that an address map may store the address mappings to the processing element sets of instructions/parameters.)
Lee may not explicitly teach that logical addressing is used. The examiner is taking official notice that the use of physical addresses, logical addresses, and virtual addresses and mapping/translating between the addressing types is well-known in the art prior to the effective filing date of the claimed invention. One of ordinary skill in the art prior to the effective filing date of the claimed invention could have replaced the generic address mapping of Lee to use logical addressing and been able to achieve predictable results. The motivation for such is that logical addressing lets the memory device handle the physical addressing and translations, such that physical addresses can be changed (due to maintenance operations and such), without involvement or notification to the host system.
In regards to claim 3 and 15, Lee further teaches
wherein before receiving the operation request, the method further comprises: receiving, from the processing device, a parameter configuration request requesting to configure the first operation parameter, wherein the parameter configuration request carries the first operation parameter and a [logical] address of the first operation parameter; and storing, in a storage location indicated by the [logical] address, the first operation parameter. (¶35-36 the controller can transmit a series of instructions to be loaded into the memory 200 such that the series of instructions can later be commanded to be executed by a processing element, see fig. 6, where the instructions are transmitted and stored and then later executed in the operation processing mode when the host sends the correct command/address. ¶54 teaches that an address map may store the address mappings to the processing element sets of instructions/parameters.)
Lee may not explicitly teach that logical addressing is used. The examiner is taking official notice that the use of physical addresses, logical addresses, and virtual addresses and mapping/translating between the addressing types is well-known in the art prior to the effective filing date of the claimed invention. One of ordinary skill in the art prior to the effective filing date of the claimed invention could have replaced the generic address mapping of Lee to use logical addressing and been able to achieve predictable results. The motivation for such is that logical addressing lets the memory device handle the physical addressing and translations, such that physical addresses can be changed (due to maintenance operations and such), without involvement or notification to the host system.
In regards to claim 4 and 16, Lee further teaches
further comprising reserving, at a request of the processing device, storage locations for the operation rule and the first operation parameter, wherein [logical] addresses of the storage locations are from the processing device. (¶35-36 the controller can transmit a series of instructions to be loaded into the memory 200 (i.e. at a specific address/location) such that the series of instructions can later be commanded to be executed by a processing element, see fig. 6, where the instructions are transmitted and stored and then later executed in the operation processing mode when the host sends the correct command/address. ¶54 teaches that an address map may store the address mappings to the processing element sets of instructions/parameters.)
Lee may not explicitly teach that logical addressing is used. The examiner is taking official notice that the use of physical addresses, logical addresses, and virtual addresses and mapping/translating between the addressing types is well-known in the art prior to the effective filing date of the claimed invention. One of ordinary skill in the art prior to the effective filing date of the claimed invention could have replaced the generic address mapping of Lee to use logical addressing and been able to achieve predictable results. The motivation for such is that logical addressing lets the memory device handle the physical addressing and translations, such that physical addresses can be changed (due to maintenance operations and such), without involvement or notification to the host system.
In regards to claim 5, Lee further teaches
reserving storage locations for the operation rule and the first operation parameter; and providing, for the processing device, logical addresses of the operation rule and the first operation parameter. (¶35-36 the controller can transmit a series of instructions to be loaded into the memory 200 (i.e. at a specific address/location) such that the series of instructions can later be commanded to be executed by a processing element, see fig. 6, where the instructions are transmitted and stored and then later executed in the operation processing mode when the host sends the correct command/address. ¶54 teaches that an address map may store the address mappings to the processing element sets of instructions/parameters.)
Lee may not explicitly teach that logical addressing is used. The examiner is taking official notice that the use of physical addresses, logical addresses, and virtual addresses and mapping/translating between the addressing types is well-known in the art prior to the effective filing date of the claimed invention. One of ordinary skill in the art prior to the effective filing date of the claimed invention could have replaced the generic address mapping of Lee to use logical addressing and been able to achieve predictable results. The motivation for such is that logical addressing lets the memory device handle the physical addressing and translations, such that physical addresses can be changed (due to maintenance operations and such), without involvement or notification to the host system.
In regards to claims 6-7, Lee further teaches
wherein the operation request comprises a [virtual] address of the first operation, wherein the [virtual] address is separately associated with storage locations of the operation rule and the first operation parameter, and wherein obtaining the operation rule and the first operation parameter comprises obtaining, from the storage locations, the operation rule and the first operation parameter. obtaining the [virtual address]; and establishing associations between the [virtual] address and the storage locations. (¶35-36 the controller can transmit a series of instructions to be loaded into the memory 200 (i.e. at a specific address/location) such that the series of instructions can later be commanded to be executed by a processing element, see fig. 6, where the instructions are transmitted and stored and then later executed in the operation processing mode when the host sends the correct command/address. ¶54 teaches that an address map may store the address mappings to the processing element sets of instructions/parameters.)
Lee may not explicitly teach that virtual addressing is used. The examiner is taking official notice that the use of physical addresses, logical addresses, and virtual addresses and mapping/translating between the addressing types is well-known in the art prior to the effective filing date of the claimed invention. One of ordinary skill in the art prior to the effective filing date of the claimed invention could have replaced the generic address mapping of Lee to use virtual addressing and been able to achieve predictable results. The motivation for such is that virtual addressing lets the memory device handle the physical addressing and translations, such that physical addresses can be changed (due to maintenance operations and such), without involvement or notification to the host system.
EXAMINER’S NOTE
Examiner has cited particular paragraphs, figures, and/or columns and line numbers in the references applied to the claims above for the convenience of the Applicants. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicants in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON W BLUST whose telephone number is (571)272-6302. The examiner can normally be reached 12-8:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571) 272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JASON W BLUST/Primary Examiner, Art Unit 2132
Prosecution Insights