Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 61, 68, 76 and 79 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 43 and 58 of U.S. Patent No. 12,254,839. Although the claims at issue are not identical, they are not patentably distinct from each other because as the table below shows the claims are patently undistinguishable. Claims 62-67; 69-75; 77-78; and 80 are dependent from claims 61, 68, 76 and 79 and as such suffer from the same deficiencies.
Application: 19/079,148 U.S. Patent No. 12,254,839
61. A pixel of a light-emitting display device, the pixel comprising: a first transistor including a gate coupled to a gate node, a first terminal, and a second terminal;
43. A pixel of a light-emitting display device, the pixel comprising: a first transistor including a gate coupled to a gate node, a first terminal, and a second terminal;
a second transistor including a gate receiving a first signal, a first terminal coupled to a data line, and a second terminal coupled to the first transistor;
a second transistor including a gate receiving a first signal, a first terminal coupled to a data line, and a second terminal coupled to the first terminal of the first transistor;
a third transistor including a gate receiving a second signal, a first terminal coupled to a line of an initialization voltage, and a second terminal coupled to an anode of a light-emitting diode;
a third transistor including a gate receiving a second signal, a first terminal coupled to a line of an initialization voltage, and a second terminal coupled to an anode of a light-emitting diode;
and a fourth transistor including a gate receiving a third signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the light-emitting diode,
and a fourth transistor including a gate receiving a third signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the light-emitting diode,
wherein a frequency of the first signal is different from a frequency of at least one of the second signal and the third signal,
wherein a frequency of the first signal is different from a frequency of at least one of the second signal and the third signal.
wherein the fourth transistor is a PMOS transistor.
wherein the first, second, third and fourth transistors are PMOS transistors.
76. A pixel of a light-emitting display device, the pixel comprising: a first transistor including a gate coupled to a gate node, a first terminal, and a second terminal;
58. (Previously Presented) A pixel of a light-emitting display device, the pixel comprising: a first transistor including a gate coupled to a gate node, a first terminal, and a second terminal;
a second transistor including a gate receiving a first signal, a first terminal coupled to a data line, and a second terminal coupled to the first transistor;
a second transistor including a gate receiving a first signal, a first terminal coupled to a data line, and a second terminal coupled to the first terminal of the first transistor;
a third transistor including a gate receiving a second signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the gate node;
a third transistor including a gate receiving a second signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the gate node;
and a fourth transistor including a gate receiving a third signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to an anode of a light-emitting diode,
and a fourth transistor including a gate receiving a third signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to an anode of a light-emitting diode,
wherein a frame period for the light-emitting display device includes a first sub- frame period and a second sub-frame period,
wherein a frame period for the light-emitting display device includes a first sub- frame period and a second sub-frame period,
wherein, in the first sub-frame period, the second, third and fourth transistors are turned on, wherein, in the second sub-frame period, the fourth transistor is turned on,
wherein, in the first sub-frame period, the second, third and fourth transistors are turned on, wherein, in the second sub-frame period, the fourth transistor is turned on,
and the second and third transistors are not turned on, wherein at least one of the first, second and third transistors is an NMOS transistor, and the fourth transistor is a PMOS transistor.
and the second and third transistors are not turned on, and wherein at least one of the first, second, third and fourth transistors is an NMOS transistor.
Allowable Subject Matter
Claims 61-80 would be allowable if the applicant traverses or otherwise overcomes the above rejection. The applicant must properly traverse the double patenting rejection prior to any final disposition can be determined regarding the application, however regarding the claims as presently presented by the applicant, the Office has not discovered any prior art which discloses or suggests the claim limitations to date.
As the claims are presently presented the representative closest prior art is Lee
US Patent Application (20180174514), hereinafter “Lee” and Lee US Patent
Application (20190051250), hereinafter “Lee II’, which alone, or in combination, do
not provide a teaching, a suggestion or a motivation that could be found either
in the art or within the skill of one of ordinary skill in the art at the time of the
invention to modify or combine the prior art to disclose the cited claim limitations above and more specifically “and a fourth transistor including a gate receiving a third signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the light-emitting diode, wherein a frequency of the first signal is different from a frequency of at least one of the second signal and the third signal” of the claimed invention. Claims 62-67; 69-75; 77-78 and 80; depend from claims 61, 68, 76 and 79 respectively and as such the claims could be allowed when the independent claims are in position for allowance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT J MICHAUD whose telephone number is (571)270-3981. The examiner can normally be reached 8:30 - 5:00.
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/ROBERT J MICHAUD/Examiner, Art Unit 2622