DETAILED ACTION
1. This Office Action is responsive to claims filed for App. 19/079,304 on April 22, 2026. Claims 1-19 are pending.
America Invents Act
2. The present application is being examined under the pre-AIA first to invent provisions.
Information Disclosure Statement
3. The information disclosure statements (IDS) submitted on March 13, 2025 and December 31, 2025 were filed. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al.
( US 2023/0039449 A1 ) in view of Her et al. ( US 2025/0061847 A1 ). Please note Her was provided in an Information Disclosure Statement and the PCT/WIPO has a publication date of November 16, 2023, rendering the reference as a 102(a)(1) available art. For reference, mappings are taken from the US equivalent.
Kim teaches in Claim 1:
A pixel circuit ( Figure 4A, [0077] discloses a sub-pixel circuit 110 ) comprising:
a first transistor including a control electrode connected to a first node, a first electrode connected to a second node and a second electrode connected to a third node ( Figure 4A, [0081] discloses a PWM circuit 11 which includes transistor T3 (read as a first transistor). Please note the control electrode is connected to a first node (see the node just to the right of C1), a second node (see below T3) and a third node (see above T3) );
a second transistor connected to the first node and the second node ( Figure 4A, [0081] discloses transistor T4 which is connected to the interpreted first node and the interpreted second node );
a third transistor configured to apply a data voltage to the first transistor ( Figure 4A, [0081] discloses transistor T2 applies Vdata to T3 );
a seventh transistor connected to a fourth node and configured to apply a driving current to a light emitting element ( Figure 4A, [0080] discloses transistor T8 which is connected to a fourth node (see the node just to the left of T8) and can apply a driving voltage and constant current generator data voltage. Please note T8 is part of constant current generator circuit 112. Please note T8 is a driving transistor and applies to light-emitting element 120 );
a ninth transistor configured to apply a constant-current voltage to the fourth node ( Figure 4A, [0117] discloses transistor T9, which is part of the constant current generator circuit 112, can apply a voltage to the interpreted fourth node. Again, 112 provides a specific voltage to driving transistor T8 which is then applied to light-emitting element 120 ); and
the light emitting element configured to emit a light based on the data voltage and the constant-current voltage ( Figure 4A, [0070] discloses the light-emitting element 120 emits light based on the PWM circuit 111 and constant current generator circuit 112 ); but
Kim does not explicitly teach “wherein the first transistor is an N-type transistor, and wherein the seventh transistor is a P-type transistor.”
However, N and P-type transistor layouts are well known in the art and are often interchangeable based on design needs. To emphasize, in the same field of endeavor, pixel driving circuits using PWM and constant current generation, Her teaches of a similar pixel circuit, ( Figure 4, [0156] ). Her also teaches of various layouts and designs for transistor, notably in [0293] in which each of the transistor T1 to T12 may be one of P or N type transistors. Specifically, Her teaches in [0418] the PWM block can have transistors T1 to T5 and these can be n-type (such as the claimed first transistor). Furthermore, the constant current generation block has transistors T6 to T12 and these can be p-type (such as the claimed seventh transistor). For reference, please compare Figure 4 of Her to Figure 4A of Kim and the akin transistors are applicable as well.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the n and p-type transistor designs, as taught by Her, with the motivation that Her essentially renders it a design choice by explicitly suggesting any of the transistors could be designed using either type, ( Her, [0293] ).
Kim and Her teach in Claim 2:
The pixel circuit of claim 1, wherein the second transistor, the third transistor and the ninth transistor are N-type transistors. ( Her, [0293] notes each of T1 to T12 (which comprise PWM and CCG transistors) can be one of n-type of p-type essentially rendering this a design choice issue. Respectfully, one of ordinary skill in the art would realize that transistors could be designed in either type )
Kim teaches in Claim 3:
The pixel circuit of claim 1, further comprising a sixth transistor including a control electrode configured to receive a first initialization signal, a first electrode connected to the first node and a second electrode connected to a first initialization voltage terminal. ( Figure 4A, [0087] discloses transistor T12 with a control electrode receiving VST, a first electrode connected to the interpreted first node and a second electrode connected to Vinitial )
Kim teaches in Claim 4:
The pixel circuit of claim 1, further comprising a first capacitor including a first electrode configured to receive a sweep signal and a second electrode connected to the first node. ( Figure 4A, [0086] discloses capacitor C1 with a first electrode receiving sweep voltage Sweep and a second electrode connected to the interpreted first node )
Kim teaches in Claim 5:
The pixel circuit of claim 1, further comprising:
a fourth transistor including a control electrode configured to receive a first emission signal, a first electrode configured to receive a first power voltage and a second electrode connected to the second node ( Figure 4A, [0083]-[0084] discloses transistor T1 with a control electrode connected to emission control signal Emi, a first electrode connected to VDD_PWM and second electrode connected to the interpreted second node ); and
a fifth transistor including a control electrode configured to receive a second emission signal, a first electrode connected to the third node and a second electrode connected to the fourth node. ( Figure 4A, [0083]-[0084] discloses transistor T5 with a control electrode connected to emission control signal Emi (respectfully, it is the same emission control signal as Applicant’s Figure 2), a first electrode connected to the interpreted third node and second electrode connected to the interpreted fourth node )
Kim teaches in Claim 6:
The pixel circuit of claim 1, further comprising an eighth transistor including a control electrode configured to receive a first emission signal, a first electrode configured to receive a second power voltage and a second electrode connected to a first electrode of the seventh transistor. ( Figure 4A, [0084] discloses transistor T6 with a control electrode which receives an emission control signal Emi, a first electrode which is connected to VDD_CCG and second electrode connected to the first electrode of T8 )
Kim teaches in Claim 8:
The pixel circuit of claim 1, further comprising a tenth transistor including a control electrode configured to receive a second initialization signal, a first electrode connected to an anode electrode of the light emitting element and a second electrode configured to receive a second initialization voltage. ( Figure 4A, [0088] discloses transistor T13 with a control electrode to receive Test/Discharging, a first electrode connected to the anode of light-emitting element 120 and a second electrode connected to VSS )
Kim teaches in Claim 9:
The pixel circuit of claim 1, further comprising a second capacitor including a first electrode configured to receive a second power voltage and a second electrode connected to the fourth node. ( Figure 4A, [0135] discloses capacitor C2 with a first electrode connected to VDD_PWM and a second electrode connected to the interpreted fourth node )
Kim teaches in Claim 10:
The pixel circuit of claim 1, wherein when the first transistor is turned off and the seventh transistor is turned on in a light emission period, the light emitting element is configured to emit a light ( Figures 4A/4B, [0124] discloses T8 is turned off and the flow of current stops and as such, the reverse is true. Also, please note [0101] as well ), and wherein when the first transistor is turned on in a light emission off period, the seventh transistor is turned off and the light emitting element is configured to stop emitting a light. ( Figures 4A/4B, [0107] discloses when T8 is turned off and the driving current does not flow )
Kim teaches in Claim 11:
The pixel circuit of claim 1, further comprising:
a fourth transistor including a control electrode configured to receive a first emission signal, a first electrode configured to receive a first power voltage and a second electrode connected to the second node ( Figure 4A, [0083]-[0084] discloses transistor T1 with a control electrode connected to emission control signal Emi, a first electrode connected to VDD_PWM and second electrode connected to the interpreted second node ); and
an eighth transistor including a control electrode configured to receive the first emission signal, a first electrode configured to receive a second power voltage and a second electrode connected to a first electrode of the seventh transistor ( Figure 4A, [0084] discloses transistor T6 with a control electrode which receives an emission control signal Emi, a first electrode which is connected to VDD_CCG and second electrode connected to the first electrode of T8 ),
wherein the first power voltage is greater than the second power voltage. ( Respectfully, VDD_PWM is typically the maximum power voltage in a circuit, higher than the others )
Kim teaches in Claim 12:
The pixel circuit of claim 1, further comprising a tenth transistor including a control electrode configured to receive a second initialization signal, a first electrode connected to an anode electrode of the light emitting element and a second electrode configured to receive a second initialization voltage ( Figure 4A, [0088] discloses transistor T13 with a control electrode to receive Test/Discharging, a first electrode connected to the anode of light-emitting element 120 and a second electrode connected to VSS ),
wherein a third power voltage is applied to a cathode electrode of the light emitting element, and wherein the second initialization voltage is less than the third power voltage. ( Respectfully, an initialization transistor which resets the anode of the transistor, such as VAINT, is well known in the art. Examiner asserts Official Notice to this being well known )
Kim teaches in Claim 13:
The pixel circuit of claim 1, wherein the first transistor further includes a second control electrode connected to the third node. ( Figure 4A shows the second control electrode connected to the interpreted third node )
Kim teaches in Claim 15:
The pixel circuit of claim 1, wherein the second transistor includes a control electrode configured to receive a first scan signal, a first electrode connected to the first node and a second electrode connected to the second node ( Figure 4A, [0081] discloses transistor T4 with a control electrode to receive SPWM(n), a first electrode connected to the interpreted first node and a second electrode connected to the interpreted second node ),
wherein the third transistor includes a control electrode configured to receive the first scan signal, a first electrode configured to receive the data voltage and a second electrode connected to the third node ( Figure 4A, [0116] discloses transistor T2 with a control electrode for receiving SPWM(n), a first electrode for receiving Vdata and a second electrode connected to the interpreted third node ),
wherein the seventh transistor includes a control electrode connected to the fourth node, a first electrode connected to a fifth node and a second electrode connected to an anode electrode of the light emitting element ( Figure 4A, [0117] discloses transistor T8 with a control electrode connected to the interpreted fourth node, a first electrode connected to a node just above T8 (read as a fifth node) and a second electrode connected to the anode of light-emitting element 120 ),
wherein the ninth transistor includes a control electrode configured to receive a second scan signal, a first electrode connected to the fourth node and a second electrode connected to a first initialization voltage terminal ( Figure 4A, [0117] discloses transistor T9 with a control electrode receiving SCCG, a first electrode connected to the interpreted fourth node and a second electrode connected to Vinitial ), and
wherein the light emitting element includes the anode electrode and a cathode electrode configured to receive a third power voltage. ( Figure 4A discloses the anode of light-emitting element 120 and a cathode connected to VSS )
Kim teaches in Claim 16:
The pixel circuit of claim 15, further comprising: a fourth transistor including a control electrode configured to receive a first emission signal, a first electrode configured to receive a first power voltage and a second electrode connected to the second node ( Figure 4A, [0083]-[0084] discloses transistor T1 with a control electrode connected to emission control signal Emi, a first electrode connected to VDD_PWM and second electrode connected to the interpreted second node );
a fifth transistor including a control electrode configured to receive a second emission signal, a first electrode connected to the third node and a second electrode connected to the fourth node( Figure 4A, [0083]-[0084] discloses transistor T5 with a control electrode connected to emission control signal Emi (respectfully, it is the same emission control signal as Applicant’s Figure 2), a first electrode connected to the interpreted third node and second electrode connected to the interpreted fourth node );
a sixth transistor including a control electrode configured to receive a first initialization signal, a first electrode connected to the first node and a second electrode connected to the first initialization voltage terminal ( Figure 4A, [0087] discloses transistor T12 with a control electrode receiving VST, a first electrode connected to the interpreted first node and a second electrode connected to Vinitial );
an eighth transistor including a control electrode configured to receive the first emission signal, a first electrode configured to receive a second power voltage and a second electrode connected to the fifth node ( Figure 4A, [0084] discloses transistor T6 with a control electrode which receives an emission control signal Emi, a first electrode which is connected to VDD_CCG and second electrode connected to the interpreted second node );
a tenth transistor including a control electrode configured to receive a second initialization signal, a first electrode connected to the anode electrode of the light emitting element and a second electrode configured to receive a second initialization voltage ( Figure 4A, [0088] discloses transistor T13 with a control electrode to receive Test/Discharging, a first electrode connected to the anode of light-emitting element 120 and a second electrode connected to VSS );
a first capacitor including a first electrode configured to receive a sweep signal and a second electrode connected to the first node ( Figure 4A, [0086] discloses capacitor C1 with a first electrode receiving sweep voltage Sweep and a second electrode connected to the interpreted first node ); and
a second capacitor including a first electrode configured to receive the second power voltage and a second electrode connected to the fourth node. ( Figure 4A, [0135] discloses capacitor C2 with a first electrode connected to VDD_PWM and a second electrode connected to the interpreted fourth node )
Kim and Her teach in Claim 17:
The pixel circuit of claim 16, wherein the second transistor, the third transistor, the sixth transistor and the ninth transistor are N-type transistors, and wherein the fourth transistor, the fifth transistor, the eighth transistor and the tenth transistor are P-type transistors. ( Her, [0293] notes each of T1 to T12 (which comprise PWM and CCG transistors) can be one of n-type of p-type essentially rendering this a design choice issue. Respectfully, one of ordinary skill in the art would realize that transistors could be designed in either type )
Kim teaches in Claim 19:
An electronic apparatus ( Figure 10, [0038] discloses a display device ) comprising:
a display panel including a pixel circuit ( Figure 10, [0051] discloses a display panel 100 );
a gate driver configured to output a gate signal to the pixel circuit ( Figure 10, [0223] discloses a scan driver 230 for applying scan signals ); and
a data driver configured to output a data voltage to the pixel circuit ( Figure 10, [0223] discloses a data driver 220 for applying data voltages Vdata ),
wherein the pixel circuit ( Figure 4A, [0077] discloses a sub-pixel circuit 110 ) comprises:
a first transistor including a control electrode connected to a first node, a first electrode connected to a second node and a second electrode connected to a third node ( Figure 4A, [0081] discloses a PWM circuit 11 which includes transistor T3 (read as a first transistor). Please note the control electrode is connected to a first node (see the node just to the right of C1), a second node (see below T3) and a third node (see above T3) );
a second transistor connected to the first node and the second node ( Figure 4A, [0081] discloses transistor T4 which is connected to the interpreted first node and the interpreted second node );;
a third transistor configured to apply the data voltage to the first transistor ( Figure 4A, [0081] discloses transistor T2 applies Vdata to T3 );
a seventh transistor connected to a fourth node and configured to apply a driving current to a light emitting element ( Figure 4A, [0080] discloses transistor T8 which is connected to a fourth node (see the node just to the left of T8) and can apply a driving voltage and constant current generator data voltage. Please note T8 is part of constant current generator circuit 112. Please note T8 is a driving transistor and applies to light-emitting element 120 );
a ninth transistor configured to apply a constant-current voltage to the fourth node ( Figure 4A, [0117] discloses transistor T9, which is part of the constant current generator circuit 112, can apply a voltage to the interpreted fourth node. Again, 112 provides a specific voltage to driving transistor T8 which is then applied to light-emitting element 120 ); and
the light emitting element configured to emit a light based on the data voltage and the constant-current voltage ( Figure 4A, [0070] discloses the light-emitting element 120 emits light based on the PWM circuit 111 and constant current generator circuit 112 ); but
Kim does not explicitly teach “wherein the first transistor is an N-type transistor, and wherein the seventh transistor is a P-type transistor.”
However, N and P-type transistor layouts are well known in the art and are often interchangeable based on design needs. To emphasize, in the same field of endeavor, pixel driving circuits using PWM and constant current generation, Her teaches of a similar pixel circuit, ( Figure 4, [0156] ). Her also teaches of various layouts and designs for transistor, notably in [0293] in which each of the transistor T1 to T12 may be one of P or N type transistors. Specifically, Her teaches in [0418] the PWM block can have transistors T1 to T5 and these can be n-type (such as the claimed first transistor). Furthermore, the constant current generation block has transistors T6 to T12 and these can be p-type (such as the claimed seventh transistor). For reference, please compare Figure 4 of Her to Figure 4A of Kim and the akin transistors are applicable as well.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the n and p-type transistor designs, as taught by Her, with the motivation that Her essentially renders it a design choice by explicitly suggesting any of the transistors could be designed using either type, ( Her, [0293] ).
Conclusion
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DENNIS P JOSEPH whose telephone number is (571)270-1459. The examiner can normally be reached Monday - Friday 5:30 - 3:30 EST.
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/DENNIS P JOSEPH/Primary Examiner, Art Unit 2621
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