DETAILED ACTION
This FINAL action is in response to Application No. 19/079,415 originally filed 03/13/2025. The amendment presented on 03/04/2026 which provides amendments to claims 1 and 4 is hereby acknowledged. Currently Claims 1-4 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 03/04/2026 have been fully considered but they are not persuasive.
Applicant asserts the amended portion of the claims “correspond to the selection periods corresponding to the display gradations, so that at least two identical pixel values are converted into different pixel values in the selection periods corresponding to each of the display gradations.” is not taught by the prior art of record however The Office respectfully disagrees. Uchiyama states [0154] “The display gradation conversion data generator 48 converts the gradation value of the video data VDS into the holding period cumulative optimum value WTDAT_CMPRS_ACC, and outputs the result as the gradation-corrected video data SVDS to the horizontal scanning circuit 51 of the liquid crystal device 5.” In addition, Figure 30 of Uchiyama teaches “an example of a display image of the video data VDS. FIG. 30 shows a state that, in the J-th row (1≤J≤y) of the display pixel unit 50, the number of gradations of the pixels 53 in 10 columns from the 1-st column to 10-th column is 10, and the number of gradations of the pixels 53 in 1000 columns from the 11-th column to 1010-th column is 0, and the number of gradations of the pixels 53 in 910 columns from the 1011-th column to 1920-th column is 255. The J-th row corresponds to the J-th line.” and “FIG. 31 shows an example of a gradation histogram NDP generated by the gradation histogram generator 41 of the signal processing device 4 based on the video data VDS.” This is similarly described and shown in the instant application with respect to Applicant’s Figure 6-7. Finally in paragraph [0192] Uchiyama states “the first display gradation holding period value WTDAT_SLW corresponding to the settling period (corresponding to the number of clocks) in which the slew rate is stabilized is small. However, because the number of pixels (1000) with the gradation value of 0 is larger than the number of pixels (10) with the gradation value of 10, the ringing that occurs when sampling of the pixel 53 with the gradation value of 0 is turned off is large. Therefore, the second display gradation holding period value WTDAT_STP corresponding to the settling period (corresponding to the number of clocks) in which ringing is stable is large. That is, the first display gradation holding period value WTDAT_SLW and the second display gradation holding period value WTDAT_STP satisfy the relationship WTDAT_SLW<WTDAT_STP.”
Therefore, it is respectfully submitted that Uchiyama reasonably teaches “at least two identical pixel values are converted into different pixel values in the selection periods corresponding to each of the display gradations.” and the rejection will be currently maintained.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Uchiyama U.S. Patent Application Publication No. 2020/0327859 A1 hereinafter Uchiyama.
Consider Claim 1:
Uchiyama discloses a signal processing device comprising: (Uchiyama, See Abstract.)
a grayscale histogram generator configured to generate a grayscale histogram indicating the number of pixels for each display gradation in horizontal scanning periods of input video data; (Uchiyama, [0083], “The video data VDS, the horizontal synchronization signal SHD, the clock signal CLK, and a data enable signal DE that is a control input signal are input to the gradation histogram generator 41. The gradation histogram generator 41 generates a display target gradation histogram NDP, which represents the number of display pixels for each display gradation of the video data VDS input during one horizontal scanning period, and outputs the same to the display gradation number acquisition unit 42. Hereinafter, the display target gradation histogram NDP is simply referred to as a gradation histogram NDP.”)
a non-selection period setting unit configured to set a non-selection period corresponding to the display gradations in a stepwise waveform signal, which is an analog signal with a stepwise increase in voltage value in accordance with the display gradations present within the horizontal scanning periods, based on settling time from a start time of each step when the voltage value corresponding to the display gradations increases stepwise until the voltage value of each step falls within an allowable range of a target value; (Uchiyama, [0115], “The gradation histogram value HV is input from the gradation histogram generator 41 to the second display gradation holding period value generator 44. The second display gradation holding period value generator 44 generates the number of each display gradation and the second display gradation holding period value WTDAT_STP corresponding to the time to hold the display gradation determined by the settling period in which the ringing of the ramp waveform signal VREF, which is generated by the number of each display gradation, attenuates to a level that does not affect the displayed image, and outputs the same to the holding period provisional value generator 45.”)
a selection period setting unit configured to set a selection period corresponding to the display gradations following the non-selection period, based on the grayscale histogram, a non-selection sum period obtained by summing up the non-selection periods corresponding to the display gradations in the horizontal scanning periods, and a selection sum period obtained by subtracting the non-selection sum period from the total number of gradations of the video data; (Uchiyama, [0146], “Therefore, (256−(STEP_SUM+1)) in the above relational expression can be expressed as (256−actual display gradation number). The above relational expression relates to a case in which the number of gradations of the video data VDS is 256 (0 to 255 represented by 8 bits8). The gradation number of the video data VDS matches the gradation counter value QD of the liquid crystal device 5. That is, (256−actual display gradation number) is a value obtained by subtracting the display gradation number from the count number 256 of the gradation counter value QD, and is a gradation count number that can be used as a gradation holding period.”)
a display gradation period start time acquisition unit configured to acquire a start time of a display gradation period which is a period obtained by combining the non- selection period and the selection period, for each of the display gradations based on the display gradation period; (Uchiyama, [0134], “The holding period optimum value WTDAT_CMPRS shown in (a) of FIG. 21B is obtained by HM2_PB_RD × [256−(STEP_SUM+1) / WTDAT_SUM. The holding period cumulative optimum value WTDAT_CMPRS_ACC shown in (b) of FIG. 21B is cleared when the enable signal STAGE2_ENA is 0, and otherwise obtained by cumulatively adding the holding period optimum value WTDAT_CMPRS. The holding period cumulative optimum value WTDAT_CMPRS_ACC is a cumulative addition value of the input signal HM5_PA_WD to WD terminal of the A port PA of a memory 480 shown in FIG. 20.”)
a stepwise waveform generation data generator configured to generate stepwise waveform generation data for generating the stepwise waveform signal, based on gradation values of the display gradations and start time of the display gradation period for each of the display gradations; and (Uchiyama, [0058], “The ramp waveform signal generating circuit 3 generates the ramp waveform signal VREF (analog ramp waveform signal) based on the gradation counter clock signal ACLK, and outputs the same to the horizontal scanning circuit 51. The ramp waveform signal VREF is constituted by an analog ramp waveform of a periodic sweep signal that changes in a direction in which the voltage increases from a black display voltage level to a white display voltage level in the pixel 53 in a cycle of one horizontal scanning period.”)
a grayscale-transformed video data generator configured to generate grayscale-transformed video data, which is video data obtained by transforming pixel values of each pixel in the horizontal scanning periods of the video data into pixel values that are dispersed so as to correspond to the selection periods corresponding to the display gradations. (Uchiyama, [0152-0153], [0159], “The display gradation conversion data generator 48 updates the gradation conversion data for the video data VDS in units of one horizontal scanning period, and converts the video data VDS based on the gradation conversion data. However, such operation is performed during a period when the enable signal STAGE2_ENA is at the high level, and the timing when the enable signal STAGE2_ENA changes from the high level to the low level is different from the rising timing of the data enable signal DE. Therefore, in one or more embodiments, updating of the gradation conversion data is performed at the rising timing of the horizontal synchronization signal SHD that becomes the high level during the period when the data enable signal DE is at the low level. This operation will be described below.”)
so that at least two identical pixel values are converted into different pixel values in the selection periods corresponding to each of the display gradations. (Uchiyama, [0192], “the first display gradation holding period value WTDAT_SLW corresponding to the settling period (corresponding to the number of clocks) in which the slew rate is stabilized is small. However, because the number of pixels (1000) with the gradation value of 0 is larger than the number of pixels (10) with the gradation value of 10, the ringing that occurs when sampling of the pixel 53 with the gradation value of 0 is turned off is large. Therefore, the second display gradation holding period value WTDAT_STP corresponding to the settling period (corresponding to the number of clocks) in which ringing is stable is large. That is, the first display gradation holding period value WTDAT_SLW and the second display gradation holding period value WTDAT_STP satisfy the relationship WTDAT_SLW<WTDAT_STP.”)
Consider Claim 2:
Uchiyama discloses the signal processing device according to claim 1, wherein the selection period setting unit is configured to set the selection period corresponding to the display gradations having a time length corresponding to the number of pixels of the display gradations; and (Uchiyama, [0064], “The counter circuit 63 receives the counter clock signal CCLK and the counter reset signal CRST from the timing generating circuit 2. The counter circuit 63 sequentially counts up the n-bit gradation counter value QD based on the counter clock signal CCLK. As a result, the counter circuit 63 outputs 2n gradation counter values QD (0 to (2n−1)) to the comparator circuits 64 (641 to 64x) per horizontal scanning period. Accordingly, the counter circuit 63 outputs to each comparator circuit 64 the gradation counter value QD having the same number of gradations as the gradation data.”)
the stepwise waveform generation data generator is configured to generate stepwise waveform generation data having a time length corresponding to the number of pixels of the display gradations. (Uchiyama, [0058], “The ramp waveform signal generating circuit 3 generates the ramp waveform signal VREF (analog ramp waveform signal) based on the gradation counter clock signal ACLK, and outputs the same to the horizontal scanning circuit 51. The ramp waveform signal VREF is constituted by an analog ramp waveform of a periodic sweep signal that changes in a direction in which the voltage increases from a black display voltage level to a white display voltage level in the pixel 53 in a cycle of one horizontal scanning period.”)
Consider Claim 3:
Uchiyama discloses a display comprising: (Uchiyama, See Abstract.)
a signal processing device according to claim 1; (Uchiyama [0052], See Claim 1.)
a stepwise waveform signal generation circuit configured to generate the stepwise waveform signal by converting the stepwise waveform generation data into an analog signal; and (Uchiyama, [0058], “The ramp waveform signal generating circuit 3 generates the ramp waveform signal VREF (analog ramp waveform signal) based on the gradation counter clock signal ACLK, and outputs the same to the horizontal scanning circuit 51. The ramp waveform signal VREF is constituted by an analog ramp waveform of a periodic sweep signal that changes in a direction in which the voltage increases from a black display voltage level to a white display voltage level in the pixel 53 in a cycle of one horizontal scanning period.”)
a display device having a plurality of pixels and configured to generate a gradation drive voltage for each of the pixels, based on the grayscale-transformed video data and the stepwise waveform signal. (Uchiyama, [0008], “A second aspect of one or more embodiments provides a liquid crystal display device including the above-described signal processing device further including a display gradation converting data generator configured to correct a gradation of the video data for each horizontal scanning period based on the holding period optimum value, and to generate gradation-corrected video data, a ramp waveform signal generating circuit configured to analog convert the ramp waveform signal data to generate the ramp waveform signal; and a liquid crystal device having a plurality of pixels and configured to generate a gradation drive voltage for each of the pixels based on the gradation-corrected video data and the ramp waveform signal.”)
Consider Claim 4:
Uchiyama discloses a signal processing method comprising: (Uchiyama, See Abstract.)
generating a grayscale histogram indicating the number of pixels for each display gradation in horizontal scanning periods of input video data; (Uchiyama, [0083], “The video data VDS, the horizontal synchronization signal SHD, the clock signal CLK, and a data enable signal DE that is a control input signal are input to the gradation histogram generator 41. The gradation histogram generator 41 generates a display target gradation histogram NDP, which represents the number of display pixels for each display gradation of the video data VDS input during one horizontal scanning period, and outputs the same to the display gradation number acquisition unit 42. Hereinafter, the display target gradation histogram NDP is simply referred to as a gradation histogram NDP.”)
setting a non-selection period corresponding to the display gradations in a stepwise waveform signal, which is an analog signal with a stepwise increase in voltage value in accordance with display gradations present within the horizontal scanning periods, based on settling time from a start time of each step when the voltage value corresponding to the display gradations increases stepwise until the voltage value of each step falls within an allowable range of a target value; (Uchiyama, [0115], “The gradation histogram value HV is input from the gradation histogram generator 41 to the second display gradation holding period value generator 44. The second display gradation holding period value generator 44 generates the number of each display gradation and the second display gradation holding period value WTDAT_STP corresponding to the time to hold the display gradation determined by the settling period in which the ringing of the ramp waveform signal VREF, which is generated by the number of each display gradation, attenuates to a level that does not affect the displayed image, and outputs the same to the holding period provisional value generator 45.”)
setting a selection period corresponding to the display gradations following the non-selection period, based on the grayscale histogram, a non-selection sum period obtained by summing up the non-selection periods corresponding to the display gradations in the horizontal scanning periods, and a selection sum period obtained by subtracting the non-selection sum period from the total number of gradations of the video data; (Uchiyama, [0146], “Therefore, (256−(STEP_SUM+1)) in the above relational expression can be expressed as (256−actual display gradation number). The above relational expression relates to a case in which the number of gradations of the video data VDS is 256 (0 to 255 represented by 8 bits8). The gradation number of the video data VDS matches the gradation counter value QD of the liquid crystal device 5. That is, (256−actual display gradation number) is a value obtained by subtracting the display gradation number from the count number 256 of the gradation counter value QD, and is a gradation count number that can be used as a gradation holding period.”)
acquiring a start time of a display gradation period which is a period obtained by combining the non-selection period and the selection period, for each of the display gradations based on the display gradation period; and (Uchiyama, [0134], “The holding period optimum value WTDAT_CMPRS shown in (a) of FIG. 21B is obtained by HM2_PB_RD × [256−(STEP_SUM+1) / WTDAT_SUM. The holding period cumulative optimum value WTDAT_CMPRS_ACC shown in (b) of FIG. 21B is cleared when the enable signal STAGE2_ENA is 0, and otherwise obtained by cumulatively adding the holding period optimum value WTDAT_CMPRS. The holding period cumulative optimum value WTDAT_CMPRS_ACC is a cumulative addition value of the input signal HM5_PA_WD to WD terminal of the A port PA of a memory 480 shown in FIG. 20.”)
generating grayscale-transformed video data, which is video data obtained by transforming pixel values of each pixel in the horizontal scanning periods of the video data into pixel values that are dispersed so as to correspond to the selection periods corresponding to the display gradations, (Uchiyama, [0115], “The gradation histogram value HV is input from the gradation histogram generator 41 to the second display gradation holding period value generator 44. The second display gradation holding period value generator 44 generates the number of each display gradation and the second display gradation holding period value WTDAT_STP corresponding to the time to hold the display gradation determined by the settling period in which the ringing of the ramp waveform signal VREF, which is generated by the number of each display gradation, attenuates to a level that does not affect the displayed image, and outputs the same to the holding period provisional value generator 45.”)
so that at least two identical pixel values are converted into different pixel values in the selection periods corresponding to each of the display gradations. (Uchiyama, [0192], “the first display gradation holding period value WTDAT_SLW corresponding to the settling period (corresponding to the number of clocks) in which the slew rate is stabilized is small. However, because the number of pixels (1000) with the gradation value of 0 is larger than the number of pixels (10) with the gradation value of 10, the ringing that occurs when sampling of the pixel 53 with the gradation value of 0 is turned off is large. Therefore, the second display gradation holding period value WTDAT_STP corresponding to the settling period (corresponding to the number of clocks) in which ringing is stable is large. That is, the first display gradation holding period value WTDAT_SLW and the second display gradation holding period value WTDAT_STP satisfy the relationship WTDAT_SLW<WTDAT_STP.”)
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Prior art made of record and not relied upon which is still considered pertinent to applicant's disclosure is cited in a current or previous PTO-892. The prior art cited in a current or previous PTO-892 reads upon the applicants claims in part, in whole and/or gives a general reference to the knowledge and skill of persons having ordinary skill in the art before the effective filing date of the invention. Applicant, when responding to this Office action, should consider not only the cited references applied in the rejection but also any additional references made of record.
In the response to this office action, the Examiner respectfully requests support be shown for any new or amended claims. More precisely, indicate support for any newly added language or amendments by specifying page, line numbers, and/or figure(s). This will assist The Office in compact prosecution of this application. The Office has cited particular columns, paragraphs, and/or line numbers in the applied rejection of the claims above for the convenience of the applicant. Citations are representative of the teachings in the art and are applied to the specific limitations within each claim, however other passages and figures may apply. Applicant, in preparing a response, should fully consider the cited reference(s) in its entirety and not only the cited portions as other sections of the reference may expand on the teachings of the cited portion(s).
Applicant Representatives are reminded of CFR 1.4(d)(2)(ii) which states “A patent practitioner (§ 1.32(a)(1) ), signing pursuant to §§ 1.33(b)(1) or 1.33(b)(2), must supply his/her registration number either as part of the S-signature, or immediately below or adjacent to the S-signature. The number (#) character may be used only as part of the S-signature when appearing before a practitioner’s registration number; otherwise the number character may not be used in an S-signature.” When an unsigned or improperly signed amendment is received the amendment will be listed in the contents of the application file, but not entered. The examiner will notify applicant of the status of the application, advising him or her to furnish a duplicate amendment properly signed or to ratify the amendment already filed. In an application not under final rejection, applicant should be given a two month time period in which to ratify the previously filed amendment (37 CFR 1.135(c) ).
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/Michael J Jansen II/ Primary Examiner, Art Unit 2626