DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 7, 8, 11, 12, 17, 18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jo (US 20040179005).
Regarding claim 1: Jo teaches a display driving circuit for driving a display device including a pixel receiving a first power supply voltage and a second power supply voltage (Figs. 1-2 and paragraph [0034-0041] teach a display driving circuit for driving a display device 1 including a pixel 2 receiving a first power supply voltage Vdd via L1 and a second power supply voltage Vout via L2), comprising: the pixel comprising: a driving transistor configured to generate a driving current; a data writing transistor configured to provide a data voltage to the driving transistor; and a light emitting element configured to emit light based on the driving current (Figs. 1-2 and paragraph [0034-0045] teach the pixel 2 comprising a driving transistor T4, a data writing transistor T1, and a light emitting element OLED as claimed); and a display controller controlling the first power supply voltage and the second power supply voltage during an emission period of a frame period for the pixel so that the frame period includes sub-emission periods in which the pixel emits light and black insertion periods in which the pixel does not emit the light that alternate with one another (Figs. 1-4 and paragraph [0041-0047] teach a display controller controlling the first power supply voltage Vdd to have a fixed potential and the second supply voltage Vout is controlled to alternate between Voff and Vss (high or low) during a frame period including sub-emission periods from t3-t4 in which pixel emit light during forward bias and black insertion period during reverse biased in which the pixel does not emit the light that alternate with one another based on Sc during the sub-emission period).
Regarding claims 2, 12: Jo teaches wherein the display controller controls the first power supply voltage to have a high level and the second power supply voltage to have a low level, in the sub-emission periods (Figs. 1-4 and paragraph [0041-0047, 0059] teach the first power supply voltage Vdd of L1 to have a fixed potential or a high level and the second power supply voltage Vout of L2 to have a low level in the sub-emission periods. Further, paragraph [0059] disclose the first power supply voltage Vdd of L1 can be set to alternate between high and low, instead of fixed potential).
Regarding claims 7, 17: Jo teaches wherein the display controller controls the first power supply voltage and the second power supply voltage such that the pixel and at least one other pixel operate with simultaneous emission driving (Figs. 1-4 and paragraph [0034-0047] teach to control the first power supply voltage of L1 and the second power supply voltage of L2 such that the plurality of pixels 2 operated simultaneously).
Regarding claims 8, 18: Jo teaches wherein a ratio of the sub-emission period to the frame period is greater than or equal to 10 percent (Figs. 1-4 and paragraph [0034-0047] teach .
Regarding claim 11: Jo teaches a display device (Fig. 1 and paragraph [0034] disclose a display device), comprising: a display panel including a pixel; a gate driver configured to provide a gate signal to the pixel; a data driver configured to provide a data voltage to the pixel; and a power supply voltage generator configured to provide a first power supply voltage and a second power supply voltage (Figs. 1-2 and paragraph [0034-0041, 0059] teach a display panel including a pixel 2, a gate driver 3, a data driver 4, a power supply voltage controller 6, functioning as claimed), wherein an emission period of a frame period for the pixel includes sub-emission periods in which the pixel emits light that alternate with black insertion periods in which the pixel does not emit the light (Figs. 1-4 and paragraph [0041-0047] teach an emission period of a frame period including sub-emission periods from t3-t4 in which pixel emit light during forward bias and black insertion period during reverse biased in which the pixel does not emit the light that alternate with one another based on Sc during the sub-emission period).
Regarding claim 20: Jo teaches an electronic device, comprising the display device of claim 11 (Fig. 1 and paragraph [0034], and see claim 11 rejection).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-6 and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Jo (US 20040179005).
Regarding claims 3, 13: Current embodiment of Jo do not explicitly disclose wherein the display controller controls the first power supply voltage to have a low level and the second power supply voltage to have a high level, in the black insertion periods.
However, in another embodiment Jo discloses wherein the display controller controls the first power supply voltage to have a low level and the second power supply voltage to have a high level, in the black insertion periods (Figs. 8-9 and paragraph [0055-0059] teach controlling the first power supply voltage Vdd of L1 to have a low level and the second power supply voltage Vout of L2 to have a high level in the black insertion periods). It would have been obvious for a person skilled in the art, before the effective date of the invention to modify Jo’s first embodiment by including teachings from another embodiment, because to achieve the black insertion period can be done by modifying either the one of the first or second voltages or by modifying both of the first and second voltages as taught by Jo, both method can achieve similar results. The rationale would have been to use a known method or technique to achieve predictable results.
Regarding claims 4, 14: Jo teaches wherein a high level of the first power supply voltage is higher than the low level of the first power supply voltage, and the high level of the second power supply voltage is higher than a low level of the second power supply voltage (Figs. 8-9 and paragraph [0055-0059]).
Regarding claims 5, 15: Jo teaches wherein the low level of the first power supply voltage is equal to the high level of the second power supply voltage (Figs. 8-9 and paragraph [0055-0059]).
Regarding claims 6, 16: Jo teaches wherein the driving current is generated in the sub-emission periods and not generated in the black insertion periods (Figs. 1-4, 8-9 and paragraph [0041-0047, 0055-0059] teach the driving current is generated in the sub-emission periods during forward bias when light is emitted and not during the black insertion period or reverse biased when light is not emitted).
Claims 9-10, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Jo (US 20040179005) in the view of Park (US 20210125560).
Regarding claims 9, 19: Jo does not explicitly disclose wherein the pixel comprises: the driving transistor including a gate electrode connected to a first node, a first electrode receiving the first power supply voltage, and a second electrode connected to a second node; a compensation transistor including a gate electrode receiving a compensation gate signal, a first electrode connected to the second node, and a second electrode connected to a third node; the data writing transistor including a gate electrode receiving a data write gate signal, a first electrode connected to the third node, and a second electrode connected to the first node; a storage capacitor including a first electrode receiving an initialization voltage and a second electrode connected to the first node; a parasitic capacitor including a first electrode connected to a data line transmitting the data voltage and a second electrode connected to the third node; and the light emitting element including an anode connected to the second node and a cathode receiving the second power supply voltage.
However, Park teaches wherein the pixel comprises: the driving transistor including a gate electrode connected to a first node, a first electrode receiving the first power supply voltage, and a second electrode connected to a second node; a compensation transistor including a gate electrode receiving a compensation gate signal, a first electrode connected to the second node, and a second electrode connected to a third node; the data writing transistor including a gate electrode receiving a data write gate signal, a first electrode connected to the third node, and a second electrode connected to the first node; a storage capacitor including a first electrode receiving an initialization voltage and a second electrode connected to the first node; a parasitic capacitor including a first electrode connected to a data line transmitting the data voltage and a second electrode connected to the third node; and the light emitting element including an anode connected to the second node and a cathode receiving the second power supply voltage (Fig. 2 and paragraph [0078-0098] teach the pixel comprises the driving transistor T1 connected to a first node N1, receiving the first power supply voltage ELVDD, and a second node N3; a compensation transistor T2 receiving a compensation gate signal GC, connected to a second node N3, and a third node N2; the data writing transistor T3 receiving a data write gate signal GW, connected to the third node N2 and the first Node N1; a storage capacitor CST; a parasitic capacitor CPR; and the light emitting element OLED connected as claimed). It would have been obvious for a person skilled in the art, before the effective filing date of the invention to modify Jo’s invention by including above teachings of Park, because a pixel circuit with above disclosed structure is very well-known and widely used in the art in order to drive the pixel optimally and achieve good display quality, as taught by Park. The rationale would have been to use a known method or technique to achieve predictable results.
Regarding claim 10: Combination of Jo and Park teach wherein the driving transistor, the compensation transistor, and the data writing transistor are P-channel metal-oxide-semiconductor (PMOS) transistors (Park in Fig. 2 and paragraph [0078, 0111, 0150]). See claim 9 rejection for combination reasoning of Jo and Park, same rationale applies here.
Conclusion
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/AMIT CHATLY/Primary Examiner, Art Unit 2624