DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The references cited in the IDS have been considered by examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: DISPLAY DEVICE HAVING DIFFERENT ON/OFF VOLTAGE LEVELS FOR CONTROL AND SCAN SIGNALS AND ELECTRONIC APPARATUS THEREOF.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (U.S. Patent Pub. No. 2017/0061928).
Regarding claim 13, Kim discloses a display device (1000), (fig. 1, [0045]), comprising:
a first pixel (PX11) connected to a first scan line (GL1) which transmits a first scan signal (GL1) and a first data line (DL1);
a second pixel (PX12) connected to the first scan line (GL1) and a second data line (DL2);
a third pixel (PX21) connected to a second scan line (GL2) which transmits a second scan signal (GL2) and the first data line (DL1);
a fourth pixel (PX22) connected to the second scan line (GL2) and the second data line (DL2), (figs. 1-2, [0047 and 0079]);
a data driver (300a) including an output buffer (10) which outputs a data signal (DATA1) to an output line (CH1), (fig. 4, [0073-0074]); and
a demultiplexer (200a) including a first transistor (SW1) connected between the first data line (DL1) and the output line (CH1) and turned-on in response to a first control signal (CLA), and a second transistor (SW2) connected between the second data line (DL2) and the output line (CH1) and turned-on in response to a second control signal (CLB), (fig. 2, [0077-0078]), wherein
in a first horizontal period (H1) in which the first scan signal (GL1) has a turn-on voltage level, the second control signal (CLB) has a turn-on voltage level after the first control signal (CLA) has a turn-on voltage level (i.e. CLB is turned on during the second half of period H1 and CLA is turned on during the first half of period H1; see Fig.3d), and
in a second horizontal period (H2) in which the second scan signal (GL2) has a turn-on voltage level, the first control signal (CLA) has the turn-on voltage level after the second control signal (CLB) has the turn-on voltage level (i.e. CLA is turned on during the second half of period H2 and CLB is turned on during the first half of period H2), (fig. 3d, [0088-0089]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7, 11 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Kang (U.S. Patent Pub. No. 2020/0074908).
Regarding claim 1, Kim discloses a display device (1000), (fig. 1, [0045]), comprising:
a first pixel (PX11) connected to a first scan line (GL1) which transmits a first scan signal (GL1) and a first data line (DL1), (figs. 1-2, [0047 and 0079]);
a second pixel (PX12) connected to the first scan line (GL1) and a second data line (DL2), (figs. 1-2, [0047 and 0079]);
a data driver (300a) including an output buffer (10) which outputs a data signal (DATA1) to an output line (CH1), (fig. 4, [0073-0074]); and
a demultiplexer (200a) including a first transistor (SW1) connected between the first data line (DL1) and the output line (CH1) and turned-on in response to a first control signal (CLA), and a second transistor (SW2) connected between the second data line (DL2) and the output line (CH1) and turned-on in response to a second control signal (CLB), (fig. 2, [0077-0078]),
wherein a difference between a turn-on voltage level and a turn-off voltage level of each of the first and second control signals (i.e. difference between high and low levels of selection signals CLA and CLB) is more than a difference between a turn-on voltage level and a turn-off voltage level of the first scan signal (i.e. difference between high and low levels of GL1), (i.e. fig. 3D shows that the high voltage level of selection signals CLA and CLB is greater than the high voltage level of the gate signal GL1), [0051 and 0088].
However, Kim does not mention a difference between a turn-on voltage level and a turn-off voltage level of each of the first and second control signals is less than a difference between a turn-on voltage level and a turn-off voltage level of the first scan signal.
In a similar filed of endeavor, Kang teaches
wherein a difference between a turn-on voltage level and a turn-off voltage level of each of the first and second control signals (i.e. difference between Von and Voff of data selection signals DSS1 and DSS2) is less than a difference between a turn-on voltage level and a turn-off voltage level of the first scan signal (i.e. difference between Von and Voff of scan control signal SCS), (fig. 4, [0129 and 0141]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kim, by specifically providing the difference in voltage levels of the selection signals and the scan signal, as taught by Kang, for the purpose of reducing power consumption, [0010].
Regarding claim 7, Kim discloses further comprising:
a third pixel (PX21) connected to a second scan line (GL2) which transmits a second scan signal (GL2) and the first data line (DL1); and
a fourth pixel (PX22) connected to the second scan line (GL2) and the second data line (DL2), (figs. 1-2, [0047 and 0079]), wherein,
in a first horizontal period (H1) in which the first scan signal (GL1) has the turn-on voltage level, the second control signal (CLB) has the turn-on voltage level after the first control signal (CLA) has the turn-on voltage level (i.e. CLB is turned on during the second half of period H1 and CLA is turned on during the first half of period H1), and
in a second horizontal period (H2) in which the second scan signal (GL2) has a turn-on voltage level, the first control signal (CLA) has the turn-on voltage level after the second control signal (CLB) has the turn-on voltage level (i.e. CLA is turned on during the second half of period H2 and CLB is turned on during the first half of period H2), (fig. 3d, [0088-0089]).
Regarding claim 11, Kim discloses wherein a period (i.e. first half of period H1) in which the first control signal (CLA) has the turn-on voltage level does not overlap a period (i.e. second half of period H1) in which the second control signal (CLB) has the turn-on voltage level, (fig. 3d, [0088-0089]).
Regarding claim 20, Kim discloses an electronic apparatus (3000), (fig. 18, [0180]), comprising:
a display device (1000) which displays an image, (fig. 1, [0045]); and
a processor (3110) which controls the display device (1000), (fig. 18, [0180 and 0182]), wherein
the display device (1000) comprises:
a first pixel (PX11) connected to a first scan line (GL1) which transmits a first scan signal (GL1) and a first data line (DL1), (figs. 1-2, [0047 and 0079]);
a second pixel (PX12) connected to the first scan line (GL1) and a second data line (DL2), (figs. 1-2, [0047 and 0079]);
a data driver (300a) including an output buffer (10) which outputs a data signal (DATA1) to an output line (CH1), (fig. 4, [0073-0074]); and
a demultiplexer (200a) including a first transistor (SW1) connected between the first data line (DL1) and the output line (CH1) and turned-on in response to a first control signal (CLA), and a second transistor (SW2) connected between the second data line (DL2) and the output line (CH1) and turned-on in response to a second control signal (CLB), (fig. 2, [0077-0078]),
a difference between a turn-on voltage level and a turn-off voltage level of each of the first and second control signals (i.e. difference between high and low levels of selection signals CLA and CLB) is more than a difference between a turn-on voltage level and a turn-off voltage level of the first scan signal (i.e. difference between high and low levels of GL1), (i.e. fig. 3D shows that the high voltage level of selection signals CLA and CLB is greater than the high voltage level of the gate signal GL1), [0051 and 0088].
However, Kim does not mention a difference between a turn-on voltage level and a turn-off voltage level of each of the first and second control signals is less than a difference between a turn-on voltage level and a turn-off voltage level of the first scan signal.
In a similar filed of endeavor, Kang teaches
a difference between a turn-on voltage level and a turn-off voltage level of each of the first and second control signals (i.e. difference between Von and Voff of data selection signals DSS1 and DSS2) is less than a difference between a turn-on voltage level and a turn-off voltage level of the first scan signal (i.e. difference between Von and Voff of scan control signal SCS), (fig. 4, [0129 and 0141]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kim, by specifically providing the difference in voltage levels of the selection signals and the scan signal, as taught by Kang, for the purpose of reducing power consumption, [0010].
Claim(s) 4-5 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Kang and in view of Park et al (U.S. Patent Pub No. 2023/0206855).
Regarding claim 4, Kim discloses wherein a frame period (i.e. when all the gate lines GL are scanned) includes an address scan period (H1) in which the data signal (DATA1) is applied to the first and second data lines (i.e. data signals applied to data lines DL1 and DL2 when selection signals CLA and CLB are at a high voltage level during period H1), (figs. 2 and 3d, [0074, 0078, 0084 and 0088]), and
each of the first and second control signals (CLA and CLB) toggles between the turn-on voltage level (high level) and the turn-off voltage level (low level) with a first toggling duration (i.e. during the first half horizontal period 1/2 H, selection signal CLA is high and selection signal CLB is low, thus are toggled) in the address scan period (H1), (fig. 3d, [0078 and 0088]).
However, Kim in view of Kang does not mention a self-scan period.
In a similar field of endeavor, Park teaches a frame period (1F) includes an address scan period (scan period DS) and a self-scan period (self-scan period SS) in which the data signal is not applied to the first and second data lines (i.e. during a self-scan period, data signal is not written), (fig. 6, [0113]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kim in view of Kang, by specifically providing the self-scan period, as taught by Park, for the purpose of reducing power consumption in a low-speed driving mode, [0074].
Regarding claim 5, Kim and Park discloses wherein each of the first and second control signals (selection signals CLA and CLB of Kim) has the turn-off voltage level in the self-scan period (period SS of taught by Park), (i.e. Park teaches that during the self-scan period SS, data signal is not written, then it is obvious that the selection signals CLA and CLB of Kim will be at a low voltage level during the self-scan period SS because the data signal will not be transmitted to the data lines), (see Kim: fig. 2, [0078] and Park: fig. 6, [0113]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kim in view of Kang, by specifically providing the self-scan period, as taught by Park, for the purpose of reducing power consumption in a low-speed driving mode, [0074].
Regarding claim 12, Park discloses wherein each of the first and second pixels (PX) includes:
a driving transistor (T1) including a gate electrode connected to a first node (N1), a first electrode connected to a second node (N2), and a second electrode connected to a third node (N3);
a writing transistor (T2) including a gate electrode which receives a first scan signal (TW), a first electrode which receives the data signal (DATA), and a second electrode connected to the first node (N1);
a reference transistor (T3) including a gate electrode which receives a reference gate signal (GR), a first electrode which receives a reference voltage (VREF), and a second electrode connected to the first node (N1);
an initialization transistor (T4) including a gate electrode which receives an initialization gate signal (GI), a first electrode which receives an initialization voltage (VINT), and a second electrode connected to the third node (N3);
an emission transistor (T5) including a gate electrode which receives an emission signal (EM), a first electrode which receives a first power voltage (ELVDD), and a second electrode connected to the second node (N2);
a storage capacitor (C1) including a first electrode connected to the first node (N1) and a second electrode connected to the third node (N3);
a hold capacitor (C2) including a first electrode which receives the first power voltage (ELVDD) and a second electrode connected to the third node (N3); and
a light-emitting element (OLED) including a first electrode connected to the third node (N3) and a second electrode which receives a second power voltage (ELVSS), (fig. 3, [0084-0095]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kim in view of Kang, by specifically providing the pixel circuit, as taught by Park, for the purpose of reducing power consumption in a low-speed driving mode, [0074].
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Kang in view of Yi et al (U.S. Patent Pub. No. 2020/0082758).
Regarding claim 8, Kim in view of Kang discloses everything as specified above in claim 7. However, Kim in view of Kang does not mention a first width of a period in which the first control signal has the turn-on voltage level is different from a second width of a period in which the second control signal has the turn-on voltage level.
In a similar field of endeavor, Yi teaches wherein, in each of the first and second horizontal periods (first and second 1H), a first width of a period in which the first control signal (i.e. width PW1 of first control signal CS1) has the turn-on voltage level is different from a second width of a period in which the second control signal (i.e. width PW2 of second control signal CS2) has the turn-on voltage level, (fig. 11, [0138]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kim in view of Kang, by specifically providing the different widths of the control signals, as taught by Yi, for the purpose of providing uniform image quality, [0005].
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Kang in view of Yi and in view of Lee et al (U.S. Patent Pub. No. 2014/0146030).
Regarding claim 9, Kim in view of Kang and in view of Yi discloses everything as specified above in claim 8. However, Kim in view of Kang and in view of Yi does not mention wherein the first width is greater than the second width in the first horizontal period.
In a similar field of endeavor, Lee teaches wherein the first width (W1) is greater than the second width (W2) in the first horizontal period (first 1H), (fig. 6, [0066]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kim in view of Kang and in view of Yi, by specifically providing the first width is greater than the second width in the first horizontal period, as taught by Lee for the purpose of improving image quality, [0003].
Regarding claim 10, Yi discloses wherein the second width (PW2) is greater than the first width (PW1) in the second horizontal period (second period 1H), (fig. 11, [0138]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kim in view of Kang, by specifically providing the different widths of the control signals, as taught by Yi, for the purpose of providing uniform image quality, [0005].
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Park.
Regarding claim 14, Kim discloses wherein a frame period (i.e. when all the gate lines GL are scanned) includes an address scan period (H1) in which the data signal (DATA1) is applied to the first and second data lines (i.e. data signals applied to data lines DL1 and DL2 when selection signals CLA and CLB are at a high voltage level during period H1), (figs. 2 and 3d, [0074, 0078, 0084 and 0088]), and
each of the first and second control signals (CLA and CLB) toggles between the turn-on voltage level (high level) and the turn-off voltage level (low level) with a first toggling duration (i.e. during the first half horizontal period 1/2 H, selection signal CLA is high and selection signal CLB is low, thus are toggled) in the address scan period (H1), (fig. 3d, [0078 and 0088]).
However, Kim does not mention a self-scan period.
In a similar field of endeavor, Park teaches a frame period (1F) includes an address scan period (scan period DS) and a self-scan period (self-scan period SS) in which the data signal is not applied to the first and second data lines (i.e. during a self-scan period, data signal is not written), (fig. 6, [0113]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kim, by specifically providing the self-scan period, as taught by Park, for the purpose of reducing power consumption in a low-speed driving mode, [0074].
Regarding claim 15, Kim and Park discloses wherein each of the first and second control signals (selection signals CLA and CLB of Kim) has the turn-off voltage level in the self-scan period (period SS of taught by Park), (i.e. Park teaches that during the self-scan period SS, data signal is not written, then it is obvious that the selection signals CLA and CLB of Kim will be at a low voltage level during the self-scan period SS because the data signal will not be transmitted to the data lines), (see Kim: fig. 2, [0078] and Park: fig. 6, [0113]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kim, by specifically providing the self-scan period, as taught by Park, for the purpose of reducing power consumption in a low-speed driving mode, [0074].
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Yi.
Regarding claim 17, Kim discloses everything as specified above in claim 13. However, Kim does not mention a first width of a period in which the first control signal has the turn-on voltage level is different from a second width of a period in which the second control signal has the turn-on voltage level.
In a similar field of endeavor, Yi teaches wherein, in each of the first and second horizontal periods (first and second 1H), a first width of a period in which the first control signal (i.e. width PW1 of first control signal CS1) has the turn-on voltage level is different from a second width of a period in which the second control signal (i.e. width PW2 of second control signal CS2) has the turn-on voltage level, (fig. 11, [0138]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kim, by specifically providing the different widths of the control signals, as taught by Yi, for the purpose of providing uniform image quality, [0005].
Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Yi and in view of Lee.
Regarding claim 18, Kim in view of Yi discloses everything as specified above in claim 17. However, Kim in view of Yi does not mention wherein the first width is greater than the second width in the first horizontal period.
In a similar field of endeavor, Lee teaches wherein the first width (W1) is greater than the second width (W2) in the first horizontal period (first 1H), (fig. 6, [0066]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kim in view of Yi, by specifically providing the first width is greater than the second width in the first horizontal period, as taught by Lee for the purpose of improving image quality, [0003].
Regarding claim 19, Yi discloses wherein the second width (PW2) is greater than the first width (PW1) in the second horizontal period (second period 1H), (fig. 11, [0138]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kim, by specifically providing the different widths of the control signals, as taught by Yi, for the purpose of providing uniform image quality, [0005].
Allowable Subject Matter
Claims 2-3, 6 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
Claim 2, none of the prior art of record teaches alone or in combination the limitation “wherein the turn-off voltage level of each of the first and second control signals is higher than the turn-off voltage level of the first scan signal.
Claim 3, none of the prior art of record teaches alone or in combination the limitation “wherein the turn-on voltage level of each of the first and second control signals is lower than the turn-on voltage level of the first scan signal.”
Claim 6, none of the prior art of record teaches alone or in combination the limitation “wherein each of the first and second control signals toggles between the turn-on voltage level and the turn-off voltage level with a second toggling duration greater than the first toggling duration in the self-scan period.”
Claim 16 is allowed for similar reason as mentioned above in claim 6.
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/LONG D PHAM/ Primary Examiner, Art Unit 2623