DETAILED ACTION
This action is responsive to the application filed on 3/14/2025. Claims 1-20 are pending and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 4 is objected to because of the following informalities:
In claim 4, line 1 delete the redundant language stating, “further comprising”.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8 and 10-14 of U.S. Patent No. 12,288,062. Although the claims at issue are not identical, they are not patentably distinct from each other because each of the claims of the reference application anticipates each of the claims of the instant application.
Claims 1, 4, 6-8, 11, 13-15, 18 and 20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5-7, 9, 13-17 and 21-23 of U.S. Patent No. 11,321,086 in view of Mansell, PGPUB No. 2020/0218538. Although the claims at issue are not identical, they are not patentably distinct from each other because each of the above claims of the instant application is an obvious variant of a corresponding claim of reference patent 11,321,086.
However, claim 1 of reference patent 086’ does not disclose “…the accumulation data element and the result data element each having a width greater than the first element width and the second element width.”.
Mansell discloses the accumulation data element and the result data element each having a width greater than the first element width and the second element width ([0061]: wherein 32-bit result and accumulation data have greater widths than 8-bit input values (See Figs. 9A-10))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the accumulation and result data of the multiply-accumulate operation of reference patent 086’ to have greater widths than input values as the multiply accumulate operations as taught in Mansell. It would have been obvious because it would have been viewed as a change in size/proportion such that the result and accumulated data would have a greater width than input elements and changes in size/proportion have been deemed obvious by the courts (See In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955)).
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., abstract idea) without significantly more.
Regarding claim 1:
Subject Matter Eligibility Analysis Step 1:
Claim 1 recites “A non-transitory machine-readable medium” and thus an article of manufacture, one of the four statutory categories of patentable subject matter.
Subject Matter Eligibility Analysis Step 2A Prong 1:
Claim 1 recites “…a first source vector having a first bit width and a first element width, and a second source vector having a second bit width that is smaller than the first bit width and a second element width that is smaller than the first element width… perform multiply-accumulate operations… the multiply-accumulate operations including: multiplying a subset of elements of the first source vector by corresponding elements of the second source vector to produce a corresponding subset of products, and accumulating the subset of products with an accumulation data element …to generate a result data element… the accumulation data element and the result data element each having a width greater than the first element width and the second element width” which describe a process that under its broadest reasonable interpretation encompasses mathematical calculations. That is other than reciting generic computing components (e.g. one or more processors and execution circuit) nothing in the claimed elements precludes the steps from practically being performed in the mind and/or with the aid of pen and paper.
For example, the claim discusses performing multiply-accumulate operations (see Figs. 2-4 of applicant’s specification), thus the limitation encompasses mathematical calculations (MPEP 2106.04(a)(2)(I)(C)).
If a claim, limitation, under its broadest reasonable interpretation, covers performance of a mathematical calculation in the mind with the aid of pen and paper but for the recitation of generic computer components then it falls within the “Mathematical concepts” grouping of abstract ideas.
Subject Matter Eligibility Analysis Step 2A Prong 2:
Claim 1 further recites additional elements of
program code stored thereon which, when executed by one or more processors, cause the one or more processors to perform operations comprising: fetching instructions, one or more of the instructions having fields to indicate an opcode, a destination, a first source vector and a second source vector… decoding the one or more instructions; and executing the one or more instructions on a single instruction multiple data (SIMD) execution circuit… within each processing lane of a plurality of processing lanes… corresponding to the processing lane…corresponding to the processing lane
These additional elements do not integrate the abstract idea into a practical application because (a) recites at a high-level of generality the words “apply it” (or an equivalent) with the judicial exception, or use mere instructions to implement the abstract idea on a computer, or merely uses a computer as a tool to perform the abstract idea (See MPEP 2106.05(f)); the use of vector data can also be viewed as an attempt to tie the abstract idea to a particular field of use (e.g. vector/SIMD processing) (MPEP 2106.05(h))). Additionally, the fetching of instructions recites insignificant extra-solution activity (i.e. data retrieving) (See MPEP 2106.05 (g)).
Therefore, claim 1 is directed to the abstract idea.
Subject Matter Eligibility Analysis Step 2B:
The additional elements of claim 1 do not provide significantly more than the abstract idea itself, taken alone and in combination, because (a) uses mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)); the use of vector data can also be viewed as an attempt to tie the abstract idea to a particular field of use (e.g. vector/SIMD processing) (MPEP 2106.05(h))). Furthermore, using computer components such as SIMD execution circuitry can be viewed as well-understood, routine and conventional because it is well-known in computer architecture to process instructions by using SIMD execution circuitry including processing lanes (See NPL reference “Computer Architecture A Quantitative Approach”, pages 292-297). While, “fetching of instructions” is insignificant extra-solution activity of data retrieval (see MPEP 2106.05(g)) which the courts have deemed to be well-understood, routine and conventional activities that do not provide significantly more (MPEP 2106.05(d)); the courts have recognized that receiving or transmitting data over a network ((Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362), as well as storing and retrieving information in memory are well‐understood, routine, and conventional functionalities (Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93)).
Therefore, based on the discussion of the additional elements above, claim 1 is not patent eligible.
Claim 2, dependent upon claim 1, further recites “…wherein the first element width is twice the second element width”, which discloses relative sizes of data elements used in the abstract idea of in claim 1. Thus, the additional limitation ties the abstract idea to a particular type of data, e.g. a particular field of use or technological environment (MPEP 2106.05(h)). Also, the limitation ties the abstract idea to using mere instructions to implement an abstract idea on a computer or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 3, dependent upon claim 1, further recites “…wherein the first bit width is at least 128 bits”, which discloses a size of a vector used in the abstract idea of in claim 1. Thus, the additional limitation ties the abstract idea to a particular type of data, e.g. a particular field of use or technological environment (MPEP 2106.05(h)). Also, the limitation ties the abstract idea to using mere instructions to implement an abstract idea on a computer or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 4, dependent upon claim 1 further recites “…further comprising further comprising program code to cause the operations of: storing a rounding control indication in a control register, the multiply-accumulate operations in each processing lane further including rounding the result data element according to the rounding control indication” which ties the abstract idea of claim 1 to mere instructions used on a computer (e.g. including a control register), using the words “apply it” with the judicial exception or merely uses a computer as a tool to perform an abstract idea (See MPEP 2106.05(f)). The claim also recites an additional abstract idea of rounding. Further, the limitation states “storing a rounding control indication” which can be the insignificant extra-solution activity of data outputting, which is also a well-understood, routine and conventional activity (See MPEP 2106.05(d and g)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 5, dependent upon claim 1 further recites “…wherein if the result data element is larger than a maximum value, the SIMD execution circuit is to saturate the result data element to a predefined value” which ties the abstract idea of claim 1 to mere instructions used on a computer, using the words “apply it” with the judicial exception or merely uses a computer as a tool to perform an abstract idea (See MPEP 2106.05(f)). The claim also recites an additional abstract idea of saturating the result if result data element is larger than a maximum value. Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 6, dependent upon claim 1, further recites “…wherein the first element width and the second element width are to be specified by fields of the opcode”, which ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 7, dependent upon claim 1, further recites “…wherein the second element width is a first width when a portion of the opcode is set to a first value and a second, narrower width when the portion of the opcode is set to a second value”, which ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claims 8 and 15 are similarly rejected on the same basis as claim 1 above.
Claims 9-14 and 16-20 are similarly rejected on the same basis as claims 2-7 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mansell, PGPUB No. 2020/0218538 and further in view of Karthikeyan, PGPUB No. 2014/0195783.
In regard to claim 1, Mansell discloses A non-transitory machine-readable medium having program code stored thereon which, when executed by one or more processors, cause the one or more processors to perform operations ([0005, 0047, 0051 and 0073] and See Fig. 1) comprising: fetching instructions ([0051]) one or more of the instructions having fields to indicate an opcode, a destination, a first source vector having a first bit width and a first element width, and a second source vector having a second bit width and a second element width ([0037-0040, 0061]: wherein instruction has fields indicating opcode, output/accumulator, first source and second source vector. Wherein the first and second sources have first and second bit widths and element widths which may vary (See Figs. 9A-13)) decoding the one or more instructions ([0051 and 0065]) and executing the one or more instructions on a single instruction multiple data (SIMD) execution circuit to perform multiply-accumulate operations within each processing lane of a plurality of processing lanes ([0051 and 0061]: wherein multiply accumulate operations are performed using processing circuitry which includes a plurality of lanes comprising multiplication and addition circuits (see Figs. 10-14)) the multiply-accumulate operations in each processing lane including: multiplying a subset of elements of the first source vector by corresponding elements of the second source vector to produce a corresponding subset of products ([0063-0065]: wherein each processing lane multiplies a subset of elements of a first and second source vector (See Figs. 10-14)) and accumulating the subset of products with an accumulation data element corresponding to the processing lane to generate a result data element corresponding to the processing lane ([0063-0065]: wherein the subset of products are accumulated with an accumulator value corresponding to the processing lane to generate a result corresponding to the processing lane (See Figs. 10-14)) the accumulation data element and the result data element each having a width greater than the first element width and the second element width. ([0033-0034, 0044, 0061]: wherein an accumulation data element and result data element have a width greater than the first and second source vector element widths (See Fig. 11-14))
Mansell does not disclose instructions performing operations using a first source vector having a first bit width and a first element width, and a second source vector having a second bit width that is smaller than the first bit width and a second element width that is smaller than the first element width. Mansell does disclose that register sizes and data element widths for the first and second source vectors may vary (see [0039-0040]). However, Mansell does not disclose the first source vector width and element width being larger than the second source width and element width.
Karthikeyan discloses instructions performing operations using a first source vector having a first bit width and a first element width, and a second source vector having a second bit width and a second element width ([0066-0070, 0072, 0079, 0093]: wherein dot product operations are performed using first and second source vectors of varying bits widths and elements widths (see Figs. 6-10)) a second element width that is smaller than the first element width ([0066-0070, 0072, 0079, 0093](see Figs. 6-10))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the dot product operations performed in Mansell to perform operations on source vectors wherein a second source vector includes a data element width smaller than a first source vector as taught in Karthikeyan. It would have been obvious to one of ordinary skill in the art because it would have been a mere change in size which the courts have deemed obvious (e.g. changing a size of data elements of a second source to be smaller than elements of a first source) (See In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955)). Additionally, the modification can add flexibility to the instruction of Mansell and using a smaller element width can lower power consumption and thus improve processor efficiency. Furthermore, it can be used to provide a more efficient way of calculating a dot product (Karthikeyan [0039 and 0097]).
The combination of Mansell and Karthikeyan does not explicitly disclose a second source vector having a second bit width that is smaller than the first bit width of a first source vector. However, each reference discloses source vector registers having varying register sizes such as 128-bit and 256-bit registers in Mansell (see [0034, 0039-0040 and Fig. 13]); and source vector registers having varying register sizes such as 64-bit, 128-bit, 256-bit, and 512-bit in Karthikeyan [0072 and Fig. 1205]).
Thus, it would have been obvious to one of ordinary skill in the art skill before the effective filing date of the invention to modify the dot product operations performed in Mansell and Karthikeyan to perform operations on source vectors wherein a second source vector includes a width smaller than a first source vector width. It would have been obvious to one of ordinary skill in the art because it would have been a mere change in size which the courts have deemed obvious (e.g. changing a size of second source vector to be smaller in width than a first source vector) (See In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955)). Additionally, the modification can add flexibility to the instruction and using a smaller register size can lower power consumption and thus improve processor efficiency.
Claim 8 is similarly rejected on the same basis as claim 1 above as claim 8 is the method claim corresponding to the medium of claim 1 above.
Claim 15 is similarly rejected on the same basis as claim 1 above as claim 15 is the system corresponding to the medium of claim 1 above. (Note: claim 15 includes additional limitations stating, “A system comprising: a host processor to execute program code; a memory controller to couple the host processor to a memory, the host processor to access the program code from the memory; a graphics processor coupled to the memory controller”. Karthikeyan [0197-0201 and Fig. 21] discloses the above limitations. Using a processor in a system as disclosed above would have been obvious for the benefits of added flexibility and increased processing capabilities by using a graphics co-processor)
In regard to claim 2, the combination of Mansell and Karthikeyan discloses The non-transitory machine-readable medium of claim 1 (see rejection of claim 1 above) wherein the first element width is twice the second element width. (Karthikeyan [0075 and 0079-0080])
Claim 9 is similarly rejected on the same basis as claim 2 above as claim 9 is the method claim corresponding to the medium of claim 2 above.
Claim 16 is similarly rejected on the same basis as claim 2 above as claim 16 is the system corresponding to the medium of claim 2 above.
In regard to claim 3, the combination of Mansell and Karthikeyan discloses The non-transitory machine-readable medium of claim 1 (see rejection of claim 1 above) wherein the first bit width is at least 128 bits. (Mansell [0033-0034, 0061 and 0063] |Karthikeyan [0066, 0069 and 0093])
Claim 10 is similarly rejected on the same basis as claim 3 above as claim 10 is the method claim corresponding to the medium of claim 3 above.
Claim 17 is similarly rejected on the same basis as claim 3 above as claim 17 is the system corresponding to the medium of claim 3 above.
In regard to claim 4, the combination of Mansell and Karthikeyan thus far discloses The non-transitory machine-readable medium of claim 1 (see rejection of claim 1 above). the multiply-accumulate operations in each processing lane (Mansell: See Figs. 9-14|Karthikeyan: See Figs. 6-8)
The combination of Mansell and Karthikeyan thus far does not disclose further comprising program code to cause the operations of storing a rounding control indication in a control register, operations further including rounding the result data element according to the rounding control indication.
Karthikeyan discloses further comprising further comprising program code to cause the operations of storing a rounding control indication in a control register ([0125, 0137 and 0168]) operations further including rounding the result data element according to the rounding control indication. ([0125, 0137 and 0168]: wherein a result of an operation is rounded based on a rounding indicator in a control register when instructions don’t specify a rounding mode)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify a processor that performs multiply-accumulate operations as taught in Mansell to include a control register including a rounding mode to allow a result to be rounded as taught in Karthikeyan. It would have been obvious to one of ordinary skill in the art because rounding a result would control round-off error as to improve accuracy of result, allow data to fit within hardware register constraints and provide added flexibility/control by allowing a variety of rounding mode to be selected in a processor by a programmer.
Claim 11 is similarly rejected on the same basis as claim 4 above as claim 11 is the method claim corresponding to the medium of claim 4 above.
Claim 18 is similarly rejected on the same basis as claim 4 above as claim 18 is the system corresponding to the medium of claim 4 above.
In regard to claim 5, the combination of Mansell and Karthikeyan thus far discloses The non-transitory machine-readable medium of claim 1 (see rejection of claim 1 above).
The combination of Mansell and Karthikeyan thus far does not disclose wherein if the result data element is larger than a maximum value, the SIMD execution circuit is to saturate the result data element to a predefined value.
Karthikeyan discloses wherein if the result data element is larger than a maximum value, the SIMD execution circuit is to saturate the result data element to a predefined value. ([0053, 0063 and 0065])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify a processor that performs multiply-accumulate operations as taught in Mansell to saturate a result as the SIMD execution circuit as taught in Karthikeyan. It would have been obvious to one of ordinary skill in art because saturating results prevents wrap-around/overflow errors.
Claim 12 is similarly rejected on the same basis as claim 5 above as claim 12 is the method claim corresponding to the medium of claim 5 above.
Claim 19 is similarly rejected on the same basis as claim 5 above as claim 19 is the system corresponding to the medium of claim 5 above.
In regard to claim 6, the combination of Mansell and Karthikeyan discloses The non-transitory machine-readable medium of claim 1 (see rejection of claim 1 above) wherein the first element width and the second element width are to be specified by fields of the opcode. (Karthikeyan [0056 and 0077])
Claim 13 is similarly rejected on the same basis as claim 6 above as claim 13 is the method claim corresponding to the medium of claim 6 above.
Claim 20 is similarly rejected on the same basis as claim 6 above as claim 20 is the system corresponding to the medium of claim 6 above.
In regard to claim 7, the combination of Mansell and Karthikeyan discloses The non-transitory machine-readable medium of claim 1 (see rejection of claim 1 above) wherein the second element width is a first width when a portion of the opcode is set to a first value and a second, narrower width when the portion of the opcode is set to a second value. (Karthikeyan [0056 and 0076-0077])
Claim 14 is similarly rejected on the same basis as claim 7 above as claim 14 is the method claim corresponding to the medium of claim 7 above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Mahurin, PGPUB No. 2017/0024209 for teaching mixed width SIMD instructions
Stephens, PGPUB No. 2015/0186142 for teaching mix size scalar data processing instructions
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST.
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/COURTNEY P SPANN/Primary Examiner, Art Unit 2183
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