DETAILED ACTION
This action is responsive to the following communications: the Application filed on March 14, 2025 and the Information Disclosure Statements filed on March 14, 2025 and December 10, 2025.
Claims 1-20 are pending. Claims 1, 13 and 16 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statements (IDSs) filed on March 14, 2025 and December 10, 2025. These IDSs have been considered.
Specification
The disclosure is objected to because of the following informalities:
In paragraph [0117], lines 6-7, “the charge trap layer 483” should be --the charge trap layer 463--.
In paragraph [0121], lines 8-9, “the target NAND strings 802” should be --the target NAND strings 804--.
In paragraph [0125], line 2, “memory structure die 202” should be --memory structure die 201--.
In paragraph [0137], line 4, “control circuit in the storage 1120” should be --control circuit in the storage 1110--.
In paragraph [0145], line 3, “the process 1300 in FIG. 10” should be --the process 1000 in FIG. 10--.
In paragraph [0148], line 2, “With reference to FIG. 11” should be --With reference to FIG. 11A--.
Appropriate correction is required.
Claim Objections
Claims 6, 15 and 19 are objected to because of the following informalities:
In claim 6, lines 6-7, “each or more victim NAND strings” should be --each of the one or more victim NAND strings--.
In claim 15, line 2, “the victim NAND from” should be --the victim NAND string from--.
In claim 19, line 6, “the one or more circuits” should be --the one or more control circuits--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 16, the limitation “the victim NAND strings” lacks proper antecedent basis and is inconsistent with the earlier recitation of “a victim NAND string”. Claims 17-20 are rejected for the same reason because claims 17-20 depend on and incorporate the indefinite limitation of claim 16.
With respect to claim 19, the claim recites “a transistor connected to a first pin of the set of external pins and the bit line, the transistor configured to selectively pass a voltage to the first pin”. The recited location and operation of the transistor are inconsistent. The transistor is recited as connected to both the first pin and the bit line, suggesting that it selectively passes a voltage from the first pin to the bit line. However, the claim subsequently requires the transistor to pass voltage to the first bin, followed by the one or more circuits passing that voltage from the first pin to the bit line. Therefore, it is unclear whether the transistor is upstream of the first pin, between the first bin and bit line, or connected in another arrangement.
With respect to claim 20, the limitation “the one or more victim NAND strings” lacks proper antecedent basis in claim 16, which initially recites only “a victim NAND string”.
Allowable Subject Matter
Claims 1-15 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to independent claim 1, the closest prior art, Hazeghi et al. (US 20210240388), which shows in Figure 1 a memory controller and a temperature sensor that monitor and heat a memory device, including controlling bit lines to activate conductive channel pillars in a memory die [para. 20]. Hazeghi et al. teach a non-planar three-dimensional NAND memory in which vertically stacked memory cells are arranged in strings sharing common channel regions [para. 21] and further teach vertical semiconductor pillars forming the common channels of the memory cell strings, together with associated word lines, bit lines, bit line selectors and a common source line [para. 23]. Hazeghi et al. also disclose placing the memory die in a self-heating mode in which the bit lines provide current through substantially all conductive channels to the common source line, thereby reducing Ohmic heating or Joule's heating in the memory die [para. 24]. In addition, Hazeghi et al. disclose temperature control in which the controller obtains temperature measurement, activates heating when the temperature is below a threshold, continues or adjusts the heat during successive control loops, turns the conductive channel heater off when the threshold is satisfied and calculates different heating strength values based on temperature and rate of temperature change [para. 26-29]. Hazeghi et al. also teach selecting an idle memory die for self-heating mode and using a retired, defective, or rejected die as a heater for surrounding memory dies [para. 30-32]. However, Hazeghi et al. do not teach or suggest creating a current through the NAND channel of one or more victim NAND strings in the memory structure to heat a region of the memory structure having target NAND strings and regulating the current through the NAND channel of each of the one or more victim NAND strings to maintain temperature of the region of the memory structure to a target range of temperatures for a period of time to remove trapped charges from the memory cells on the target NAND strings.
Thus, there is no teaching or suggestion either alone or in combination in the prior art of record to provide the recited a system comprising one or more control circuits configured to create a current through the NAND channel of one or more victim NAND strings in the memory structure to heat a region of the memory structure having target NAND strings; and regulate the current through the NAND channel of each of the one or more victim NAND strings to maintain temperature of the region of the memory structure to a target range of temperatures for a period of time to remove trapped charges from the memory cells on the target NAND strings, in combination with other limitations.
With respect to independent claim 13, similar to the reasons for independent claim 1, there is no teaching or suggestion either alone or in combination in the prior art of record to provide the recited a method for recovering NAND from excessive wear, the method comprising applying a first voltage to a bit line connected to the victim NAND string while applying a second voltage to control gates of memory cells on the victim NAND string to generate a current through the channel of the victim NAND string to heat a region of the memory structure having target NAND strings; and regulating the first voltage to the bit line to maintain temperature of the region to a target range of temperatures for a period of time to recover fail bits due to trapped charges in tunneling layers of the memory cells on the target NAND strings, in combination with other limitations.
Claims 16-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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/DUY H LUONG/Examiner, Art Unit 2825
/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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