DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application filed 03/16/2025. Claims 1-20 are pending in the Application, of which Claims 1, 11 and 12 are independent.
Continuity Priority information
The present Application 19080881 filed 03/16/2025 claims foreign priority to UNITED KINGDOM, Application GB 2404421.6, filed 03/27/2024 and Application GB 2416636.5, filed 11/12/2024.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/31/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS has been considered by the examiner.
Claim Objections
Claims 1-10 are objected to because of the following informalities:
Claims 1, line 3, “coupleable” change to “coupled”, which in this case it indicates connection of two things together. The word “coupleable” isn't in the dictionary. Appropriate correction is required.
Any Claims not specifically mentioned above are objected due to their dependency on an objected claim.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 11 and 12 the limitation “that re-configures the dynamically configurable multi-instrument to function as a different measurement or test instrument for the DUT” renders the claims indefinite. There is no adequate description in the specification of how the multi-instrument is configures to function as a different measurement or test instrument. The specification merely repeats the same claims language.
Regarding Claims 9, 20, the limitation “the dynamically configurable digital logic circuitry, dynamically configurable analogue circuitry, is selected on a time-limited or a capability limited license” is indefinite. There is no adequate description in the specification for the above limitation, i.e. time-limited or a capability limited license.
Any Claims not specifically mentioned above are rejected due to their dependency on an rejected claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by McWilliam et al. (PgPub. US 20030200484) Pub. Date: 2003-10-23.
Regarding independent Claims 1, 11 and 12, McWilliam discloses System And Method For Temporally Isolating Environmentally Sensitive Integrated Circuit Faults, comprising:
a dynamically configurable multi-instrument operably coupled to a user interface; FIG. 1 illustrates an IC test system 100 for isolating environmentally sensitive integrated circuit faults, comprising: a “processor” a processing unit 132; a “user interface” input/output unit 134 and an associated input/output device 136 such as a keyboard and/or a mouse.
an input-output (IO), interface to be connected to a device under test (DUT); [0016] FIG. 1, a Device Under Test (DUT) interface unit 110,
a software configurable switch responsive to a control signal that connects at least one selectable item of test equipment to at least one individual input-output (IO) that re-configures the electronic test equipment system to function as a different measurement or test instrument for a device under test (DUT). [0018] The test execution unit 120 “software configurable switch” may be conventional, and in one embodiment comprises a set of signal assertion, detection, and/or measurement devices, which may include, for example, one or more programmable power supplies and/or a set of Source and Measurement Units (SMUs). The test execution unit 120 may also comprise a switching matrix or signal routing mechanism that facilitates the establishment of selective connections or couplings between elements within the test execution unit 120 and the DUT. One or more elements within the test execution unit 120 may include a memory for storing program instruction sequences and/or data to facilitate test pattern application or integrated circuit testing procedures.
Regarding Claims 2, 13, McWilliam discloses the dynamically configurable multi-instrument comprises digital and analogue test instrumentation equipment. [0018] The test execution unit 120 may be conventional, and in one embodiment comprises a set of signal assertion, detection, and/or measurement devices, which may include, for example, one or more programmable power supplies and/or a set of Source and Measurement Units (SMUs).
Regarding Claims 3, 4, 14, 15, McWilliam discloses a plurality of test equipment items is connected to the DUT via the software configurable switch. [0016] FIG. 1, the IC test system 100 comprises a Device Under Test (DUT) interface unit 110, a test execution unit 120, and a control computer 130. The DUT interface unit 110 is electrically coupled to the test execution unit 120, which is electrically coupled to the control computer 130.
[0017] The DUT interface unit 110 may be conventional, and may comprise essentially any type of apparatus and/or mechanism for interfacing one or more integrated circuits to the text execution unit 120. The DUT interface unit 110 may comprise, for example, a test head and any associated test fixture for exchanging test signals and/or test results with the test execution unit 120; a DUT positioning apparatus or device; and integrated circuit handling and/or transport equipment, in a manner understood by those skilled in the art.
Regarding Claims 5-7, 16-18, McWilliam discloses instrumentation equipment that is configurable via the processor; [0020] The processing unit 132 may comprise a microprocessor for executing stored program instructions. [0021] In one embodiment, an operating system 160 and a test management unit 170 reside within the memory 150. The operating system 160 may comprise program instructions that manage access to system resources, in a manner understood by those skilled in the art. The test management unit 170 may comprise program instructions that direct or oversee the operation of the test execution unit 120 and/or the DUT interface unit 110. Thus, the test management unit 170 may direct the application of test vectors or test patterns to one or more integrated circuits to verify integrated circuit operating characteristics across a range of conditions.
Regarding Claims 8, 19, McWilliam discloses the IO interface comprises IO ports connectable to DUT; [0020] The communication interface 142 may comprise one or more of a serial, a parallel, a Universal Serial Bus (USB), an IEEE 488, an IEEE 1394, an Ethernet, or other interface and associated hardware and software that facilitate signal exchange in accordance with a known protocol. The communication interface 142 may be coupled to the test execution unit 120 and/or the DUT interface unit 110.
Regarding Claims 9, 10, 20, McWilliam discloses configurable analogue circuitry, is selected on a time-limited or a capability limited license; a test engineer to re-configure the electronic test equipment system; [0016] FIG. 1, In one embodiment, the IC test system 100 comprises a Device Under Test (DUT) interface unit 110, a test execution unit 120, and a control computer 130. The DUT interface unit 110 is electrically coupled to the test execution unit 120, which is electrically coupled to the control computer 130. The DUT interface unit 110 may further be coupled to the control computer 130. [0019] an input/output unit 134 and an associated input/output device 136 such as a keyboard and/or a mouse, used by a “test engineer”.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: September 15, 2026
Non-Final Rejection 20260914
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
