DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 03/17/2025 have been accepted by the examiner.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449, filed 03/17/2025, 0108/2025 & 05/21/2026. The information disclosed therein was considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-8 of 19/081528 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8 of U.S. Patent NoUS12277990 issued on 4/15/2025. Although the claims at issue are not identical, they are not patentably distinct from each other because, claims 1-8 of the current application are either anticipated, or would have been obvious over, by the claims 1-8 of U.S. U.S. Patent NoUS12277990 e.g., despite a slight difference in the current application (claim 1 not having a sense amplifier being coupled between the mux transistor and control transistor, it consider to be a design choice). Below is the chart showing the similarities (in bold) and differences between Claims -8, of the present application and claims 1-8 of U.S. Patent NoUS12277990.
19/081528
US12277990
Claim 1,
A memory device, comprising: a first mux transistor and a first control transistor connected to each other at a first node; a first shared gate transistor connecting a first bit line to the first node; a second shared gate transistor connecting a second bit line to the first node; a first memory cell connected to the first bit line; and a second memory cell connected to the second bit line; wherein the first memory cell and the second memory cell are commonly gated by a first word line.
Claim 1,
A memory device, comprising: a first mux transistor and a first control transistor coupled between a sense amplifier and ground, and commonly connected at a first node; a first shared gate transistor connecting a first bit line to the first node; a second shared gate transistor connecting a second bit line to the first node; a first memory cell connected to the first bit line; and a second memory cell connected to the second bit line, wherein the first memory cell and the second memory cell share a first word line transistor gated by a first word line.
Claim 2,
wherein the first shared gate transistor and the second shared gate transistor each have a gate terminal connected to a gate control line.
Claim 2,
wherein the first shared gate transistor and the second shared gate transistor each have a gate terminal connected to a gate control line.
Claim 3,
further comprising a controller, during a read operation of the first memory cell, configured to: activate the first word line; activate the gate control line; and activate a mux control line connected to a gate terminal of the first mux transistor.
Claim 3,
further comprising a controller, during a read operation of the first memory cell, configured to: activate the first word line; activate the gate control line; and activate a mux control line connected to a gate terminal of the first mux transistor.
Claim 4,
wherein the controller, during the read operation of the first memory cell, is further configured to deactivate a control line connected to a gate terminal of the first control transistor.
Claim 4,
wherein the controller, during the read operation of the first memory cell, is further configured to deactivate a control line connected to a gate terminal of the first control transistor.
Claim 5,
further comprising: a third memory cell connected to the first bit line; a fourth memory cell connected to the second bit line, wherein the third memory cell and the fourth memory cell are commonly gated by a second word line.
Claim 5,
further comprising: a third memory cell connected to the first bit line; a fourth memory cell connected to the second bit line, wherein the third memory cell and the fourth memory cell share a second word line transistor gated by a second word line.
Claim 6,
Wherein the controller is configured to, during the read operation of the first memory cell, deactivate the second word line.
Claim 6,
wherein the controller is configured to, during the read operation of the first memory cell, deactivate the second word line.
Claim 7,
wherein the first and second memory cells each comprise a storage unit including a resistor or a capacitor.
Claim 7,
wherein the first and second memory cells each comprise a storage unit including a resistor or a capacitor.
Claim 8,
further comprising: a second mux transistor and a second control transistor connected to each other at a second node; a third shared gate transistor connecting a third bit line to the second node; a fourth shared gate transistor connecting a fourth bit line to the second node; a third memory cell connected to the third bit line; and a fourth memory cell connected to the fourth bit line; wherein the third memory cell and the fourth memory cell are commonly gated by the first word line.
Claim 8,
further comprising: a second mux transistor and a second control transistor coupled between the sense amplifier and ground, and commonly connected at a second node; a third shared gate transistor connecting a third bit line to the second node; a fourth shared gate transistor connecting a fourth bit line to the second node; a third memory cell connected to the third bit line; and a fourth memory cell connected to the fourth bit line, wherein the third memory cell and the fourth memory cell share a second word line transistor gated by the first word line.
Allowable Subject Matter
Claims 9-20 are allowed.
Claim1-8 are objected to because of their dependency to the double patenting rejected claim 1 but would be allowed if the rejected claims are rewritten to overcome the double patenting or a terminal disclaimer is provided to overcome the double patenting.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Morikawa et al (US20040114428): discloses a memory device, comprising: a first mux transistor and a sense amplifier connected to the first mux transistor (FIG 4; 12 connected to first and second 11s, 12 connected to sense amplifier 5 e.g., reading circuit).
a first bit line connected to the first memory cell(FIG 4; LBL2 connected to first memory cell on the left side); a second bit line connected to the second memory cell(LBL1 connected to second memory cell on the right side); a first word line connected to the first and second memory cells(FIG 4; WL1 connected to first and second memory cells; a first control transistor connected to the first bit line(FIG 4; first 11 connected to LBL2); a second control transistor connected to second bit line(FIG 4; second 11 connected to LBL1);
Ueda et al (US20090225586 FIG 1 & 3; discloses memory cells, Mux, transistor and SA connected).
Choy et al (US10224088 FIG 1; discloses Mux connected to sense amplifier and memory cells).
Onuki et al (US20220050373 FIG 4), Carissimi et al (US20210020237 FIG 4), Wu et al (US8233330 FIG 2A) & Naura et al (US20070053233 FIG 1-2).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUNA A TECHANE whose telephone number is (571)272-7856. The examiner can normally be reached 571-272-7856.
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/MUNA A TECHANE/Primary Examiner, Art Unit 2827
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