DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims [1 and 15-20] rejected on the ground of nonstatutory double patenting as being unpatentable over claims [1, 11-13, 14+15 and 16-17] of U.S. Patent No. [12, 232, 332]. Although the claims at issue are not identical, they are not patentably distinct from each other because claims [1 and 15-20] of the current application are an obvious variant and encompassed by claims [1, 11-13, 14+15 and 16-17] of U.S. Patent No. [12, 232, 332].
Below is the table showing the conflicting claims.
US. 19/081,618
US.PAT. No. 12, 232, 332
A semiconductor device, comprising: a plurality of sensors configured to generate a plurality of analog sensing signals;
and a machine learning (ML) processor configured to process the plurality of analog sensing signals using one or more machine learning models, wherein the ML processor comprises: one or more crossbar arrays configured to process the analog sensing signals,
wherein the one or more crossbar arrays are fabricated on a first plurality of interconnect layers on a wafer, and wherein the plurality of sensors is fabricated on a second plurality of interconnect layers on the wafer.
A semiconductor device, comprising: a sensing module configured to generate a plurality of analog sensing signals;
and a machine learning (ML) processor, comprising: one or more crossbar arrays configured to process the analog sensing signals to generate analog preprocessed sensing data;
an analog-to-digital converter (ADC) configured to convert the analog preprocessed sensing data into digital preprocessed sensing data; and a machine learning processing unit configured to process the digital preprocessed sensing data utilizing one or more machine learning models, wherein the sensing module and the ML processor are
fabricated on a single wafer, wherein the sensing module is fabricated on a first portion of the wafer, and wherein the ML processor is fabricated on a second portion of the wafer that surrounds the first portion of the wafer.
15. The semiconductor device of claim 1, further comprising a packaging substrate, wherein the wafer is connected to the packaging substrate.
11. The semiconductor device of claim 1, further comprising a packaging substrate, wherein the wafer is connected to the packaging substrate through an interconnect layer.
16. Zhang as modified further discloses, wherein the ML processor is powered utilizing the analog sensing signals.
12. The semiconductor device of claim 1, wherein the ML processor is powered utilizing the analog sensing signals.
17. The semiconductor device of claim 1, further comprising a transceiver configured to: transmit, to a computing device, a predictive output generated by the ML processor based on the one or more machine learning models; and receive, from the computing device, instructions for performing operations based on the predictive output.
13. The semiconductor device of claim 1, further comprising a transceiver configured to: transmit, to a computing device, a predictive output generated by the machine learning processing unit based on the one or more machine learning models; and receive, from the computing device, instructions for performing operations based on the predictive output.
18. The semiconductor device of claim 1, wherein the one or more crossbar arrays produce analog preprocessed sensing data represents a convolution of the analog sensing signals and a kernel.
14. The semiconductor device of claim 1, wherein the analog preprocessed sensing data represents a convolution of the analog sensing signals and a kernel.
15. The semiconductor device of claim 14, wherein conductance values of a plurality of cross-point devices of the one or more crossbar arrays are programmed to values representing the kernel.
19. The semiconductor device of claim 1, wherein the plurality of sensors comprises a two-dimensional sensor array, wherein a plurality of cross-point devices of the one or more crossbar arrays is configured to receive the analog sensing signals produced by the two-dimensional sensor array as input.
16. The semiconductor device of claim 1, wherein the sensing module comprises a two-dimensional sensor array, wherein a plurality of cross-point devices of the one or more crossbar arrays is configured to receive the analog sensing signals produced by the two-dimensional sensor array as input.
20. The semiconductor device of claim 19, wherein the one or more crossbar arrays comprise a plurality of crossbar arrays positioned on a plurality of different planes.
17. The semiconductor device of claim 16, wherein the one or more crossbar arrays comprises a plurality of crossbar arrays positioned on a plurality of different planes.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) [1, 3, 6-15 and 19-20] is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG (US. 10,970,441) in view of LI(CN-110572593)herein after CN-593.
Reclaim [1], Zhang discloses A semiconductor device (see fig. 2C), comprising: a plurality of sensors configured to generate a plurality of analog sensing signals (see the image sensor as depicted in fig. 2C); and a machine learning (ML) processor configured to process the plurality of analog sensing signals using one or more machine learning models (see the NeUADC as depicted in fig. 2C, [ the NeUADC is equated to the claimed machine learning processor by the virtue of processing a signal using Machine learning algorithm as disclosed in the text of cols. 5-6 lines 65-4), wherein the ML processor comprises: one or more crossbar arrays configured to process the analog sensing signals (see col. 6 lines 10-11 The NeuADC framework also includes a dual-path RRAM crossbar architecture) ,
Zhang does not seem to explicitly discloses, wherein the one or more crossbar arrays are fabricated on a first plurality of interconnect layers on a wafer, and wherein the plurality of sensors is fabricated on a second plurality of interconnect layers on the wafer.
Nonetheless CN-593 discloses an image processing system as Zhang (see for example CN-593 fig. 1 on the attached original document). CN-593 further discloses one or more crossbar arrays are fabricated on a first plurality of interconnect layers on a wafer, and wherein the plurality of sensors is fabricated on a second plurality of interconnect layers on the wafer (see figs 1on the attached original document and, as shown in FIG. 1, and page five, on the attached translation, comprising an upper pixel substrate (Toplayer) and a lower layer processing substrate (bottom layer), wherein the upper pixel substrate comprises a pixel array, the lower processing substrate comprises an artificial intelligence algorithm module, and the upper layer pixel substrate is connected with the lower layer processing substrate [text in the page 5 paragraph 3 on the attached translation]).
Hence it would have been obvious to one of ordinary skill in the art to have been motivated to structurally modify Zhang by the teachings of CN-593 before the effective filling date of the claimed invention since this would allow to improve speed of processing data and enhance energy efficiency of Zhang’s system.
Reclaim [3] , Zhang as modified further discloses wherein the plurality of sensors and the ML processor are fabricated on opposite sides of the wafer (see CN-593 fig. 1,top and page five, on the attached translation, bottom configuration as depicted in fig. 1 of the attached original document, and page five, on the attached translation, comprising an upper pixel substrate (Toplayer) and a lower layer processing substrate (bottom layer)).
Reclaim [6] Zhang as modified further discloses , wherein the semiconductor device further comprises one or more photodiodes, and wherein the second plurality of interconnect layers is fabricated on the one or more photodiodes (see CN-593fig. 1 and . wherein the upper pixel substrate comprises a pixel array, the lower processing substrate comprises an artificial intelligence algorithm module, (on the attached text of translation)).
Reclaim [7] Zhang as modified further discloses , wherein the first plurality of interconnect layers and the second plurality of interconnect layers are positioned at opposite sides of the wafer (see CN-593 fig. 1 on the attached original document and related text on the attached translation) .
Reclaim [8] , Zhamg as modified further discloses wherein the one or more crossbar arrays are configured to generate analog preprocessed sensing data by processing the analog sensing signals, and wherein the ML processor further comprises an analog-to-digital converter (ADC) configured to convert the analog preprocessed sensing data into digital preprocessed sensing data (see Zhang fig. 2C and .col. 38 lines 39-47, ML methods and algorithms are applied to data inputs and generate machine learning (ML) outputs. Data inputs may include but are not limited to: analog and digital signals (e.g. sound, light, motion, natural phenomena, etc.) Data inputs may further include: sensor data, image data, video data, telematics data. ML outputs may include but are not limited to: digital signals (e.g. information data converted from natural phenomena)).
Reclaim [9], Zhang as modified further discloses wherein the ML processor further comprises a machine learning processing unit configured to process the digital preprocessed sensing data using the one or more machine learning models (see Zhang col. 38 lines 41 to 47, Data inputs may include but are not limited to: analog and digital signals (e.g. sound, light, motion, natural phenomena, etc.) Data inputs may further include: sensor data, image data, video data, telematics data. ML outputs may include but are not limited to: digital signals (e.g. information data converted from natural phenomena)).
Reclaim [10] Zhang as modified further discloses, wherein a resistive random-access memory (RRAM) device of the ML processor is fabricated on a metallic pad or a metallic via of the first plurality of interconnect layers (see. Zhang col. 5 lines 56-64, new design is called NeuADC, as it is based on neural network (NN). The systems described herein are founded on a deep learning framework and implemented by using mixed-signal resistive random-access memory (RRAM) cross bar architecture, including RRAM, an NVM technology. In the exemplary embodiment, the RRAM is used as a testbed to facilitate the scaling-compatible and portability-friendly features of this system).
Reclaim [11] Zhang as modified further discloses, wherein the ML processor further comprises at least one transistor, wherein the first plurality of interconnect layers is fabricated on the at least one transistor, and wherein the RRAM device is connected to the at least one transistor through the metallic pad or the metallic via (see Zhang fig. 8 and col. 14 lines 44-48, shows an example ReRAM CROSSBAR™ architecture. Additionally or alternatively, while most previous systems use resistive current-to-voltage (I/V) converter techniques that consume static power, the design system deliberately replaces it with a capacitor and adopts charge pump techniques to save power).
Reclaim [12] Zhang as modified further discloses , wherein the plurality of sensors is fabricated on the ML processor (see CN-593 fig. 1 on the attached original document and page 5 on the attached translation, wherein the upper pixel substrate comprises a pixel array, the lower processing substrate comprises an artificial intelligence algorithm module).
Reclaim [13] Zhang as modified further discloses, further comprising one or more photodiodes fabricated on an interconnect layer of the first plurality of interconnect layers (see CN-593 fig. 1, on the attached original document and page 5 on the attached translation, wherein the upper pixel substrate comprises a pixel array, the lower processing substrate comprises an artificial intelligence algorithm module).
Reclaim [14] Zhang as modified further discloses, wherein the plurality of sensors comprises an array of image sensors, wherein the plurality of analog sensing signals comprises a plurality of analog image signals (see Zhang. Fig. 2c, image sensor as depicted and, col. 38 lines 39-47, ML methods and algorithms are applied to data inputs and generate machine learning (ML) outputs. Data inputs may include but are not limited to: analog and digital signals).
Reclaim [15] Zhang as modified further discloses, further comprising a packaging substrate, wherein the wafer is connected to the packaging substrate (see CN-593 figs. 1, 2 on the attached original document, the entire connected layers of substrate as depicted in fig. 1).
Reclaim [19] Zhang as modified further discloses , wherein the plurality of sensors comprises a two-dimensional sensor array, wherein a plurality of cross-point devices of the one or more crossbar arrays is configured to receive the analog sensing signals produced by the two-dimensional sensor array as input (see Zhang figs. 2C, 8 and col. 38 lines 41 to 47, Data inputs may include but are not limited to: analog and digital signals (e.g. sound, light, motion, natural phenomena, etc.)).
Reclaim [20] Zhang as modified further discloses, wherein the one or more crossbar arrays comprise a plurality of crossbar arrays positioned on a plurality of different planes (see Zhang fig. 8 and col. 14 lines43-44, shows an example ReRAM CROSSBAR™ architecture.).
Allowable Subject Matter
Claims [2 and 3-4] are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AHMED A BERHAN whose telephone number is (571)270-5094. The examiner can normally be reached 9:00Am-5:00pm (MAX- Flex).
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/AHMED A BERHAN/Primary Examiner, Art Unit 2639
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