DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Electronic Display Device Comprising Three Correction Circuits.
Allowable Subject Matter
Claims 3, 6-8, 10-12, 14, and 19-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the closest related art is Hong and Ebisawa. The closest prior art however does not detail the claim 3 limitations stating, The electronic device of claim 2, wherein when the first pixel operates in the first mode, the second correction circuit is turned on, and the third correction circuit is turned off, and
wherein when the first pixel operates in the second mode, the second correction circuit is turned off, and the third correction circuit is turned on.
Regarding claim 6, the closest related art is Hong and Ebisawa. The closest prior art however does not detail the claim 6 limitations stating, The electronic device of claim 5, wherein when the first pixel operates in the second mode and the second pixel operates in the first mode, the first-type light emitting element does not emit light, the second-type light emitting element emits light, the third-type light emitting element emits light, the fourth-type light emitting element does not emit light, the second correction circuit and the third correction circuit are turned on, the second correction circuit is configured to generate the third-type intermediate correction data, and the third correction circuit is configured to generate the second-type intermediate correction data.
Regarding claim 7, the closest related art is Hong and Ebisawa. The closest prior art however does not detail the claim 7 limitations stating, the electronic device of claim 5, wherein when the first pixel and the second pixel operate in the first mode, the first-type light emitting element emits light, the second-type light emitting element does not emit light, the third-type light emitting element emits light, the fourth-type light emitting element does not emit light, the second correction circuit is turned on, the third correction circuit is turned off, and the second correction circuit is configured to generate the first-type intermediate correction data and the third-type intermediate correction data.
Regarding claim 8, the closest related art is Hong and Ebisawa. The closest prior art however does not detail the claim 8 limitations stating, the electronic device of claim 5, wherein when the first pixel and the second pixel operate in the second mode, the first-type light emitting element does not emit light, the second-type light emitting element emits light, the third-type light emitting element does not emit light, the fourth-type light emitting element emits light, the second correction circuit is turned off, the third correction circuit is turned on, and the third correction circuit is configured to generate the second-type intermediate correction data and the fourth-type intermediate correction data.
Regarding claim 10, the closest related art is Hong and Ebisawa. The closest prior art however does not detail the claim 10 limitations stating, The electronic device of claim 9, wherein when the first pixel operates in the second mode and the second pixel operates in the first mode, the first correction data is provided to the second-type light emitting element, and the second correction data is provided to the third- type light emitting element.
Regarding claim 11, the closest related art is Hong and Ebisawa. The closest prior art however does not detail the claim 11 limitations stating, The electronic device of claim 9, wherein when the first pixel and the second pixel operate in the first mode, the first correction data is provided to the first-type light emitting element, and the second correction data is provided to the third-type light emitting element.
Regarding claim 12, the closest related art is Hong and Ebisawa. The closest prior art however does not detail the claim 12 limitations stating, The electronic device of claim 9, wherein when the first pixel and the second pixel operate in the second mode, the first correction data is provided to the second-type light emitting element, and the second correction data is provided to the fourth-type light emitting element.
Regarding claim 14, the closest related art is Hong, Ebisawa, and Tang. The closest prior art however does not detail the claim 14 limitations stating, The electronic device of claim 13, wherein an active period of the first clock signal overlaps an inactive period of the second clock signal, and an active period of the second clock signal overlaps an inactive period of the first clock signal.
Regarding claim 19, the closest related art is Hong and Ebisawa. The closest prior art however does not detail the claim 19 limitations stating, The electronic device of claim 17, wherein when the first pixel and the second pixel are driven in the first mode, the first-type light emitting element emits light, the second- type light emitting element does not emit light, the third-type light emitting element emits light, the fourth-type light emitting element does not emit light, the second correction circuit is turned on, the third correction circuit is turned off, and the second correction circuit is configured to generate the first-type intermediate correction data and the third-type intermediate correction data, and wherein when the first pixel and the second pixel are driven in the second mode, the first-type light emitting element does not emit light, the second-type light emitting element emits light, the third-type light emitting element does not emit light, the fourth-type light emitting element emits light, the second correction circuit is turned off, the third correction circuit is turned on, and the third correction circuit is configured to generate the second-type intermediate correction data and the fourth-type intermediate correction data.
Regarding claim 20, the closest related art is Hong and Ebisawa. The closest prior art however does not detail the claim 20 limitations stating, a first division correction circuit configured to receive a first portion of the intermediate correction data, the first division correction circuit including the second correction circuit and the third correction circuit; and a second division correction circuit configured to receive a second portion of the intermediate correction data, wherein the display panel includes a first division area and a second division area, wherein the first division correction circuit is configured to correct the first portion of the intermediate correction data that is provided to the first division area, and wherein the second division correction circuit is configured to correct the second portion of the intermediate correction data that is provided to the second division area.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 9, and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US 20230217763 A1) in view of Ebisawa et al. (US 20080150842 A1).
Regarding claims 1 and 16, Hong teaches an electronic device (Title, Fig. 1, display device) comprising:
a display panel (Title, Fig. 1, display device) including a first pixel including a first pixel circuit (Figs. 1 and 6 show a plurality of pixels and a pixel circuit thereby teaching a first pixel), a first-type light emitting element electrically connected to the first pixel circuit (Figs. 5-6, [0072], “first and second light emitting diodes D1 and D2”), and a second-type light emitting element electrically connected to the first pixel circuit (Figs. 5-6, [0072], “first and second light emitting diodes D1 and D2”), wherein the first pixel is configured to operate in a first mode or a second mode different from the first mode (Fig. 5, [0068, 0095-0097], teaches first and second modes, wide view and narrow view modes).
Hong is not relied upon for teaching a first, second, and third correction circuit. Ebisawa teaches a display device comprising a first correction circuit configured to receive data and generate intermediate correction data by performing a primary correction on the data (Fig. 4, see inversed gamma correction unit 14 which receives image signal data and generate intermediate correction data as evidenced by its output being fed into a second halation unit 15);
a second correction circuit configured to generate first-type intermediate correction data by correcting first intermediate correction data corresponding to the first-type light emitting element among the intermediate correction data (Fig. 4, see halation correction unit 15); and
a third correction circuit configured to generate second-type intermediate correction data by correcting second intermediate correction data corresponding to the second-type light emitting element among the intermediate correction data (Fig. 4, bit correction unit 16).
It would have been obvious to one skilled in the art, before the effective filing date of the invention, to modify Hong with Ebisawa as this amounts to combining prior art elements according to known methods to yield predictable results. Hong and Ebisawa include each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods, and in combination, each element of Hong and Ebisawa merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable. Further note, Ebisawa [0008] teaches his correction circuits result in an image display having small image unevenness. Therefore, one skilled in the art would have recognized, before the effective filing date of the invention, that modifying Hong’s display to include Ebisawa’s correction circuits would result in an image display having small image unevenness (Ebisawa, [0008]).
For the remaining limitations of claim 16 see the rejections of claims 4 and 5 below.
Regarding claim 2, Hong teaches wherein when the first pixel operates in the first mode, the first-type light emitting element emits light, and the second-type light emitting element does not emit light (Fig. 5, [0092], “when the display panel 150 operates in the wide view mode, the first light emitting diode D1 of each of the red, green and blue subpixels SPr, SPg and SPb has an ON state to emit a light, and the second light emitting diode D2 of each of the red, green and blue subpixels SPr, SPg and SPb has an OFF state not to emit a light.”), and
wherein when the first pixel operates in the second mode, the first-type light emitting element does not emit light, and the second-type light emitting element emits light (Fig. 5, [0094], “When the display panel 150 operates in the narrow view mode, the first light emitting diode D1 of each of the red, green and blue subpixels SPr, SPg and SPb has an OFF state not to emit a light, and the second light emitting diode D2 of each of the red, green and blue subpixels SPr, SPg and SPb has an ON state to emit a light.”).
Regarding claims 4 and 16-17, Hong teaches the electronic device of claim 1, wherein a first area, in which the first pixel is placed, and a second area adjacent to the first area are defined in the display panel (Fig. 1, [0064-0065], “ the display panel 150 includes a plurality of pixels P.” Examiner notes the plurality of pixels P teaches first and second pixels, and, the display panel first pixel defines a first area and a second pixel defines a second area), and
wherein the display panel further includes a second pixel placed in the second area (Fig. 1, 0064-0065], see explanation above), the second pixel including a second pixel circuit (Fig. 6 shows a pixel circuit), a third-type light emitting element electrically connected to the second pixel circuit (Figs. 5-6 show sub-pixels comprising light emitting elements. SPr, for example, is third light emitting element. In fig. 6, D1 can also be considered a third light emitting element. Examiner notes, “third” is interpreted as a label in the same manner as SPr and D1 are labels), and a fourth-type light emitting element electrically connected to the second pixel circuit (Figs. 5-6 show sub-pixels comprising light emitting elements. SPg, for example, is a fourth light emitting element. In fig. 6, D2 can also be considered a fourth light emitting element. Examiner notes, “fourth” is interpreted as a label in the same manner as SPr and D1 are labels),
and the first pixel and the second pixel are configured to be driven in a first mode or in a second mode different from the first mode (Fig. 5, [0068, 0095-0097], teaches first and second modes, wide view and narrow view modes. Fig. 1 teaches first and second pixels).
Regarding claims 5 and 16, Hong is not relied upon for teaching the claim limitations.
Ebisawa teaches the second correction circuit is configured to generate third-type intermediate correction data by correcting third intermediate correction data corresponding to the third-type light emitting element among the intermediate correction data (Fig. 4, halation correction unit 15 generates intermediate correction data which can be labeled third intermediate correction data. The halation correction unit will correct data corresponding to all light emitting elements including a third type light emitting element. Examiner recommends applicant amend this limitation such that the third intermediate correction data is only applied to the third-type light emitting element), and
wherein the third correction circuit is configured to generate fourth-type intermediate correction data by correcting fourth intermediate correction data corresponding to the fourth-type light emitting element among the intermediate correction data (Fig. 4, Bit correction unit 16 is configured to generate intermediate correction data which can be labeled as fourth-type. The bit correction unit will correct data corresponding to all light emitting elements including a fourth-type light emitting element. Examiner recommends applicant amend this limitation such that the fourth intermediate correction data is only applied to the fourth-type light emitting element).
It would have been obvious to one skilled in the art, before the effective filing date of the invention, to modify Hong with Ebisawa as this amounts to combining prior art elements according to known methods to yield predictable results. Hong and Ebisawa include each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods, and in combination, each element of Hong and Ebisawa merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable. Further note, Ebisawa [0008] teaches his correction circuits result in an image display having small image unevenness. Therefore, one skilled in the art would have recognized, before the effective filing date of the invention, that modifying Hong’s display to include Ebisawa’s correction circuits would result in an image display having small image unevenness (Ebisawa, [0008]).
Regarding claim 9, Hong is not relied upon for teaching the claim limitations.
Ebisawa teaches the electronic device of claim 5, further comprising:
a fourth correction circuit configured to receive at least one of the first-type intermediate correction data, the second-type intermediate correction data, the third-type intermediate correction data, and the fourth-type intermediate correction data (Fig. 4, Phosphor saturation correction unit 17 will receive all intermediate correction data from previous correction units),
wherein the fourth correction circuit is configured to generate first correction data by performing a secondary correction on at least one of the first-type intermediate correction data and the second-type intermediate correction data, and the fourth correction circuit is configured to generate second correction data by performing a secondary correction on at least one of the third-type intermediate correction data and the fourth-type intermediate correction data (Fig. 4, phosphor saturation correction unit will perform correction on all data that it receives from the previous correction units thereby meeting these claim limitations).
It would have been obvious to one skilled in the art, before the effective filing date of the invention, to modify Hong with Ebisawa as this amounts to combining prior art elements according to known methods to yield predictable results. Hong and Ebisawa include each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods, and in combination, each element of Hong and Ebisawa merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable. Further note, Ebisawa [0008] teaches his correction circuits result in an image display having small image unevenness. Therefore, one skilled in the art would have recognized, before the effective filing date of the invention, that modifying Hong’s display to include Ebisawa’s correction circuits would result in an image display having small image unevenness (Ebisawa, [0008]).
Regarding claim 15, Hong is not relied upon for teaching the claim limitations.
Ebisawa teaches the electronic device of claim 4, further comprising:
a fourth correction circuit configured to generate third-type intermediate correction data by correcting third intermediate correction data corresponding to the third-type light emitting element among the intermediate correction data (Fig. 4, Phosphor saturation correction unit 17 will receive all intermediate correction data from previous correction units and perform correction on said data).
Ebisawa does not explicitly teach a fifth correction circuit configured to generate fourth-type intermediate correction data by correcting fourth intermediate correction data corresponding to the fourth-type light emitting element among the intermediate correction data, however, a fifth correction circuit as claimed is merely a duplication of parts, In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See MPEP 2144. As Ebisawa details first – fourth correction circuits one skilled in the art would have recognized a fifth correction circuit configured to generate intermediate correction data based on the previous correction unit stages would provide the benefit of an image display having small image unevenness (Ebisawa, [0008]).
Regarding claim 18, Hong teaches when the first pixel is driven in the second mode and the second pixel is driven in the first mode (Fig. 5, [0068, 0095-0097], teaches first and second modes, wide view and narrow view modes which each pixel can be driven in. Fig. teaches a plurality of pixels), the first-type light emitting element does not emit light ([0094], narrow view mode for first pixel results in its first light emitting element D1 being in an off state), the second-type light emitting element emits light ([0094], second light emitting diode D2 is on), the third-type light emitting element emits light ([0092], wide view mode for third light emitter of second pixel which corresponds to D1 which is ON), the fourth-type light emitting element does not emit light ([0092], fourth light emitter of second pixel corresponds to D2 which is off).
Hong is not relied upon for teaching the remaining limitations.
Ebisawa teaches the second correction circuit and the third correction circuit are turned on, the second correction circuit is configured to generate the third-type intermediate correction data, and the third correction circuit is configured to generate the second-type intermediate correction data (Fig. 4, halation correction unit 15 and bit correction unit 16 are turned on when display is operating and are configured to generate intermediate correction data which can be labeled as third-type correction data and second-type correction data).
It would have been obvious to one skilled in the art, before the effective filing date of the invention, to modify Hong with Ebisawa as this amounts to combining prior art elements according to known methods to yield predictable results. Hong and Ebisawa include each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods, and in combination, each element of Hong and Ebisawa merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable. Further note, Ebisawa [0008] teaches his correction circuits result in an image display having small image unevenness. Therefore, one skilled in the art would have recognized, before the effective filing date of the invention, that modifying Hong’s display to include Ebisawa’s correction circuits would result in an image display having small image unevenness (Ebisawa, [0008]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US 20230217763 A1) in view of Ebisawa et al. (US 20080150842 A1), as applied to claim 1 above, and further in view of Tang et al. (US 20140362936 A1).
Regarding claim 13, Hong and Ebisawa are not relied upon for teaching the claim limitations.
Tang teaches a phase locked loop (PLL) configured to output a first clock signal and a second clock signal, wherein the PLL outputs a first clock signal to a first transceiver and a second clock signal to a third transceiver (see claim 9, “first and second phase-locked-loop (PLL) circuits, coupled to the first and second RF transceivers, configured to receive a common clock source signal to respectively generate a first clock signal for use by the first and second RF transceivers, and a second clock signal for use by the third RF transceiver; and the first and second clock signals have different clock frequencies”).
As Ebisawa teaches the second correction circuit and third correction circuit, the combination of Hong, Ebisawa, and Tang will arrive at the claim 13 limitations stating a phase locked loop configured to output a first clock signal and a second clock signal, wherein when the second correction circuit is turned on, the phase locked loop is configured to output the first clock signal to the second correction circuit, and wherein when the third correction circuit is turned on, the phase locked loop is configured to output the second clock signal to the third correction circuit.
It would have been obvious to one skilled in the art, before the effective filing date of the invention, to modify Hong and Ebisawa with Tang as this amounts to combining prior art elements according to known methods to yield predictable results. Hong, Ebisawa, and Tang include each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods, and in combination, each element of Hong, Ebisawa, and Tang merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 11490479 B2, McGrath et al. disclose a tunable LED lighting system with two correction circuits.
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/NATHAN P BRITTINGHAM/Examiner, Art Unit 2629