DETAILED ACTION
Claims 1-20 are presented for examination.
The present application is being examined under the AIA (America Invents Act) First Inventor to File.
This Office Action is Non-Final.
Claims 1, 10 and 19 are independent claims. Claims 2-9, 11-18, 20 are dependent claims.
This action is responsive to the following communication: corresponding claims filed on 03-18-2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03-18-2025 is in compliance with the provisions of 37 CFR 1.97
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 10-17,19-20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2017/0245007 (hereinafter, “Huang”) in view of U.S. Publication No. 2021/0004241 (hereinafter, “Banik”).
As per claim(s) 1, 10, 191, Huang discloses a method comprising:
initializing a system memory during a boot cycle of a computing system having an [display unit] communicatively coupled to a general processing core; (inter alia: ¶ [003] discloses the claimed system memory initialization when the kernel of the operating system needs to be loaded to a system memory from a non-volatile memory using a bootloader when booting a television. Further, Fig. 1 illustrates a television system having a display unit coupled to a processor unit.)
storing display data in a memory buffer of the [display unit]; and (storing image file in the frame buffer 210 of the display unit; Fig. 1, ¶ [0017])
during the initializing of the system memory, retrieving the stored display data from the memory buffer of the [display unit] for presentation on a display device of the computing system. (¶ [0017] discloses the invention where the boot module 322 loads the kernel 310 from the system memory 200. Further, the boot module 322 stores the boot image file 334 to a frame buffer 210 in the system memory 200, so as to display the boot image file 334 through the display unit 500 “till the normal boot process is completed” )
Huang does not distinctly disclose an accelerated processing unit (APU).
However, Banik explicitly discloses an accelerated processing unit (APU). In particular, Banik discloses the following:
initializing a system memory during a boot cycle of a computing system having an accelerated processing unit (APU) communicatively coupled to a general processing core; (¶ [0057] discloses how the static memory (e.g., SRAM) that is available as system memory used during a hardware initialization (e.g., boot) (e.g., hardware initialization code) phase. Fig 1 further illustrated graphics core/boot controller coupled to processor 102 cores)
storing display data in a memory buffer of the APU; and (Banik discloses “early display initialization and visualization” stored in L4 cache that is utilized “graphics circuitry” ; ¶ [0055])
during the initializing of the system memory, retrieving the stored display data from the memory buffer of the APU for presentation on a display device of the computing system. (inter alia: At least ¶s [0059], [0067] disclose parallel processing involving multiple resources (i.e., memories and processing cores) as part of the boot process. Further, Fig’s 3-6 discloses the initialization of both the system memory and L4. For example, ¶ [0033] states “ L4 cache 126 that is initialized as static memory for early display initialization independent of DRAM ….. initialization during the boot process” )
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Huang and Banik because both references are in the same field of endeavor. Banik’s teaching of using multiple resources would enhance Huang's system by further speeding the booting process of the system, thus achieving improvement on boot management.
As per claim 2, Huang as modified discloses a method wherein initializing the system memory comprises generating memory training data for the system memory, (Banik: enable display initialization of DRAM training; ¶s [0048] ) and wherein the method further comprises saving the memory training data. (Banik: enable display initialization and early display bring up independent of DRAM training ¶ [0051] )
As per claims 3, 20,Huang as modified discloses a method further comprising, subsequent to the retrieving of the stored display data from the memory buffer of the APU for presentation, enabling the general processing core to load and initialize a basic input output system (BIOS) of the computing system without initiating an additional boot cycle of the computing system. (Banik: hardware initialization code (such as basic input/output system (BIOS) and/or Unified Extensible Firmware Interface (UEFI)) is improved by configuring a shared (e.g., L4) cache to be available; ¶s [0018], [0027]-[0037] and The improved boot flow of implementations of the disclosure enables utilization of the pre-initialized memory to perform display initialization without being dependent on DRAM resources being trained and initialized by the hardware initialization code. ¶ [0037])
As per claim 4, Huang as modified discloses a method wherein the general processing core is communicatively coupled to a bootloader processor that performs the method. (Banik: processor 102 coupled to boot controller 114 as illustrated by at Fig 1)
As per claim 5, Huang as modified discloses a method wherein retrieving the stored display data from the memory buffer of the APU for presentation on the display device comprises configuring a controller of the display device to retrieve the stored display data from the memory buffer. (Huang: (¶ [0017] discloses the invention where the boot module 322 loads the kernel 310 from the system memory 200. Further, the boot module 322 stores the boot image file 334 to a frame buffer 210 in the system memory 200, so as to display the boot image file 334 through the display unit 500 “till the normal boot process is completed” ) & (Banik: At least ¶s [0059], [0067] disclose parallel processing involving multiple resources (i.e., memories and processing cores) as part of the boot process. Further, Fig’s 3-6 discloses the initialization of both the system memory and L4. For example, ¶ [0033] states “ L4 cache 126 that is initialized as static memory for early display initialization independent of DRAM ….. initialization during the boot process” )
As per claim 6, Huang as modified discloses a method wherein configuring the controller of the display device comprises one or more direct memory access (DMA) or memory-mapped input/output (IO) operations to provide the controller of the display device with a memory address corresponding to the memory buffer of the APU. (Banik: discloses interfaces that are configured to communicably be coupled and facilitate the exchange of information and/or data between various system components including I/O interfaces 820 and I/O interfaces 830. Further these interfaces allow parallel processing involving multiple resources (i.e., memories and processing cores) as part of the boot process. Further, Fig’s 3-6 discloses the initialization of both the system memory and L4. For example, ¶ [0033] states “ L4 cache 126 that is initialized as static memory for early display initialization independent of DRAM ….. initialization during the boot process” ) & (Huang: Fig 1 discloses input/output interface for facilitating the invention where the boot module 322 loads the kernel 310 from the system memory 200. Further, the boot module 322 stores the boot image file 334 to a frame buffer 210 in the system memory 200, so as to display the boot image file 334 through the display unit 500 “till the normal boot process is completed” )
As per claim 7, Huang as modified discloses a method wherein the memory buffer of the APU comprises one or more memory locations within a static random-access memory (SRAM) of the APU. (Banik: SRAM; ¶s [0018], [0024], [0040], [0048])
As per claim 8, Huang as modified discloses a method further comprising updating, during the initializing of the system memory, the display data stored in the memory buffer for presentation on the display device. (Banik: modify a pre-reset initialization flow of the boot process to initialize at least a portion of the shared cache as static memory (e.g., SRAM) available for platform initialization usage (e.g., usage by the BIOS and/or UEFI). Implementations of the disclosure utilize the shared (e.g., L4) cache that is initialized as static memory for early display initialization independent of DRAM training and initialization during the boot process; ¶ [0018])
As per claim 11, Huang as modified discloses a computing system wherein the system memory initialization comprises generating memory training data for the system memory, and wherein the computing system is further configured to save the memory training data for future use after the system memory initialization. (Banik: enable display initialization of DRAM training; ¶s [0048] ) and wherein the method further comprises saving the memory training data. (Banik: enable display initialization and early display bring up independent of DRAM training ¶ [0051] )
As per claim 12, Huang as modified discloses a computing system wherein the memory buffer of the APU comprises one or more memory locations within a static random-access memory (SRAM) of the APU. (Banik: SRAM; ¶s [0018], [0024], [0040], [0048])
As per claims 13, 20, Huang as modified discloses a computing system further comprising, subsequent to the retrieval of the stored display data from the memory buffer for presentation, enabling the general processing core to load and initialize a basic input output system (BIOS) of the computing system without initiating an additional boot cycle of the computing system. (Banik: such as basic input/output system (BIOS) and/or Unified Extensible Firmware Interface (UEFI)) is improved by configuring a shared (e.g., L4) cache to be available; ¶s [0018], [0027]-[0037] and The improved boot flow of implementations of the disclosure enables utilization of the pre-initialized memory to perform display initialization without being dependent on DRAM resources being trained and initialized by the hardware initialization code. ¶ [0037]))
As per claim 14, Huang as modified discloses a computing system further comprising a bootloader processor communicatively coupled to the general processing core, wherein the bootloader processor is configured to initialize the system memory and to enable the general processing core to load and initialize the BIOS. (Banik: entire (e.g., BIOS or UEFI) hardware initialization (e.g., boot) to take place in a multi-threaded (e.g., multiple core) environment.; ¶ [0053])
As per claim 15, Huang as modified discloses a computing system wherein to retrieve the stored display data from the memory buffer of the APU for presentation on the display device comprises configuring a controller of the display device to retrieve the stored display data from the memory buffer. (Huang: (¶ [0017] discloses the invention where the boot module 322 loads the kernel 310 from the system memory 200. Further, the boot module 322 stores the boot image file 334 to a frame buffer 210 in the system memory 200, so as to display the boot image file 334 through the display unit 500 “till the normal boot process is completed” ) & (Banik: At least ¶s [0059], [0067] disclose parallel processing involving multiple resources (i.e., memories and processing cores) as part of the boot process. Further, Fig’s 3-6 discloses the initialization of both the system memory and L4. For example, ¶ [0033] states “ L4 cache 126 that is initialized as static memory for early display initialization independent of DRAM ….. initialization during the boot process” )
As per claim 16, Huang as modified discloses a computing system wherein to configure the controller of the display device comprises providing the controller with a memory address corresponding to the memory buffer of the APU. (Banik: discloses interfaces that are configured to communicably be coupled and facilitate the exchange of information and/or data between various system components including I/O interfaces 820 and I/O interfaces 830. Further these interfaces allow parallel processing involving multiple resources (i.e., memories and processing cores) as part of the boot process. Further, Fig’s 3-6 discloses the initialization of both the system memory and L4. For example, ¶ [0033] states “ L4 cache 126 that is initialized as static memory for early display initialization independent of DRAM ….. initialization during the boot process” ) & (Huang: Fig 1 discloses input/output interface for facilitating the invention where the boot module 322 loads the kernel 310 from the system memory 200. Further, the boot module 322 stores the boot image file 334 to a frame buffer 210 in the system memory 200, so as to display the boot image file 334 through the display unit 500 “till the normal boot process is completed” )
As per claim 17, Huang as modified discloses a computing system wherein the computing system is further configured to update, during the initialization of the system memory, the display data stored in the memory buffer for presentation on the display device. (Banik: modify a pre-reset initialization flow of the boot process to initialize at least a portion of the shared cache as static memory (e.g., SRAM) available for platform initialization usage (e.g., usage by the BIOS and/or UEFI). Implementations of the disclosure utilize the shared (e.g., L4) cache that is initialized as static memory for early display initialization independent of DRAM training and initialization during the boot process; ¶ [0018])
Claim(s) 9 ,18 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2017/0245007 (hereinafter, “Huang”) in view of U.S. Publication No. 2021/0004241 (hereinafter, “Banik”) and further view of U.S. Publication No. 2021/0277599 (hereinafter, “Mikoshiba”).
As per claim 9, Huang as modified does not distinctly disclose a method wherein the display data stored in the memory buffer for presentation on the display device comprises one or more of a group that includes a boot cycle progress indicator, diagnostic information, or status information regarding the computing system.
However, Mikoshiba explicitly discloses a method wherein the display data stored in the memory buffer for presentation on the display device comprises one or more of a group that includes a boot cycle progress indicator, diagnostic information, or status information regarding the computing system. (Fig 4)
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Huang as modified and Mikoshiba because all references are in the same field of endeavor. Mikoshiba’s teaching of displaying a progress bar would enhance Huang's as modified system by visually displaying booting information to the user, thus enhancing booting process to the user.
Conclusion
With respect to any newly added or amended claims, applicant should show support in the original disclosure for the new or amended claims. See MPEP §714.02 and § 2163.06. For example, when responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUREL PRIFTI whose telephone number is (571)270-1743. The examiner can normally be reached on M-F 8 a.m.- 6 p.m..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached on 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AUREL PRIFTI/Primary Examiner, Art Unit 2175
Aurel Prifti
Primary Examiner
Art Unit 2175
Tel. (571) 270-1743
Fax (571) 270-2743
aurel.prifti@uspto.gov
1 As per independent claim(s) 10, 19, these claims are substantially equivalent to method claim 1, because the additional feature(s) are present on any off the shelf general-purpose computer. Therefore, for at least this reason, claims 10 and 19 also stand rejected. Indeed, at least Figure 1 of the cited prior art further discloses the claimed a computer system and boot loader processor
Prosecution Insights