DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/18/2025 is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2, 5, 7-8, 10-12 and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hyeon et al. (US. Pub. No. 2017/0069270, hereinafter “Hyeon”) in view of Huang et al. (US. Pub. No. 2014/0362073, hereinafter “Huang”).
As to claim 1, Hyeon discloses a display device [figure 2, display device 190] comprising:
a display [figure 2, display 240 including a plurality of light emitting devices (LEDs) arranged in a plurality of lines, paragraph 69, the display panel 240 has the plurality of scan lines and data lines which intersect to define a pixel area, and the R-G-B light emitting elements, such as, the LED (or the OLED), are formed in the pixel area] including a plurality of light emitting devices (LEDs) arranged in a plurality of lines;
a scan integrated circuit (IC) [figures 2-3 and paragraph 66, scan driver 220 (which is a circuitry block that includes TFT, TR or MOSFET switching elements, obvious to take on a well-known IC form factor, for packaging and supply availability) to scan the plurality of lines with LEDs] configured to scan the plurality of lines in which the plurality of LEDs are arranged; and
a controller [figure 2, controller 210 to apply to scan driver 220, a control signal] configured to apply, to the scan IC, a control signal.
Hyeon does not disclose a controller configured to apply, to the scan IC, a control signal including a plurality of clock intervals having different frequencies,
wherein, based on the control signal received from the controller, the scan IC non- sequentially scans the plurality of lines.
Huang teaches a display device comprising a controller configured to apply, to a scan IC [figure 5, controller 40 to apply to a gate drive circuit (comprising scan IC) 30, paragraph 46, the term "unit", "module" or "submodule" may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC)], a control signal including a plurality of clock intervals having different frequencies [figures 5 and 20, a control signal CKV(GCK) including a plurality of clock intervals having different frequencies],
wherein, based on the control signal received from the controller, the scan IC non- sequentially scans a plurality of lines [figures 21-22, based on the control signal CKV(GCK) received from the controller, the gate driver scans a plurality of lines non-sequentially GOUT1, GOUT3 (odd line), and GOUT2, GOUT4 (even lines), paragraphs 123-124].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have modified the display device of Hyeon to apply, to the scan IC, a control signal including a plurality of clock intervals having different frequencies, wherein, based on the control signal received from the controller, the scan IC non- sequentially scans the plurality of lines, as taught by Huang, in order to implement interlaced scanning of the display that would save a storage and a periphery auxiliary circuit equipped in a format converter (Huang, paragraph 5).
As to claim 2, Hyeon, as modified by Huang, discloses the display device as claimed in claim 1, wherein
the scan IC is configured to sequentially scan the plurality of lines [Hyeon, figures 4A-B, sequentially scan the plurality of lines],
the controller is configured to:
generate the control signal, in which a first clock interval of the plurality of clock intervals having different frequencies and a second clock interval of the plurality of clock intervals having different frequencies are alternately disposed based on a predetermined scanning order [Huang, figures 20-22, generate CKV, in which a first clock intervals having different frequencies CLK1 and a second clock interval having different frequencies CLK2 are alternately disposed based on a predetermined scanning order], and
apply the generated control signal to the scan IC for the scan IC to non-sequentially scan the plurality of lines [Huang, figures 20-22, apply CKV to gate driver to non-sequentially scan the plurality of lines], and
a frequency of a second clock signal included in the second clock interval is higher than a frequency of a first clock signal included in the first clock interval [Huang, figures 20-22, frequency of CLK2 is higher than a frequency of CLK1]. In addition, the same rationale is used as in rejection for claim 1.
As to claim 5, Hyeon, as modified by Huang, discloses the display device as claimed in claim 2, wherein
the controller includes:
a register storing information on the predetermined scanning order [Huang, paragraph 50, a data storage control unit 110, a data storage unit 120, If the video data signal format is in the interlaced format, the interlaced and progressive format determination unit 130 outputs a first control signal to the data storage control unit 110, and the data storage control unit 110 controls the video data signal to be buffered in the data storage unit 120. Then, video data signals in two consecutive fields of a frame of image are simultaneously output to the interlaced-to-progressive data unit 140 for combined processing],
a counter circuit configured to output a sequence signal corresponding to the information stored in the register [Huang, paragraph 50, If the video data signal format is in the interlaced format, the interlaced and progressive format determination unit 130 outputs a first control signal to the data storage control unit 110, and the data storage control unit 110 controls the video data signal to be buffered in the data storage unit 120. Then, video data signals in two consecutive fields of a frame of image are simultaneously output to the interlaced-to-progressive data unit 140 for combined processing], and
a variable clock generation circuit configured to selectively output the first clock signal and the second clock signal based on the sequence signal [Huang, figures 5 and 10, part of timing controller to selectively output first clock signal CLK1 and second clock signal CLK2 based on the sequence signal]. In addition, the same rationale is used as in rejection for claim 1.
As to claim 7, Hyeon, as modified by Huang, discloses the display device as claimed in claim 2, wherein
the controller is configured to apply, to the scan IC, the control signal for sequentially scanning odd lines among the plurality of lines [Huang, figure 21, sequentially scanning odd lines among the plurality of lines] and then sequentially scanning even lines among the plurality of lines [Huang, figure 22, sequentially scanning even lines among the plurality of lines], and
the control signal sequentially disposes the first clock interval corresponding to a line to be scanned among the plurality of lines [Huang, figure 20, sequentially disposes the first clock interval CLK1 corresponding to a line to be scanned among the plurality of lines] and the second clock interval corresponding to a line not to be scanned among the plurality of lines [Huang, figure 20, CLK2 corresponding to a line not to be scanned among the plurality of lines]. In addition, the same rationale is used as in rejection for claim 1.
As to claim 8, Hyeon, as modified by Huang, discloses the display device as claimed in claim 2, wherein
the controller is configured to apply, to the scan IC, the control signal for sequentially scanning the plurality of lines by hopping a predetermined number of lines among the plurality of lines [Huang, figure 21, sequentially scanning the plurality of lines by hopping GOUT2, GOUT4], and then sequentially scanning remaining lines among the plurality of lines by hopping the predetermined number of lines [Huang, figure 22, sequentially scanning remaining lines GOUT2, GOUT4 by hopping GOUT1, GOUT3],
the control signal sequentially disposes the first clock interval corresponding to a line to be scanned among the plurality of lines [Huang, figure 20, sequentially disposes the first clock interval CLK1 corresponding to a line to be scanned among the plurality of lines] and the second clock interval corresponding to a line not to be scanned among the plurality of lines [Huang, figure 20, CLK2 corresponding to a line not to be scanned among the plurality of lines], and
the predetermined number is two [Huang, predetermined number is two], three, or four. In addition, the same rationale is used as in rejection for claim 1.
As to claim 10, Hyeon, as modified by Huang, discloses the display device as claimed in claim 2, wherein
a scanning operation period for all of the plurality of lines includes a first scanning operation period for some lines among the plurality of lines and at least one second scanning operation period for some other lines among the plurality of lines [Huang, figures 21-22, a first scanning operation period for some lines and at least one second scanning operation period for some other lines], and
the controller is configured to adjust the scanning order differently for each of the first scanning operation period and the second scanning operation period [Huang, figures 21-22, adjust the scanning order (odd line, even line) differently for each of first scanning operation period and second scanning operation period]. In addition, the same rationale is used as in rejection for claim 1.
As to claim 11, Hyeon discloses a scanning method of a display device [abstract], which includes a plurality of light emitting devices (LEDs) arranged in a plurality of lines [figure 2, display 240 including a plurality of light emitting devices (LEDs) arranged in a plurality of lines, paragraph 69, the display panel 240 has the plurality of scan lines and data lines which intersect to define a pixel area, and the R-G-B light emitting elements, such as, the LED (or the OLED), are formed in the pixel area], and a scan integrated circuit (IC) [figure 2, scan driver 220 to scan the plurality of lines with LEDs] configured to scan the plurality of lines in which the plurality LEDs are arranged.
Hyeon does not disclose applying, to the scan IC, a control signal including a plurality of clock intervals having different frequencies; and
based on the applied control signal, non-sequentially scanning, by the scan IC, the plurality of lines.
Huang teaches applying, to a scan IC [figure 5, controller 40 to apply to a gate drive circuit (comprising scan IC) 30], a control signal including a plurality of clock intervals having different frequencies [figures 5 and 20, a control signal CKV(GCK) including a plurality of clock intervals having different frequencies]; and
based on the applied control signal, non-sequentially scanning, by the scan IC, the plurality of lines [figures 21-22, based on the control signal CKV(GCK) received from the controller, the gate driver scans a plurality of lines non-sequentially GOUT1, GOUT3 (odd line), and GOUT2, GOUT4 (even lines)].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have modified the display device of Hyeon to apply, to the scan IC, a control signal including a plurality of clock intervals having different frequencies, wherein, based on the control signal received from the controller, the scan IC non- sequentially scans the plurality of lines, as taught by Huang, in order to save a storage and a periphery auxiliary circuit equipped in a format converter (Huang, paragraph 5).
As to claim 12, Hyeon, as modified by Huang, discloses the method as claimed in claim 11, wherein
the scan IC is configured to sequentially scan the plurality of lines [Hyeon, figures 4A-B, sequentially scan the plurality of lines],
the applying of the control signal to the scan IC includes generating the control signal, in which a first clock interval of the plurality of clock intervals having different frequencies and a second clock interval of the plurality of clock intervals having different frequencies are alternately disposed based on a predetermined scanning order [Huang, figures 20-22, generate CKV, in which a first clock intervals having different frequencies CLK1 and a second clock interval having different frequencies CLK2 are alternately disposed based on a predetermined scanning order, figures 20-22, apply CKV to gate driver to non-sequentially scan the plurality of lines], and
a frequency of a second clock signal included in the second clock interval is higher than a frequency of a first clock signal included in the first clock interval [Huang, figures 20-22, frequency of CLK2 is higher than a frequency of CLK1]. In addition, the same rationale is used as in rejection for claim 11.
As to claim 14, Hyeon, as modified by Huang, discloses the method as claimed in claim 12, wherein
the generating of the control signal includes:
generating the first clock signal and the second clock signal, respectively [Huang, figure 20, generating first clock signal CLK1 and second clock signal CLK2], and
generating the control signal by multiplexing the first clock signal with the second clock signal based on scanning order information stored in a register [Huang, figure 20, multiplexing CLK1 and CLK2 based on scanning order, paragraph 50, a data storage control unit 110, a data storage unit 120, If the video data signal format is in the interlaced format, the interlaced and progressive format determination unit 130 outputs a first control signal to the data storage control unit 110, and the data storage control unit 110 controls the video data signal to be buffered in the data storage unit 120. Then, video data signals in two consecutive fields of a frame of image are simultaneously output to the interlaced-to-progressive data unit 140 for combined processing]. In addition, the same rationale is used as in rejection for claim 11.
As to claim 15, Hyeon, as modified by Huang, discloses the method as claimed in claim 12, wherein
the generating of the control signal includes generating the first clock signal and the second clock signal by controlling a variable clock generation circuit based on scanning order information stored in a register [Huang, figures 5 and 10, part of timing controller to selectively output first clock signal CLK1 and second clock signal CLK2 based on the sequence signal, paragraph 50, If the video data signal format is in the interlaced format, the interlaced and progressive format determination unit 130 outputs a first control signal to the data storage control unit 110, and the data storage control unit 110 controls the video data signal to be buffered in the data storage unit 120. Then, video data signals in two consecutive fields of a frame of image are simultaneously output to the interlaced-to-progressive data unit 140 for combined processing]. In addition, the same rationale is used as in rejection for claim 11.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hyeon in view of Huang, as applied to claims 1-2 above, further in view of Yoshikawa et al. (US. Pub. No. 2013/0145341, hereinafter “Yoshikawa”).
As to claim 4, Hyeon, as modified by Huang, discloses the display device as claimed in claim 2, wherein
the controller includes:
a first clock generation circuit configured to generate the first clock signal [Huang, figure 20, first clock signal CLK1, paragraph 61, the GCK signal including two clock pulses, which includes a first clock pulse and a second clock pulse],
a second clock generation circuit configured to generate the second clock signal [Huang, figure 20, second clock signal CLK2, paragraph 61, the GCK signal including two clock pulses, which includes a first clock pulse and a second clock pulse].
Hyeon, as modified by Huang, does not disclose a register storing information on the predetermined scanning order,
a multiplexer (MUX) circuit,
a counter circuit, and
the counter circuit is configured to transmit a sequence signal corresponding to the information stored in the register to the MUX circuit, and
the MUX circuit is configured to generate the control signal by multiplexing the first clock signal with the second clock signal based on the sequence signal.
Yoshikawa teaches a register storing information on a predetermined scanning order [figure 2, a register storing information on a predetermined scanning order, paragraph 54, The multiplexer 303 selects one of the counter circuits 301a to 303a, which are included in one group, in sequence, and writes the counted value written in the register of the counter circuit 301a to 301c into the RAM 304],
a multiplexer (MUX) circuit [figure 2, MUX],
a counter circuit [figure 2, counter circuit], and
the counter circuit is configured to transmit a sequence signal corresponding to the information stored in the register to the MUX circuit [paragraph 54, The multiplexer 303 selects one of the counter circuits 301a to 303a, which are included in one group, in sequence, and writes the counted value written in the register of the counter circuit 301a to 301c into the RAM 304], and
the MUX circuit is configured to generate the control signal by multiplexing the first clock signal with the second clock signal based on the sequence signal [paragraph 54, The multiplexer 303 selects one of the counter circuits 301a to 301c, which are included in one group, in sequence, and writes the counted value written in the register of the counter circuits 301a to 301c into the RAM 304. Such a processing is repeated].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have modified the display device of Hyeon to comprise a register storing information on the predetermined scanning order, a multiplexer (MUX) circuit, a counter circuit, and the counter circuit is configured to transmit a sequence signal corresponding to the information stored in the register to the MUX circuit, and the MUX circuit is configured to generate the control signal by multiplexing the first clock signal with the second clock signal based on the sequence signal, as taught by Yoshikawa, in order to be possible to read out data at very high speed (Yoshikawa, paragraph 55).
Allowable Subject Matter
Claims 3, 6, 9 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: None of the prior art, made of record, singularly or in combination, teaches or fairly suggests the features presented in the combination limitations of dependent claims 3, 6, 9 and 13, such as “the first clock signal is repeated in the first clock interval a predetermined number of times, and the second clock signal is repeated in the second clock interval the predetermined number of times, the scan IC is configured to: if the first clock signal is received, apply a first scan signal to one line among the plurality of lines based on the first clock signal while the first clock signal is repeated consecutively the predetermined number of times, and if the second clock signal is received after the received first clock signal is repeated consecutively the predetermined number of times, apply a second scan signal to a next line among the plurality of lines based on the second clock signal while the second clock signal is repeated consecutively the predetermined number of times, a time during which the first scan signal is applied is greater than or equal to a threshold time for turning on LEDs among the plurality of LEDs included in each respective line among the plurality of lines, and a time during which the second scan signal is applied is less than the threshold time”, recited by claim 3; “the information on the predetermined scanning order stored in the register is one of sequential operation information for sequentially scanning the plurality of lines or non- sequential operation information for performing the non-sequential operation on the plurality of lines in a predetermined number of lines among the plurality of lines, and the scanning order information is updatable”, recited by claim 6; “a scanning operation period for all of the plurality of lines includes a first scanning operation period for some lines among the plurality of lines and at least one second scanning operation period for some other lines among the plurality of lines, the controller is configured to apply, to the scan IC, the control signal for scanning the plurality of lines by hopping at least one line among the plurality of lines during the first scanning operation period, and then scanning remaining lines among the plurality of lines by hopping at least one line among the plurality of lines during the at least one second scanning operation period, and the control signal sequentially disposes the first clock interval corresponding to a line to be scanned among the plurality of lines and the second clock interval corresponding to a line not to be scanned among the plurality of lines”, recited by claim 9; and “the first clock signal is repeated in the first clock interval a predetermined number of times, and the second clock signal is repeated in the second clock interval the predetermined number of times, the non-sequential scanning includes: if the first clock signal is received, applying a first scan signal to one line among the plurality of lines based on the first clock signal while first clock signal is repeated consecutively the predetermined number of times, and if the second clock signal is received after the received first clock signal is repeated consecutively the predetermined number of times, applying a second scan signal to a next line among the plurality of lines based on the second clock signal while the second clock signal is repeated consecutively the predetermined number of times, a time during which the first scan signal is applied is greater than or equal to a threshold time for turning on LEDs among the plurality of LEDs included in each respective line among the plurality of lines, and a time during which the second scan signal is applied is less than the threshold time”, recited by claim 13.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US. Pub. No. 2018/0114566 (Aoyama et al.) is considered as pertinent art as seen in figure 1.
US. Pub. No. 2015/0332624 (Zhang et al.) is also considered as pertinent art as seen in figure 6.
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/NAN-YING YANG/Primary Examiner, Art Unit 2629