DETAILED ACTION
This FINAL action is in response to Application No. 19/083,086 originally filed 03/18/2025. The amendment presented on 04/09/2026 which provides no amendments to the claims is hereby acknowledged. This application is subject to the restriction set forth on 10/23/2025 in which Applicant elected Species I in the response 12/23/2025 in which Claims 5, 7-10, 15, and 17-20 were withdrawn. Claims 1-4, 6, 11-14, and 16 have been noted as being readable on the elected species.
Therefore, claims 1-4, 6, 11-14, and 16 are readable on the elected species and currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The office thanks the applicant for the corrected drawings received on 04/09/2026. These drawings are in compliance. This objection is hereby withdrawn.
Response to Arguments
Applicant's arguments filed 04/09/2026 have been fully considered but they are not persuasive.
The Office notes after review that the claims were noted as being rejected in view of Figure 6 and Figure 7 and not solely Figure 7. A marked-up version of Figure 6 has been provided below for convenience. The Office notes that the equated “first transistor” (i.e. Dr ) is in fact initialized at both the gate, first electrode, and second electrode. As seen in the figure, a prior gate signal “n-1” is used to turn on transistor T4 which allows the initialization signal to be supplied to both Dr and T3. The transistor T3 is also turned with signal SC2 thereby allowing the initialization signal to be applied to both the first and second electrode and gate of the driving transistor Dr. Applicants claimed second and third periods appear to happen in the reference of Kim with respect to Figure 7. Applicants claims do not expressly provide which signal is provided to the gate of the first transistor as Figure 7 describes in addition, a Vbias signal is applied, which, can be considered a type of initialization signal. The overlapping signal periods of Applicants claimed “second” and “third period” are equated to one in the same of Kim and appear to perform the function as claimed. Applicants’ claims are still broad enough to read on the prior art as they lack additional details of signal times, specific signals being applied to specific portions of the circuit etc. (Applicants marked up Figure 7 below) Therefore, upon review, it is respectfully submitted the claims are still broad enough to read on the prior art of record and will be currently maintained.
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Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. U.S. Patent Application Publication No. 2023/0178023 A1 hereinafter Kim.
Consider Claim 1:
Kim discloses a display device comprising: (Kim, See Abstract.)
a display panel in which a plurality of pixels are arranged in a display area to display an image; and (Kim, [0058], “The display panel 100 may include a plurality of pixels arranged in a matrix form. The respective pixels may include a plurality of sub pixels. For example, the display panel 100 may include the plurality of pixels (3840×2160 pixels) arranged in the matrix form, and the respective pixels may include three types of sub pixels such as a red (R) sub pixel, a green (G) sub pixel, and a blue (B) sub pixel.”)
a gate driver configured to supply gate scan signals to the pixels on a horizontal line-by-horizontal line basis, (Kim, [0077-0079], “[0077] The gate driver may include various circuitry and generate various control signals such as a control signal(SPWM(n)), a control signal(SPAM), and the like, and configured to transfer the generated various control signals to a specific row (or, a specific horizontal line), or to all the lines of the display panel 100.”)
wherein from among the pixels, pixels that are on a same horizontal line along each gate line are configured to initialize a gate electrode, a first electrode, and a second electrode of a first transistor to an emission initialization voltage in response to a previous gate initialization signal supplied to pixels of a previous horizontal line and a current compensation gate signal from among the gate scan signals in a first period, (Kim, [0099], [0104], “The third transistor T3 may be turned-on based on the second scan signal (SC2(n)) being changed to a high voltage during a third time period ({circle around (3)}) directly after the second time period ({circle around (2)}), and the first initialization signal (Vini) may be applied to the gate terminal of the first transistor (Dr. TFT) according to the third transistor T3 being turned-on. The first initialization signal (Vini) may be voltage which may turn-on the first transistor (Dr. TFT). Further, a high voltage applying time of the second scan signal (SC2(n)) may be controllable.” See Fig. 6.)
to initialize the second electrode of the first transistor to an initialization voltage in response to a current gate initialization signal and the current compensation gate signal from among the gate scan signals in a second period, and to detect and compensate for a threshold voltage of the first transistor in response to the current compensation gate signal and a current write gate signal from among the gate scan signals in a third period. (Kim, [0099], [0106], “The second transistor T2 and the seventh transistor T7 may be turned-on based on the first scan signal (SC1(n)) being changed to a high voltage during a fourth time period ({circle around (4)}) directly after the third time period ({circle around (3)}), the fourth transistor T4 may be turned-off based on the third scan signal (SC2(n-1)) being changed to a low voltage during the fourth time period ({circle around (4)}), the data signal may be a first data value, and may be applied to the gate terminal, the drain terminal and the source terminal of the first transistor (Dr. TFT) according to the second transistor T2 being turned-on, and the second initialization signal (VCR) may be a pre-set second initialization value (VCR(A)), and may be applied to the cathode of the light-emitting device according to the seventh transistor T7 being turned-on.” See Fig. 7.)
Consider Claim 11:
Kim discloses an electronic device comprising a display device configured to display an image, wherein the display device comprises: (Kim, See Abstract.)
a display panel in which a plurality of pixels are arranged in a display area to display an image; and (Kim, [0058], “The display panel 100 may include a plurality of pixels arranged in a matrix form. The respective pixels may include a plurality of sub pixels. For example, the display panel 100 may include the plurality of pixels (3840×2160 pixels) arranged in the matrix form, and the respective pixels may include three types of sub pixels such as a red (R) sub pixel, a green (G) sub pixel, and a blue (B) sub pixel.”)
a gate driver configured to supply gate scan signals to the pixels on a horizontal line-by-horizontal line basis, (Kim, [0077-0079], “[0077] The gate driver may include various circuitry and generate various control signals such as a control signal(SPWM(n)), a control signal(SPAM), and the like, and configured to transfer the generated various control signals to a specific row (or, a specific horizontal line), or to all the lines of the display panel 100.”)
wherein from among the pixels, pixels that are on a same horizontal line along each gate line are configured to initialize a gate electrode, a first electrode and a second electrode of a first transistor to an emission initialization voltage in response to a previous gate initialization signal supplied to pixels of a previous horizontal line and a current compensation gate signal from among the gate scan signals in a first period, (Kim, [0099], [0104], “The third transistor T3 may be turned-on based on the second scan signal (SC2(n)) being changed to a high voltage during a third time period ({circle around (3)}) directly after the second time period ({circle around (2)}), and the first initialization signal (Vini) may be applied to the gate terminal of the first transistor (Dr. TFT) according to the third transistor T3 being turned-on. The first initialization signal (Vini) may be voltage which may turn-on the first transistor (Dr. TFT). Further, a high voltage applying time of the second scan signal (SC2(n)) may be controllable.” See Fig. 6.)
to initialize the second electrode of the first transistor to an initialization voltage in response to a current gate initialization signal and the current compensation gate signal from among the gate scan signals in a second period, and to detect and compensate for a threshold voltage of the first transistor in response to the current compensation gate signal and a current write gate signal from among the gate scan signals in a third period. (Kim, [0099], [0106], “The second transistor T2 and the seventh transistor T7 may be turned-on based on the first scan signal (SC1(n)) being changed to a high voltage during a fourth time period ({circle around (4)}) directly after the third time period ({circle around (3)}), the fourth transistor T4 may be turned-off based on the third scan signal (SC2(n-1)) being changed to a low voltage during the fourth time period ({circle around (4)}), the data signal may be a first data value, and may be applied to the gate terminal, the drain terminal and the source terminal of the first transistor (Dr. TFT) according to the second transistor T2 being turned-on, and the second initialization signal (VCR) may be a pre-set second initialization value (VCR(A)), and may be applied to the cathode of the light-emitting device according to the seventh transistor T7 being turned-on.” See Fig. 7.)
Allowable Subject Matter
Claims 2 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Further depending claims 3-10 and 13-20 would be allowable based on their dependence from an objected allowable base claim.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Prior art made of record and not relied upon which is still considered pertinent to applicant's disclosure is cited in a current or previous PTO-892. The prior art cited in a current or previous PTO-892 reads upon the applicants claims in part, in whole and/or gives a general reference to the knowledge and skill of persons having ordinary skill in the art before the effective filing date of the invention. Applicant, when responding to this Office action, should consider not only the cited references applied in the rejection but also any additional references made of record.
In the response to this office action, the Examiner respectfully requests support be shown for any new or amended claims. More precisely, indicate support for any newly added language or amendments by specifying page, line numbers, and/or figure(s). This will assist The Office in compact prosecution of this application. The Office has cited particular columns, paragraphs, and/or line numbers in the applied rejection of the claims above for the convenience of the applicant. Citations are representative of the teachings in the art and are applied to the specific limitations within each claim, however other passages and figures may apply. Applicant, in preparing a response, should fully consider the cited reference(s) in its entirety and not only the cited portions as other sections of the reference may expand on the teachings of the cited portion(s).
Applicant Representatives are reminded of CFR 1.4(d)(2)(ii) which states “A patent practitioner (§ 1.32(a)(1) ), signing pursuant to §§ 1.33(b)(1) or 1.33(b)(2), must supply his/her registration number either as part of the S-signature, or immediately below or adjacent to the S-signature. The number (#) character may be used only as part of the S-signature when appearing before a practitioner’s registration number; otherwise the number character may not be used in an S-signature.” When an unsigned or improperly signed amendment is received the amendment will be listed in the contents of the application file, but not entered. The examiner will notify applicant of the status of the application, advising him or her to furnish a duplicate amendment properly signed or to ratify the amendment already filed. In an application not under final rejection, applicant should be given a two month time period in which to ratify the previously filed amendment (37 CFR 1.135(c) ).
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J JANSEN II whose telephone number is (571)272-5604. The examiner can normally be reached Normally Available Monday-Friday 9am-4pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
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/Michael J Jansen II/ Primary Examiner, Art Unit 2626
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