DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made of Applicant arguments/Remarks made in amendment in which the following is noted: claims 1, 16, and 20 are amended and the rejection of the claims are traversed. Claims 1 – 20 are currently pending and an Office action on the merits follows.
Response to Arguments
Applicant's arguments filed 22 January 2026 have been fully considered but they are not persuasive.
Applicant argues CHO (‘222) does not disclose at least horizontal emission lines extending in the first direction in parallel to the first horizontal scan lines. However, the Office disagrees and points to ‘222 Figure 1 which illustrates emission lines EL in parallel with gate lines GL and extending in the first direction, as claimed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 – 8, 10, 12 - 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over KA et al; (Publication number: US 2017/0287937 A1), hereafter ‘937, in view of Lee et al; (Publication number: US 2012/0127412 A1), hereafter ‘412, in view of CHO et al; (Publication number: US 2022/0068222 A1), hereafter ‘222.
Regarding claim 16:
‘937 discloses a display device (‘937 Figure 13) comprising:
a substrate (‘937 Figure 15 110) including a display area (‘937 Figure 13 display area DA), a first non-display area surrounding the display area (‘937 Figure 13 peripheral area PA), a bending area connected to the first non-display area (‘937 Figure 13 bending area BA), and a second non-display area connected to the bending area (‘937 Figure 13 FPCB);
pixels in the display area (‘937 Figure 13 pixels PX) and connected to first horizontal scan lines extending in a first direction (‘937 [0054] A plurality of pixels PX is, for example, arranged in a matrix format in the display area DA of the display panel 300. In the display area DA, signal lines such as a plurality of gate lines G1 to Gn, a plurality of data lines D1 to Dm, and a plurality of driving voltage lines P1 to Po are arranged. The plurality of gate lines G1 to Gn may substantially extend in a first direction DR1 (e.g., a row direction), and the plurality of data lines D1 to Dm and the plurality of driving voltage lines P1 to Po may extend in a second direction DR2 (e.g., a column direction) that crosses the first direction DR1. Each pixel PX is connected with a corresponding gate line among the gate lines G1 to Gn, a corresponding data line among the data lines D1 to Dm, and a corresponding driving voltage line among the driving voltage lines P1 to Po to receive a gate signal, a data voltage, and a driving voltage from the signal lines.).
‘937 does not disclose: i) a first scan driver in the second non-display area wherein the first scan driver is connected to the first vertical scan lines extending in a second direction different from the first direction, and ii) a first emission driver in the first non-display area, the first emission driver is directly connected to the horizontal emission lines extending in the first direction parallel to the first horizontal scan lines, the horizontal emission lines extending the first direction,
However, ‘412 discloses an array substrate for liquid crystal display device and liquid crystal display device including the same. More particularly, ‘412 discloses: i) a first scan driver in the second non-display area (‘412 Figure 4 171a) wherein the first scan driver is connected to the first vertical scan lines extending in a second direction different from the first direction (‘412 [0033] In addition, as shown in FIG. 3, gate lines 113 are formed along a first direction in the display region "DA" of the first substrate 110. In more detail, the gate lines 113 cross the data lines 130 and the auxiliary gate lines 132. Thus, first and second pixel regions "P1" and "P2" are defined by crossing the gate lines 113 and the data lines 130. [0041] In addition, the data pad electrode 157 is electrically connected to the data line 130 via a data link line 135, and the gate pad electrode 153 is electrically connected to the auxiliary gate line 132 via a gate link line 151. The data link line 135 is formed at the same layer as the data line 130. Namely, the data link line 135 extends from the data line 130. Further, the gate link line 151 is preferably formed at a different layer from the auxiliary gate line 132 to avoid an electrical short with the data link line 135. The gate link line 152 is also connected to the auxiliary gate line 132 through a second contact hole "CH2" (see FIG. 4).)
It would have been obvious to modify ‘937 such that the display include i) a first scan driver in the second non-display area wherein the first scan driver is connected to the first vertical scan lines extending in a second direction different from the first direction, as claimed, because such a modification would be based on the use of known techniques to improve similar devices in the same way. More specifically, the LCD display in ‘412 is comparable to the display device in ‘937 as both devices rely on scan/gate driving circuits in a non-display area to perform addressing of the plurality of pixels in the display device to create an image. Therefore, it is within the capabilities of one of ordinary skill in the art to modify ‘937 such that i) a first scan driver in the second non-display area wherein the first scan driver is connected to the first vertical scan lines extending in a second direction different from the first direction, as claimed, with the predictable result of achieving a narrow bezel, thereby improving a form factor of the display device.
Further, ‘222 discloses a display apparatus, method of operating a display apparatus and non-transitory computer-readable medium. More particularly, ‘222 discloses ii) a first emission driver in the first non-display area, the first emission driver is directly connected to the horizontal emission lines extending in the first direction in parallel to the first horizontal scan lines, the horizontal emission lines extending the first direction (‘222 Figure 2 – first emission driver 610 connected to emission lines EL11 – EL1N; Figure emission 1 Emission lines EL are illustrate extended in parallel to gate lines GL).
It would have been obvious to further modify ‘937 (in view of ‘412) such that the display includes ii) a first emission driver in the first non-display area, the first emission driver is directly connected to the horizontal emission lines, the horizontal emission lines extending the first direction, as claimed. Those skilled in the art would appreciate increasing the lifetime of the emission driver, thereby suppressing a flicker or flash phenomenon.
Regarding claim 17:
‘937 (in view of ‘412 and ‘222) discloses the display device according to claim 16, wherein the first vertical scan lines sequentially cross the second non-display area, the bending area, the first non-display area, and the display area (disclosed in combination of ‘937 Figure 13 and ‘412 Figures 2 and 4 since the auxiliary gate lines extend from the display to the gate driving IC within the FCPB).
Regarding claim 18:
‘937 (in view of ‘412 and ‘222) discloses the display device according to claim 16, wherein the first emission driver is positioned in a direction opposite to the first direction from the display area (‘222 Figure 2 610), and the first scan driver is positioned in a direction opposite to the second direction from the display area (‘412 Figures 2 and 4 171a).
Regarding claim 19:
‘937 (in view of ‘412 and ‘222) discloses the display device according to claim 16, further comprising: a second emission driver positioned in the first direction from the display area, wherein the second emission driver is connected to at least a portion of the horizontal emission lines (‘222 Figure 2 second emission driver 620; [0057] The second emission driver 620 may generate emission signals for driving emission lines EL21 to EL2N in response to the fourth control signal CONT4 from the timing controller 200. The second emission driver 620 may output the generated emission signals to the emission lines EL21 to EL2N in a predetermined manner. For example, the second emission driver 620 may sequentially output emission signals to emission lines EL21 to EL2N. In one embodiment, the first emission driver 610 and the second emission driver 620 may operate alternately. In another embodiment, the first emission driver 610 and the second emission driver 620 may operate simultaneously.)
Regarding claim 20:
Claim 20 is similarly rejected for those reasons discussed above in claim 16 (and additionally based on the further teachings related to an electronic device (‘222 Figure 13) comprising: a processor to provide input image data (‘937 [0058] The driving circuit chip 400 includes a signal controller that controls the data driver and the gate drivers 500a and 500b. According to exemplary embodiments of the inventive concept, the signal controller may be provided as a chip that is separate from the data driver, and for example, may be provided as an integrated circuit chip on an external printed circuit board of the display panel 300. Thus, the driving circuit chip 400 mounted on the display panel 300 may include only the data driver with the signal controller provided separately or externally.
[0059] A flexible printed circuit board (FPCB) that transmits an external signal to the display panel 300 is attached to the peripheral area PA of the display panel 300. The FPCB may be attached to a pad portion PP that is disposed further from the display area DA than the driving circuit chip 400 in the peripheral area PA. Thus, the pad portion PP may be disposed between an outer edge of the display panel 300 and the driving circuit chip 400. The driving circuit chip 400 may receive an image signal and a control signal of the image signal through the FPCB and the pad portion PP.).; and
a display device to display an image based on the input image data (‘937 [0004] The OLED display device includes a plurality of pixels in a display area where an image is displayed, and each pixel may include an organic light emitting diode (OLED), a capacitor, a switching transistor, and a driving transistor. A driving voltage is applied to the driving transistor and the capacitor through a driving voltage line. In a peripheral area of the display area, wires are provided to transmit the driving voltage to the driving voltage line. When the length or width of the wires is increased or decreased, current density and voltage drop may also increase or decrease, causing deterioration in luminance uniformity of the image displayed in the display area.).
Regarding claim 1:
Claim 1 is similarly rejected for those reasons discussed above in claim 16.
Regarding claim 2:
Claim 2 is similarly rejected for those reasons discussed above in claim 16.
Regarding claim 3:
Claim 3 is similarly rejected for those reasons discussed above in claim 18.
Regarding claim 4:
Claim 4 is similarly rejected for those reasons discussed above in claim 19.
Regarding claim 5:
‘937 (in view of ‘412 and ‘222) discloses the display device according to claim 4, wherein the first emission driver includes first emission stages, the second emission driver includes second emission stages, and a number of the first emission stages and a number of the second emission stages are equal (‘222 0098] The timing controller 200 may provide a first emission start signal EFLM1 as an emission start signal to the first emission driver 610. The first emission driver 610 may generate first emission signals in response to the first emission start signal EFLM1. The first emission driver 610 may include a plurality of first stages ST11 to ST1(n−1) and ST1n to ST1N connected to the plurality of first emission lines EL11 to EL1(n−1) and ELln to EL1N of the display panel 100, respectively. The first emission lines may be connected to a plurality of pixel circuits. In one embodiment, the first stages ST11 to ST1(n−1) and ST1(n−1) to ST1N may output (e.g., sequentially or according to another predetermined pattern) the first emission signals synchronized with the first clock signal ECLK1 and the second clock signal ECLK2 in response to the first emission start signal EFLM1.
[0099] The timing controller 200 may provide a second emission start signal EFLM2 as an emission start signal to the second emission driver 620. The second emission driver 620 may generate second emission signals in response to the second emission start signal EFLM2. The second emission driver 620 may include a plurality of second stages ST21 to ST2(n−1) and ST2n to ST2N connected to the plurality of second emission lines EL21 to EL2(n−1) and EL2n to EL2N of the display panel 100, respectively. The second emission lines may be connected to a plurality of pixel circuits. In one embodiment, the second stages ST21 to ST2(n−1) and ST2n to ST2N may output (e.g., sequentially or according to another predetermined pattern) the second emission signals synchronized with the first clock signal ECLK1 and the second clock signal ECLK2 in response to the second emission start signal EFLM; see also Figure 8 illustrating equal number of stages)
Regarding claim 6:
‘937 (in view of ‘412 and ‘222) disclose the display device according to claim 5, wherein a number of the horizontal emission lines is equal to a number of the first emission stages, one end of each of the horizontal emission lines is connected to a corresponding one of the first emission stages, and another end of each of the horizontal emission lines is connected to a corresponding one of the second emission stages (‘222 Figure 8 – each one end of the emission lines EL connected to respective stages of first and second emission drivers, accordingly).
Regarding claim 7:
‘937 (in view of ‘412 and ‘222) discloses the display device according to claim 5, wherein a number of the horizontal emission lines is greater than a number of the first emission stages (‘222 Figure 8 – number of lines El1N – EL 21 greater than number of stages), one end of the horizontal emission lines is connected to a corresponding one of the first emission stages in a unit of two horizontal emission lines (‘222 Figure 8 one end of each emission line connected to first stage in a group of two emission lines), and another end of the horizontal emission lines is connected to a corresponding one of the second emission stages in a unit of two horizontal emission lines (‘222 Figure 8 one end of each emission line connected to second stage in a group of two emission lines).
Regarding claim 8:
‘937 (in view of ‘412 and ‘222) discloses the display device according to claim 5, wherein the horizontal emission lines are alternately connected to one of the first emission stages or one of the second emission stages along the second direction (‘222 Figure 8 illustrates connection along a second direction, alternatively, among the first and second emission stages).
Regarding claim 10:
‘937 (in view of ‘412 and ‘222) disclose the display device according to claim 5, wherein the horizontal emission lines are alternately connected to one of the first emission stages or one of the second emission stages along the second direction in a unit of two horizontal emission lines (‘222 Figure 8 illustrates two unit connections along a second direction, alternatively, among the first and second emission stages).
Regarding claim 12:
‘937 (in view of ‘412 and ‘222) disclose the display device according to claim 1, further comprising: an additional scan driver in the non-display area, wherein the additional scan driver is connected to the first vertical scan lines (‘412 see Figure 2 illustrating additional gate driving IC 171a; see also Figure 3 and 5 illustrating connection to auxiliary gate line).
Regarding claim 13:
‘937 (in view of ‘412 and ‘222) disclose the display device according to claim 12, further comprising: a second scan driver in the non-display area, wherein the pixels are further connected to the second horizontal scan lines extending in the first direction, the second scan driver is connected to second vertical scan lines extending in the second direction, and the vertical scan lines contact the second horizontal scan lines in the display area (‘412 see Figure 2 illustrating second gate driving IC 171a extending in the first direction and connected to gate lines via the auxiliary gate line extending in the second direction; see also Figure 3 and 5 illustrating connection to auxiliary gate line).
Regarding claim 14:
‘937 (in view of ‘412 and ‘222) disclose the display device according to claim 13, further comprising: a third scan driver in the non-display area, wherein the pixels are further connected to third horizontal scan lines extending in the first direction, the third scan driver is connected to third vertical scan lines extending in the second direction, and the third vertical scan lines contact the third horizontal scan lines in the display area (‘412 see Figure 2 illustrating third gate driving IC 171a extending in the first direction and connected to third gate lines via the auxiliary gate line extending in the second direction; see also Figure 3 and 5 illustrating connection to auxiliary gate line).
Regarding claim 15:
‘937 (in view of ‘412 and ‘222) disclose the display device according to claim 1, further comprising: a second scan driver positioned in the first direction from the display area, the pixels are further connected to second horizontal scan lines extending in the first direction, and the second scan driver is directly connected to the second horizontal scan lines (‘412 see Figure 2 illustrating second gate driving IC 171a extending in the first direction and connected to gate lines via the auxiliary gate line extending in the second direction; see also Figure 3 and 5 illustrating connection to auxiliary gate line).
Claim(s) 9 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over KA et al; (Publication number: US 2017/0287937 A1), hereafter ‘937, in view of Lee et al; (Publication number: US 2012/0127412 A1), hereafter ‘412, in view of CHO et al; (Publication number: US 2022/0068222 A1), hereafter ‘222, in view of Hashimoto et al; (Patent number: US 11, 005, 475 B1), hereafter ‘475.
Regarding claim 9:
‘937 (in view of ‘412 and ‘222) does not disclose the display device according to claim 8, wherein each of the first emission stages includes a first logic circuit and a first buffer circuit,
each of the second emission stages includes a second logic circuit and a second buffer circuit,
the first buffer circuit is positioned in a direction opposite to the second direction from the logic circuit and is connected to a corresponding horizontal emission line, and the second buffer circuit is positioned in the second direction from the second logic circuit and is connected to a corresponding horizontal emission line.
However, ‘475 discloses an emission diver and pump circuit. More particularly, ‘475 discloses an emission stage includes a logic circuit (‘475 Figure 2 latch circuit 210) and buffer circuit (‘475 Figure 2 220). The buffer circuit is positioned opposite the latch circuit and connected to the horizontal emission line.
It would have been obvious to further modify ‘937 (in view of ‘412 and ‘222) wherein each of the first emission stages includes a first logic circuit and a first buffer circuit, each of the second emission stages includes a second logic circuit and a second buffer circuit, the first buffer circuit is positioned in a direction opposite to the second direction from the logic circuit and is connected to a corresponding horizontal emission line, and the second buffer circuit is positioned in the second direction from the second logic circuit and is connected to a corresponding horizontal emission line¸ as claimed. Those skilled in the art would appreciate effectively improving the stability of the emission signal or the stability of the emission driver (‘475 Col 1 lines 23 – 26).
Regarding claim 11:
‘937 (in view of ‘412 and ‘222) discloses the display device according to claim 10, wherein each of the first emission stages includes a first logic circuit and a first buffer circuit, each of the second emission stages includes a second logic circuit and a second buffer circuit, the first buffer circuit is positioned in a direction opposite to the second direction from the first logic circuit and is connected to two corresponding horizontal emission lines, and the second buffer circuit is positioned in the second direction from the second logic circuit and is connected to two corresponding horizontal lines.
However, ‘475 discloses an emission diver and pump circuit. More particularly, ‘475 discloses an emission stage includes a logic circuit (‘475 Figure 2 latch circuit 210) and buffer circuit (‘475 Figure 2 220). The buffer circuit is positioned opposite the latch circuit and connected to the horizontal emission line.
It would have been obvious to further modify 937 (in view of ‘412 and ‘222) wherein each of the first emission stages includes a first logic circuit and a first buffer circuit, each of the second emission stages includes a second logic circuit and a second buffer circuit, the first buffer circuit is positioned in a direction opposite to the second direction from the first logic circuit and is connected to two corresponding horizontal emission lines, and the second buffer circuit is positioned in the second direction from the second logic circuit and is connected to two corresponding horizontal lines. Those skilled in the art would appreciate effectively improving the stability of the emission signal or the stability of the emission driver (‘475 Col 1 lines 23 – 26).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MIHIR K RAYAN/ 12 May 2026Primary Examiner, Art Unit 2622
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