DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
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Information Disclosure Statement
The information disclosure statement filed 19 March 2025 fails to comply with the provisions of 37 CFR 1.98(a)(4) because it lacks the appropriate size fee assertion. It has been placed in the application file, but the information referred to therein has not been considered as to the merits.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 6, 7, 13, 14, and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 5-7, and 11 of U.S. Patent No. US 12,272,297 (resulting from parent application 18/375,566). Although the claims at issue are not identical, they are not patentably distinct from each other because the patent claims, as a whole, include all of the limitations of the instant application claims, respectively. The patent claims, as a whole, also include additional limitations. Hence, the instant application claims are generic to the species of invention covered by the respective patent claims, as a whole. As such, the instant application claims are anticipated by the patent claims, as a whole, and are therefore not patentably distinct therefrom. (See Eli Lilly and Co. v. Barr Laboratories Inc., 58 USPQ2D 1869, "a later genus claim limitation is anticipated by, and therefore not patentably distinct from, an earlier species claim", In re Goodman, 29 USPQ2d 2010, "Thus, the generic invention is 'anticipated' by the species of the patented invention" and the instant “application claims are generic to species of invention covered by the patent claim, and since without terminal disclaimer, extant species claims preclude issuance of generic application claims”). See the following table.
Claims 2-4, 8-12, 15-17, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 4, and 5 of U.S. Patent No. 12,272,297, in view of Takasugi et al (US 2018/0337682; hereinafter Takasugi).
• Regarding claims 2-4, 8-12, 15-17, and 20, US 12,272,297 claims everything in claims 1, 2, 4, and 5 except the additional details of the scan driver.
In the same field of endeavor, Takasugi discloses the additional details of the scan driver, as shown in the following table.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the claimed invention of US 12,272,297 according to the teachings of Takasugi, for the purpose of reducing power consumption in a display device (¶s 9 and 10).
US 19/083,438
US 12,272,297 (18/375,566)
1. A scan driver comprising:
stage groups each including a first scan stage and a second scan stage,
wherein each of the first and second scan stages outputs a carry signal and a scan signal in response to a previous carry signal provided from a previous stage group,
wherein each of the stage groups stores the previous carry signal provided from the previous stage group in a first capacitor,
wherein each of the stage groups discharges a voltage stored in the first capacitor for the first and second scan stages to a second voltage level in response to a fourth control signal of a fourth control line, and
wherein the first scan stage includes:
a second transistor including a first electrode electrically connected to a first previous carry line, a second electrode electrically connected to a first Q node, and a gate electrode electrically connected to the first electrode of the second transistor;
a ninth transistor including a first electrode electrically connected to a first carry clock line, a second electrode electrically connected to a first carry line, and a gate electrode electrically connected to the first Q node;
a first transistor including a first electrode electrically connected to a first scan clock line, a second electrode electrically connected to a first scan line, and a gate electrode electrically connected to the first Q node;
a sixth transistor including a first electrode electrically connected to a first node, a second electrode electrically connected to the first Q node, and a gate electrode electrically connected to a third control line;
a fifth transistor including a first electrode electrically connected to a second control line, a second electrode electrically connected to the first node, and a gate electrode;
a nineteenth transistor electrically connected to the gate electrode of the fifth transistor and including a gate electrode electrically connected to the fourth control line;
a twenty-fifth transistor including a first electrode electrically connected to a fifth control line, a second electrode, and a gate electrode electrically connected to the fifth control line; and
a twenty-sixth transistor including a first electrode electrically connected to the fifth control line, a second electrode electrically connected to a first QB node, and a gate electrode electrically connected to the second electrode of the twenty-fifth transistor, and
wherein the first capacitor electrically connected between the second control line and the gate electrode of the fifth transistor.
1. A scan driver comprising:
scan stages,
wherein a first scan stage among the scan stages is configured to transfer a first previous carry signal of a first previous carry line to a Q node and output a carry signal, a sensing signal, and a scan signal respectively in response to a voltage of the Q node,
wherein the first scan stage is further configured to store a second previous carry signal of a second previous carry line in a first capacitor, transmit a signal of a first voltage level to a first node in response to a voltage stored in the first capacitor, and connect the first node to the Q node in response to a third control signal of a third control line,
wherein the first scan stage discharges the first capacitor to a second voltage level in response to a fourth control signal of a fourth control line regardless of the first previous carry signal,
wherein the first voltage level is higher than the second voltage level,
wherein the first scan stage includes:
a second transistor including a first electrode electrically connected to the first previous carry line, a second electrode electrically connected to the Q node, and a gate electrode electrically connected to the first electrode of the second transistor;
a ninth transistor including a first electrode electrically connected to a carry clock line, a second electrode electrically connected to a carry line, and a gate electrode electrically connected to the Q node;
a first transistor including a first electrode electrically connected to a scan clock line, a second electrode electrically connected to a scan line, and a gate electrode electrically connected to the Q node;
a sixth transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the Q node, and a gate electrode electrically connected to the third control line;
a fifth transistor including a first electrode electrically connected to a second control line, a second electrode electrically connected to the first node, and a gate electrode;
a nineteenth transistor electrically connected to the gate electrode of the fifth transistor and including a gate electrode electrically connected to the fourth control line;
a thirteenth transistor including a first electrode electrically connected to the carry line, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a QB node;
a seventeenth transistor including a first electrode electrically connected to the scan line, a second electrode electrically connected to a second power line, and a gate electrode electrically connected to the QB node; and
a seventh transistor including a gate electrode electrically connected to the Q node, a first electrode electrically connected to the second control line, and a second electrode electrically connected to the first node, and …
7. The scan driver of claim 6 (which also includes claims 1 and 3-5), wherein the first scan stage further includes:
a twenty-fifth transistor including a gate electrode, a first electrode and a second electrode, the gate electrode and the first electrode of the twenty-fifth transistor being electrically connected to a fifth control line; and
a twenty-sixth transistor including a gate electrode electrically connected to the second electrode of the twenty-fifth transistor, a first electrode electrically connected to the fifth control line, and a second electrode electrically connected to the QB node.
1. …wherein the first capacitor electrically connected between the second control line and the gate electrode of the fifth transistor.
2. The scan driver of claim 1, wherein the first scan stage further includes:
a thirteenth transistor including a first electrode electrically connected to the first carry line, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a first QB node; and
a fourteenth transistor including a first electrode electrically connected to the first carry line, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a second QB node of the second scan stage.
1. A scan driver comprising: …
a thirteenth transistor including a first electrode electrically connected to the carry line, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a QB node; …
Takasugi: element T7crb in figure 5 and ¶ 67
3. The scan driver of claim 1, wherein the first scan stage further includes:
a second capacitor electrically connected between the first Q node and the first scan line;
a seventeenth transistor including a first electrode electrically connected to the first scan line, a second electrode electrically connected to a second power line, and a gate electrode electrically connected to a first QB node; and
an eighteenth transistor including a first electrode electrically connected to the first scan line, a second electrode electrically connected to the second power line, and a gate electrode electrically connected to a second QB node of the second scan stage.
2. The scan driver of claim 1, wherein the first scan stage further includes:
a second capacitor including a first electrode electrically connected to the gate electrode of the first transistor and a second electrode electrically connected to the second electrode of the first transistor.
1. A scan driver comprising: …
a seventeenth transistor including a first electrode electrically connected to the scan line, a second electrode electrically connected to a second power line, and a gate electrode electrically connected to the QB node; and …
Takasugi: element T7b in figure 5 and ¶ 67
4. The scan driver of claim 1, wherein the first scan stage further includes:
an eleventh transistor including a first electrode electrically connected to the first Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a first QB node;
a twelfth transistor including a first electrode electrically connected to the first Q node, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a second QB node of the second scan stage;
a twenty-first transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the first QB node, and a gate electrode electrically connected to the first QB node; and
a twenty-second transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the first QB node, and a gate electrode electrically connected to the first previous carry line.
4. The scan driver of claim 3, wherein the first scan stage further includes:
an eleventh transistor including a gate electrode electrically connected to the QB node, a first electrode electrically connected to the Q node, and a second electrode electrically connected to the first power line.
Takasugi: elements T32a and T32b in figure 5 and ¶ 63
5. The scan driver of claim 4, wherein the first scan stage further includes:
a twentieth transistor including a gate electrode electrically connected to the fourth control line, a first electrode electrically connected to the Q node, and a second electrode electrically connected to the first power line;
a twenty-first transistor including a gate electrode electrically connected to the Q node, a first electrode electrically connected to the first power line, and a second electrode electrically connected to the QB node; and
a twenty-second transistor including a gate electrode electrically connected to the first previous carry line, a first electrode electrically connected to the first power line, and a second electrode electrically connected to the QB node.
6. The scan driver of claim 1, wherein the first scan stage further includes:
a twenty-third transistor including a first electrode electrically connected to a first power line, a second electrode, and a gate electrode electrically connected to the gate electrode of the fifth transistor; and
a twenty-fourth transistor including a first electrode electrically connected to the second electrode of the twenty-third transistor, a second electrode electrically connected to a first QB node, and a gate electrode electrically connected to the third control line.
6. The scan driver of claim 5, wherein the first scan stage further includes:
a twenty-third transistor including a gate electrode electrically connected to a second electrode of a third transistor, a first electrode electrically connected to the first power line, and a second electrode; and
a twenty-fourth transistor including a gate electrode electrically connected to the third control line, a first electrode electrically connected to the second electrode of the twenty-third transistor, and a second electrode electrically connected to the QB node.
7. The scan driver of claim 1, wherein the first scan stage further includes:
a tenth transistor including a first electrode electrically connected to the first Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a next carry line.
3. The scan driver of claim 1, wherein the first scan stage further includes:
a tenth transistor including a gate electrode electrically connected to a reset carry line, a first electrode electrically connected to the Q node, and a second electrode electrically connected to the first power line.
8. The scan driver of claim 1, wherein
the second transistor includes a first sub-transistor electrically connected between the first previous carry line and a third node and a second sub-transistor electrically connected between the third node and the first Q node,
wherein the first scan stage further includes
a seventh transistor including a gate electrode electrically connected to the first Q node, a first electrode electrically connected to the second control line, and a second electrode electrically connected to the third node.
Takasugi: elements T1 and T1a in figure 5 and ¶ 86
1. A scan driver comprising: …
a seventh transistor including a gate electrode electrically connected to the Q node, a first electrode electrically connected to the second control line, and a second electrode electrically connected to the first node, and …
9. The scan driver of claim 1, wherein the second scan stage includes:
wherein the first scan stage includes:
a forty-ninth transistor including a first electrode electrically connected to a second previous carry line, a second electrode electrically connected to a second Q node, and a gate electrode electrically connected to the first electrode of the forty-ninth transistor;
a thirty-second transistor including a first electrode electrically connected to a second carry clock line, a second electrode electrically connected to a second carry line, and a gate electrode electrically connected to the first Q node;
a thirtieth transistor including a first electrode electrically connected to a second scan clock line, a second electrode electrically connected to a second scan line, and a gate electrode electrically connected to the second Q node;
a forty-seventh transistor including a first electrode electrically connected to a second node, a second electrode electrically connected to the second Q node, and a gate electrode electrically connected to the third control line; and
a fiftieth transistor including a gate electrode electrically connected to the second Q node, a first electrode electrically connected to the second control line, and a second electrode electrically connected to a fourth node, and
wherein the forty-ninth transistor includes a third sub-transistor electrically connected between the second Q node and the fourth node and
a fourth sub-transistor electrically connected between the fourth node and the second previous carry line.
Takasugi: figure 5 shows two adjacent shift register stages having similar structures and sharing certain signal lines and being connected to Q and Qb nodes of both stages
10. The scan driver of claim 9, wherein the second scan stage further includes:
a thirty-ninth transistor including a first electrode electrically connected to the second carry line, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a first QB node of the first scan stage; and
a fortieth transistor including a first electrode electrically connected to the second carry line, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a second QB node.
Takasugi: figure 5 shows two adjacent shift register stages having similar structures and sharing certain signal lines and being connected to Q and Qb nodes of both stages
11. The scan driver of claim 9, wherein the second scan stage further includes:
a fourth capacitor electrically connected between the second Q node and the second scan line;
a forty-third transistor including a first electrode electrically connected to the second scan line, a second electrode electrically connected to a second power line, and a gate electrode electrically connected to a first QB node of the first scan stage; and
a forty-fourth transistor including a first electrode electrically connected to the scan line, a second electrode electrically connected to the second power line, and a gate electrode electrically connected to a second QB node.
Takasugi: figure 5 shows two adjacent shift register stages having similar structures and sharing certain signal lines and being connected to Q and Qb nodes of both stages
12. The scan driver of claim 9, wherein the second scan stage further includes:
a thirty-third transistor including a first electrode electrically connected to the second Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a first QB node of the first scan stage;
a thirty-fourth transistor including a first electrode electrically connected to the first Q node, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a second QB node;
a fifty-third transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the second QB node, and a gate electrode electrically connected to the second QB node;
a fifty-fourth transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the second QB node, and a gate electrode electrically connected to the second previous carry line,
a thirty-fifth transistor including a first electrode electrically connected to a sixth control line, a second electrode, and a gate electrode electrically connected to the sixth control line;
a thirty-sixth transistor including a first electrode electrically connected to the sixth control line, a second electrode electrically connected to the second QB node, and a gate electrode electrically connected to the second electrode of the thirty-fifth transistor;
a thirty-seventh transistor including a first electrode electrically connected to the second electrode of the thirty-fifth transistor, a second electrode electrically connected to a third power line, and a gate electrode electrically connected to the first Q node of the first scan stage; and
a thirty-eighth transistor including a first electrode electrically connected to the second electrode of the thirty-fifth transistor, a second electrode electrically connected to the third power line, and a gate electrode electrically connected to the second Q node.
Takasugi: figure 5 shows two adjacent shift register stages having similar structures and sharing certain signal lines and being connected to Q and Qb nodes of both stages
13. A scan driver comprising:
stage groups each including a first scan stage and a second scan stage,
wherein each of the first and second scan stages outputs a carry signal and a scan signal in response to a previous carry signal provided from a previous stage group,
wherein each of the stage groups stores the previous carry signal provided from the previous stage group in a first capacitor,
wherein each of the stage groups discharges a voltage stored in the first capacitor for the first and second scan stages to a second voltage level in response to a first control signal of a first control line, and
wherein each of the stage groups includes:
a fifth transistor including a first electrode electrically connected to a second control line, a second electrode electrically connected to a first node, and a gate electrode;
the first capacitor electrically connected between the second control line and the gate electrode of the fifth transistor; and
a third transistor including a first electrode electrically connected to a previous carry line, a second electrode electrically connected to the gate electrode of the fifth transistor, and a gate electrode electrically connected to the first control line, and
wherein each of the first and second scan stages includes:
a second transistor including a first electrode electrically connected to a corresponding previous carry line, a second electrode electrically connected to a Q node, and a gate electrode electrically connected to the first electrode of the second transistor;
a ninth transistor including a first electrode electrically connected to a carry clock line, a second electrode electrically connected to a corresponding carry line, and a gate electrode electrically connected to the Q node;
a first transistor including a first electrode electrically connected to a scan clock line, a second electrode electrically connected to a corresponding scan line, and a gate electrode electrically connected to the Q node;
a sixth transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the Q node, and a gate electrode electrically connected to a third control line;
a twenty-fifth transistor including a first electrode electrically connected to a fifth control line, a second electrode, and a gate electrode electrically connected to the fifth control line; and
a twenty-sixth transistor including a first electrode electrically connected to the fifth control line, a second electrode electrically connected to a QB node, and a gate electrode electrically connected to the second electrode of the twenty-fifth transistor.
1 (rearranged). A scan driver comprising:
scan stages,
wherein a first scan stage among the scan stages is configured to transfer a first previous carry signal of a first previous carry line to a Q node and output a carry signal, a sensing signal, and a scan signal respectively in response to a voltage of the Q node,
wherein the first scan stage is further configured to store a second previous carry signal of a second previous carry line in a first capacitor, transmit a signal of a first voltage level to a first node in response to a voltage stored in the first capacitor, and connect the first node to the Q node in response to a third control signal of a third control line,
wherein the first scan stage discharges the first capacitor to a second voltage level in response to a fourth control signal of a fourth control line regardless of the first previous carry signal,
wherein the first voltage level is higher than the second voltage level,
wherein the first scan stage includes:
a fifth transistor including a first electrode electrically connected to a second control line, a second electrode electrically connected to the first node, and a gate electrode;
wherein the first capacitor electrically connected between the second control line and the gate electrode of the fifth transistor.
6. The scan driver of claim 5, wherein the first scan stage further includes:
a twenty-third transistor including a gate electrode electrically connected to a second electrode of a third transistor, a first electrode electrically connected to the first power line, and a second electrode; and
a twenty-fourth transistor including a gate electrode electrically connected to the third control line, a first electrode electrically connected to the second electrode of the twenty-third transistor, and a second electrode electrically connected to the QB node.
a second transistor including a first electrode electrically connected to the first previous carry line, a second electrode electrically connected to the Q node, and a gate electrode electrically connected to the first electrode of the second transistor;
a ninth transistor including a first electrode electrically connected to a carry clock line, a second electrode electrically connected to a carry line, and a gate electrode electrically connected to the Q node;
a nineteenth transistor electrically connected to the gate electrode of the fifth transistor and including a gate electrode electrically connected to the fourth control line;
a first transistor including a first electrode electrically connected to a scan clock line, a second electrode electrically connected to a scan line, and a gate electrode electrically connected to the Q node;
a sixth transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the Q node, and a gate electrode electrically connected to the third control line;
a thirteenth transistor including a first electrode electrically connected to the carry line, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a QB node;
a seventeenth transistor including a first electrode electrically connected to the scan line, a second electrode electrically connected to a second power line, and a gate electrode electrically connected to the QB node; and
a seventh transistor including a gate electrode electrically connected to the Q node, a first electrode electrically connected to the second control line, and a second electrode electrically connected to the first node, and …
7. The scan driver of claim 6, wherein the first scan stage further includes:
a twenty-fifth transistor including a gate electrode, a first electrode and a second electrode, the gate electrode and the first electrode of the twenty-fifth transistor being electrically connected to a fifth control line; and
a twenty-sixth transistor including a gate electrode electrically connected to the second electrode of the twenty-fifth transistor, a first electrode electrically connected to the fifth control line, and a second electrode electrically connected to the QB node.
14. The scan driver of claim 13, wherein the third transistor includes:
a fifth sub-transistor including a gate electrode electrically connected to the first control line and a first electrode electrically connected to the previous carry line; and
a sixth sub-transistor including a gate electrode electrically connected to the first control line, a first electrode electrically connected to a second electrode of the fifth sub-transistor, and a second electrode electrically connected to the gate electrode of the fifth transistor, and
wherein each of the stage groups further includes:
a twenty-ninth transistor including a gate electrode electrically connected to the second electrode of the sixth sub-transistor, a first electrode electrically connected to the first electrode of the sixth sub-transistor, and a second electrode electrically connected to the second control line.
11. The scan driver of claim 10, wherein the third transistor includes:
a first sub-transistor including a gate electrode electrically connected to the first control line and a first electrode electrically connected to the previous carry line; and
a second sub-transistor including a gate electrode electrically connected to the first control line, a first electrode electrically connected to a second electrode of the first sub-transistor, and a second electrode electrically connected to the gate electrode of the fifth transistor, and
wherein each of the stage groups further includes:
a twenty-ninth transistor including a gate electrode electrically connected to the second electrode of the second sub-transistor, a first electrode electrically connected to the first electrode of the second sub-transistor, and a second electrode electrically connected to the second control line.
15. The scan driver of claim 13, wherein each of the first and second scan stages further includes:
a thirteenth transistor including a first electrode electrically connected to the corresponding carry line, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a QB node of the first scan stage; and
a fourteenth transistor including a first electrode electrically connected to the corresponding carry line, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a QB node of the second scan stage.
1. A scan driver comprising: …
a thirteenth transistor including a first electrode electrically connected to the carry line, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a QB node; …
Takasugi: element T7crb in figure 5 and ¶ 67
16. The scan driver of claim 13, wherein each of the first and second scan stages further includes:
a second capacitor electrically connected between the Q node and the corresponding scan line;
a seventeenth transistor including a first electrode electrically connected to the corresponding scan line, a second electrode electrically connected to a second power line, and a gate electrode electrically connected to a QB node of the first scan stage; and
an eighteenth transistor including a first electrode electrically connected to the corresponding scan line, a second electrode electrically connected to the second power line, and a gate electrode electrically connected to a QB node of the second scan stage.
2. The scan driver of claim 1, wherein the first scan stage further includes:
a second capacitor including a first electrode electrically connected to the gate electrode of the first transistor and a second electrode electrically connected to the second electrode of the first transistor.
1. A scan driver comprising: …
a seventeenth transistor including a first electrode electrically connected to the scan line, a second electrode electrically connected to a second power line, and a gate electrode electrically connected to the QB node; and …
Takasugi: element T7b in figure 5 and ¶ 67
17. The scan driver of claim 13, wherein each of the first and second scan stages further includes:
an eleventh transistor including a first electrode electrically connected to the Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a QB node of the first scan stage;
a twelfth transistor including a first electrode electrically connected to the Q node, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a QB node of the second scan stage;
a twenty-first transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the QB node, and a gate electrode electrically connected to a corresponding QB node of one of the first and second scan stages; and
a twenty-second transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the corresponding QB node, and a gate electrode electrically connected to the corresponding previous carry line.
4. The scan driver of claim 3, wherein the first scan stage further includes:
an eleventh transistor including a gate electrode electrically connected to the QB node, a first electrode electrically connected to the Q node, and a second electrode electrically connected to the first power line.
Takasugi: elements T32a and T32b in figure 5 and ¶ 63
5. The scan driver of claim 4, wherein the first scan stage further includes:
a twentieth transistor including a gate electrode electrically connected to the fourth control line, a first electrode electrically connected to the Q node, and a second electrode electrically connected to the first power line;
a twenty-first transistor including a gate electrode electrically connected to the Q node, a first electrode electrically connected to the first power line, and a second electrode electrically connected to the QB node; and
a twenty-second transistor including a gate electrode electrically connected to the first previous carry line, a first electrode electrically connected to the first power line, and a second electrode electrically connected to the QB node.
19. The scan driver of claim 13, wherein each of the first and second scan stages further includes:
a twenty-third transistor including a first electrode electrically connected to a first power line, a second electrode, and a gate electrode electrically connected to the gate electrode of the fifth transistor;
a twenty-fourth transistor including a first electrode electrically connected to the second electrode of the twenty-third transistor, a second electrode electrically connected to a QB node, and a gate electrode electrically connected to the third control line
a tenth transistor including a first electrode electrically connected to the Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a next carry line; and
a twentieth transistor including a first electrode electrically connected to the Q node, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a fourth control line.
6. The scan driver of claim 5, wherein the first scan stage further includes:
a twenty-third transistor including a gate electrode electrically connected to a second electrode of a third transistor, a first electrode electrically connected to the first power line, and a second electrode; and
a twenty-fourth transistor including a gate electrode electrically connected to the third control line, a first electrode electrically connected to the second electrode of the twenty-third transistor, and a second electrode electrically connected to the QB node.
3. The scan driver of claim 1, wherein the first scan stage further includes:
a tenth transistor including a gate electrode electrically connected to a reset carry line, a first electrode electrically connected to the Q node, and a second electrode electrically connected to the first power line.
5. The scan driver of claim 4, wherein the first scan stage further includes:
a twentieth transistor including a gate electrode electrically connected to the fourth control line, a first electrode electrically connected to the Q node, and a second electrode electrically connected to the first power line; …
20. The scan driver of claim 13, wherein
the second transistor includes a first sub-transistor electrically connected between the corresponding previous carry line and a third node and a second sub-transistor electrically connected between the third node and the Q node,
wherein each of the first and second scan stages further includes
a seventh transistor including a gate electrode electrically connected to the Q node, a first electrode electrically connected to the second control line, and a second electrode electrically connected to the third node.
Takasugi: elements T1 and T1a in figure 5 and ¶ 86
1. A scan driver comprising: …
a seventh transistor including a gate electrode electrically connected to the Q node, a first electrode electrically connected to the second control line, and a second electrode electrically connected to the first node, and …
Claims 1-4, 6-17, 19, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4, 7-9, 11, 13, 16-18, and 20 of U.S. Patent No. 11,817,042 (resulting from parent application 17/827,272), in view of Takasugi.
• Regarding claims 1-4, 6-17, 19, and 20, US 11,817,042 claims everything in claims 1-4, 7-9, 11, 13, 16-18, and 20 except the additional details of the scan driver.
In the same field of endeavor, Takasugi discloses the additional details of the scan driver, as shown in the following table, and further the reasons previously indicated in this Office action.
US 19/083,438
US 11,817,042 (17/827,272)
1. A scan driver comprising:
stage groups each including a first scan stage and a second scan stage,
wherein each of the first and second scan stages outputs a carry signal and a scan signal in response to a previous carry signal provided from a previous stage group,
wherein each of the stage groups stores the previous carry signal provided from the previous stage group in a first capacitor,
wherein each of the stage groups discharges a voltage stored in the first capacitor for the first and second scan stages to a second voltage level in response to a fourth control signal of a fourth control line, and
wherein the first scan stage includes:
a second transistor including a first electrode electrically connected to a first previous carry line, a second electrode electrically connected to a first Q node, and a gate electrode electrically connected to the first electrode of the second transistor;
a ninth transistor including a first electrode electrically connected to a first carry clock line, a second electrode electrically connected to a first carry line, and a gate electrode electrically connected to the first Q node;
a first transistor including a first electrode electrically connected to a first scan clock line, a second electrode electrically connected to a first scan line, and a gate electrode electrically connected to the first Q node;
a sixth transistor including a first electrode electrically connected to a first node, a second electrode electrically connected to the first Q node, and a gate electrode electrically connected to a third control line;
a fifth transistor including a first electrode electrically connected to a second control line, a second electrode electrically connected to the first node, and a gate electrode;
a nineteenth transistor electrically connected to the gate electrode of the fifth transistor and including a gate electrode electrically connected to the fourth control line;
a twenty-fifth transistor including a first electrode electrically connected to a fifth control line, a second electrode, and a gate electrode electrically connected to the fifth control line; and
a twenty-sixth transistor including a first electrode electrically connected to the fifth control line, a second electrode electrically connected to a first QB node, and a gate electrode electrically connected to the second electrode of the twenty-fifth transistor, and
wherein the first capacitor electrically connected between the second control line and the gate electrode of the fifth transistor.
1 (rearranged). A scan driver comprising:
scan stages, wherein a first scan stage among the scan stages includes:
see the first and ninth transistors below
see the third and fifth transistors below
see the fourth and nineteenth transistors below
Takasugi: elements T1 and T1a in figure 5 and ¶ 86
a ninth transistor including a first electrode connected to a carry clock line, a second electrode connected to a carry line, and a gate electrode connected to the Q node;
a first transistor including a first electrode connected to a scan clock line, a second electrode connected to a scan line, and a gate electrode connected to the Q node; and
a sixth transistor including a first electrode connected to the second electrode of the fifth transistor, a second electrode connected to a Q node, and a gate electrode connected to the third control line;
a fifth transistor including a first electrode connected to a second control line, a second electrode, and a gate electrode electrically connected to the second electrode of the third transistor;
a third transistor including a first electrode connected to a previous carry line, a second electrode, and a gate electrode connected to a first control line;
a twenty-third transistor including a first electrode connected to a first power line, a second electrode, and a gate electrode connected to the second electrode of the third transistor;
a twenty-fourth transistor including a first electrode connected to the second electrode of the twenty-third transistor, a second electrode connected to a QB node, and a gate electrode connected to a third control line;
a thirteenth transistor including a first electrode connected to the carry line, a second electrode connected to the first power line, and a gate electrode connected to the QB node;
a seventeenth transistor including a first electrode connected to the scan line, a second electrode connected to a second power supply line, and a gate electrode connected to the QB node.
20. The scan driver of claim 1, wherein the first stage further includes:
a fourth transistor including a first electrode connected to the gate electrode of the fifth transistor, a second electrode connected to the second electrode of the third transistor, and a gate electrode connected to the previous carry line; and
a nineteenth transistor including a first electrode connected to the first electrode of the fourth transistor, a second electrode connected to the first power line, and a gate electrode connected to a fourth control line.
18. The scan driver of claim 1, wherein the first stage further includes:
a twenty-fifth transistor including a first electrode connected to a fifth control line, a second electrode, and a gate electrode connected to the fifth control line; and
a twenty-sixth transistor including a first electrode connected to the fifth control line, a second electrode connected to the QB node, and a gate electrode connected to the second electrode of the twenty-fifth transistor.
17. The scan driver of claim 1, wherein the first stage further includes:
a first capacitor connected between the second control line and the gate electrode of the fifth transistor.
2. The scan driver of claim 1, wherein the first scan stage further includes:
a thirteenth transistor including a first electrode electrically connected to the first carry line, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a first QB node; and
a fourteenth transistor including a first electrode electrically connected to the first carry line, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a second QB node of the second scan stage.
1. A scan driver comprising: …
a thirteenth transistor including a first electrode connected to the carry line, a second electrode connected to the first power line, and a gate electrode connected to the QB node; …
Takasugi: element T7crb in figure 5 and ¶ 67
3. The scan driver of claim 1, wherein the first scan stage further includes:
a second capacitor electrically connected between the first Q node and the first scan line;
a seventeenth transistor including a first electrode electrically connected to the first scan line, a second electrode electrically connected to a second power line, and a gate electrode electrically connected to a first QB node; and
an eighteenth transistor including a first electrode electrically connected to the first scan line, a second electrode electrically connected to the second power line, and a gate electrode electrically connected to a second QB node of the second scan stage.
4. The scan driver of claim 1, wherein the first stage further includes:
a second capacitor connected between the gate electrode of the first transistor and the scan line.
1. A scan driver comprising: …
a seventeenth transistor including a first electrode connected to the scan line, a second electrode connected to a second power supply line, and a gate electrode connected to the QB node.
Takasugi: element T7b in figure 5 and ¶ 67
4. The scan driver of claim 1, wherein the first scan stage further includes:
an eleventh transistor including a first electrode electrically connected to the first Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a first QB node;
a twelfth transistor including a first electrode electrically connected to the first Q node, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a second QB node of the second scan stage;
a twenty-first transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the first QB node, and a gate electrode electrically connected to the first QB node; and
a twenty-second transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the first QB node, and a gate electrode electrically connected to the first previous carry line.
9. The scan driver of claim 1, wherein the first stage further includes:
an eleventh transistor including a first electrode connected to the Q node, a second electrode connected to the first power line, and a gate electrode connected to the QB node.
Takasugi: elements T32a and T32b in figure 5 and ¶ 63
7. The scan driver of claim 1, wherein the first stage further includes:
a twenty-first transistor including a first electrode connected to the first power line, a second electrode connected to the QB node, and a gate electrode connected to the Q node.
8. The scan driver of claim 1, wherein the first stage further includes:
a twenty-second transistor including a first electrode connected to the first power line, a second electrode connected to the QB node, and a gate electrode connected to a next carry line.
6. The scan driver of claim 1, wherein the first scan stage further includes:
a twenty-third transistor including a first electrode electrically connected to a first power line, a second electrode, and a gate electrode electrically connected to the gate electrode of the fifth transistor; and
a twenty-fourth transistor including a first electrode electrically connected to the second electrode of the twenty-third transistor, a second electrode electrically connected to a first QB node, and a gate electrode electrically connected to the third control line.
1. A scan driver comprising: …
a twenty-third transistor including a first electrode connected to a first power line, a second electrode, and a gate electrode connected to the second electrode of the third transistor;
a twenty-fourth transistor including a first electrode connected to the second electrode of the twenty-third transistor, a second electrode connected to a QB node, and a gate electrode connected to a third control line; …
7. The scan driver of claim 1, wherein the first scan stage further includes:
a tenth transistor including a first electrode electrically connected to the first Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a next carry line.
11. The scan driver of claim 1, wherein the first stage further includes:
a tenth transistor including a first electrode connected to the Q node, a second electrode connected to the first power supply line, and a gate electrode connected to a next carry line.
8. The scan driver of claim 1, wherein
the second transistor includes a first sub-transistor electrically connected between the first previous carry line and a third node and a second sub-transistor electrically connected between the third node and the first Q node,
wherein the first scan stage further includes a seventh transistor including a gate electrode electrically connected to the first Q node, a first electrode electrically connected to the second control line, and a second electrode electrically connected to the third node.
Takasugi: elements T1 and T1a in figure 5 and ¶ 86
16. The scan driver of claim 15, wherein the first stage further includes:
a seventh transistor including a first electrode connected to the second control line, a second electrode connected to the second electrode of the fifth sub-transistor, and a gate electrode connected to the Q node.
9. The scan driver of claim 1, wherein the second scan stage includes:
wherein the first scan stage includes:
a forty-ninth transistor including a first electrode electrically connected to a second previous carry line, a second electrode electrically connected to a second Q node, and a gate electrode electrically connected to the first electrode of the forty-ninth transistor;
a thirty-second transistor including a first electrode electrically connected to a second carry clock line, a second electrode electrically connected to a second carry line, and a gate electrode electrically connected to the first Q node;
a thirtieth transistor including a first electrode electrically connected to a second scan clock line, a second electrode electrically connected to a second scan line, and a gate electrode electrically connected to the second Q node;
a forty-seventh transistor including a first electrode electrically connected to a second node, a second electrode electrically connected to the second Q node, and a gate electrode electrically connected to the third control line; and
a fiftieth transistor including a gate electrode electrically connected to the second Q node, a first electrode electrically connected to the second control line, and a second electrode electrically connected to a fourth node, and
wherein the forty-ninth transistor includes a third sub-transistor electrically connected between the second Q node and the fourth node and
a fourth sub-transistor electrically connected between the fourth node and the second previous carry line.
Takasugi: figure 5 shows two adjacent shift register stages having similar structures and sharing certain signal lines and being connected to Q and Qb nodes of both stages
10. The scan driver of claim 9, wherein the second scan stage further includes:
a thirty-ninth transistor including a first electrode electrically connected to the second carry line, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a first QB node of the first scan stage; and
a fortieth transistor including a first electrode electrically connected to the second carry line, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a second QB node.
Takasugi: figure 5 shows two adjacent shift register stages having similar structures and sharing certain signal lines and being connected to Q and Qb nodes of both stages
11. The scan driver of claim 9, wherein the second scan stage further includes:
a fourth capacitor electrically connected between the second Q node and the second scan line;
a forty-third transistor including a first electrode electrically connected to the second scan line, a second electrode electrically connected to a second power line, and a gate electrode electrically connected to a first QB node of the first scan stage; and
a forty-fourth transistor including a first electrode electrically connected to the scan line, a second electrode electrically connected to the second power line, and a gate electrode electrically connected to a second QB node.
Takasugi: figure 5 shows two adjacent shift register stages having similar structures and sharing certain signal lines and being connected to Q and Qb nodes of both stages
12. The scan driver of claim 9, wherein the second scan stage further includes:
a thirty-third transistor including a first electrode electrically connected to the second Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a first QB node of the first scan stage;
a thirty-fourth transistor including a first electrode electrically connected to the first Q node, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a second QB node;
a fifty-third transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the second QB node, and a gate electrode electrically connected to the second QB node;
a fifty-fourth transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the second QB node, and a gate electrode electrically connected to the second previous carry line,
a thirty-fifth transistor including a first electrode electrically connected to a sixth control line, a second electrode, and a gate electrode electrically connected to the sixth control line;
a thirty-sixth transistor including a first electrode electrically connected to the sixth control line, a second electrode electrically connected to the second QB node, and a gate electrode electrically connected to the second electrode of the thirty-fifth transistor;
a thirty-seventh transistor including a first electrode electrically connected to the second electrode of the thirty-fifth transistor, a second electrode electrically connected to a third power line, and a gate electrode electrically connected to the first Q node of the first scan stage; and
a thirty-eighth transistor including a first electrode electrically connected to the second electrode of the thirty-fifth transistor, a second electrode electrically connected to the third power line, and a gate electrode electrically connected to the second Q node.
Takasugi: figure 5 shows two adjacent shift register stages having similar structures and sharing certain signal lines and being connected to Q and Qb nodes of both stages
13. A scan driver comprising:
stage groups each including a first scan stage and a second scan stage,
wherein each of the first and second scan stages outputs a carry signal and a scan signal in response to a previous carry signal provided from a previous stage group,
wherein each of the stage groups stores the previous carry signal provided from the previous stage group in a first capacitor,
wherein each of the stage groups discharges a voltage stored in the first capacitor for the first and second scan stages to a second voltage level in response to a first control signal of a first control line, and
wherein each of the stage groups includes:
a fifth transistor including a first electrode electrically connected to a second control line, a second electrode electrically connected to a first node, and a gate electrode;
the first capacitor electrically connected between the second control line and the gate electrode of the fifth transistor; and
a third transistor including a first electrode electrically connected to a previous carry line, a second electrode electrically connected to the gate electrode of the fifth transistor, and a gate electrode electrically connected to the first control line, and
wherein each of the first and second scan stages includes:
a second transistor including a first electrode electrically connected to a corresponding previous carry line, a second electrode electrically connected to a Q node, and a gate electrode electrically connected to the first electrode of the second transistor;
a ninth transistor including a first electrode electrically connected to a carry clock line, a second electrode electrically connected to a corresponding carry line, and a gate electrode electrically connected to the Q node;
a first transistor including a first electrode electrically connected to a scan clock line, a second electrode electrically connected to a corresponding scan line, and a gate electrode electrically connected to the Q node;
a sixth transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the Q node, and a gate electrode electrically connected to a third control line;
a twenty-fifth transistor including a first electrode electrically connected to a fifth control line, a second electrode, and a gate electrode electrically connected to the fifth control line; and
a twenty-sixth transistor including a first electrode electrically connected to the fifth control line, a second electrode electrically connected to a QB node, and a gate electrode electrically connected to the second electrode of the twenty-fifth transistor.
1 (rearranged). A scan driver comprising:
scan stages, wherein a first scan stage among the scan stages includes:
see the first and ninth transistors below
see the third and fifth transistors below
see the fourth and nineteenth transistors below
a fifth transistor including a first electrode connected to a second control line, a second electrode, and a gate electrode electrically connected to the second electrode of the third transistor;
see claim 17
a third transistor including a first electrode connected to a previous carry line, a second electrode, and a gate electrode connected to a first control line;
Takasugi: elements T1 and T1a in figure 5 and ¶ 86
a ninth transistor including a first electrode connected to a carry clock line, a second electrode connected to a carry line, and a gate electrode connected to the Q node;
a first transistor including a first electrode connected to a scan clock line, a second electrode connected to a scan line, and a gate electrode connected to the Q node; and
a sixth transistor including a first electrode connected to the second electrode of the fifth transistor, a second electrode connected to a Q node, and a gate electrode connected to the third control line;
a twenty-third transistor including a first electrode connected to a first power line, a second electrode, and a gate electrode connected to the second electrode of the third transistor;
a twenty-fourth transistor including a first electrode connected to the second electrode of the twenty-third transistor, a second electrode connected to a QB node, and a gate electrode connected to a third control line;
a thirteenth transistor including a first electrode connected to the carry line, a second electrode connected to the first power line, and a gate electrode connected to the QB node;
a seventeenth transistor including a first electrode connected to the scan line, a second electrode connected to a second power supply line, and a gate electrode connected to the QB node.
18. The scan driver of claim 1, wherein the first stage further includes:
a twenty-fifth transistor including a first electrode connected to a fifth control line, a second electrode, and a gate electrode connected to the fifth control line; and
a twenty-sixth transistor including a first electrode connected to the fifth control line, a second electrode connected to the QB node, and a gate electrode connected to the second electrode of the twenty-fifth transistor.
17. The scan driver of claim 1, wherein the first stage further includes:
a first capacitor connected between the second control line and the gate electrode of the fifth transistor.
14. The scan driver of claim 13, wherein the third transistor includes:
a fifth sub-transistor including a gate electrode electrically connected to the first control line and a first electrode electrically connected to the previous carry line; and
a sixth sub-transistor including a gate electrode electrically connected to the first control line, a first electrode electrically connected to a second electrode of the fifth sub-transistor, and a second electrode electrically connected to the gate electrode of the fifth transistor, and
wherein each of the stage groups further includes:
a twenty-ninth transistor including a gate electrode electrically connected to the second electrode of the sixth sub-transistor, a first electrode electrically connected to the first electrode of the sixth sub-transistor, and a second electrode electrically connected to the second control line.
2. The scan driver of claim 1, wherein the third transistor includes:
a third sub-transistor including a first electrode connected to the previous carry line, a second electrode, and a gate electrode connected to the first control line; and
a fourth sub-transistor including a first electrode connected to the second electrode of the third sub-transistor, a second electrode electrically connected to the gate electrode of the fifth transistor, and a gate electrode connected to the first control line.
3. The scan driver of claim 2, wherein the first stage further includes:
a twenty-ninth transistor including a first electrode connected to the second electrode of the third sub-transistor, a second electrode connected to the second control line, and a gate electrode connected to the second electrode of the twenty-third transistor.
15. The scan driver of claim 13, wherein each of the first and second scan stages further includes:
a thirteenth transistor including a first electrode electrically connected to the corresponding carry line, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a QB node of the first scan stage; and
a fourteenth transistor including a first electrode electrically connected to the corresponding carry line, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a QB node of the second scan stage.
1. A scan driver comprising: …
a thirteenth transistor including a first electrode connected to the carry line, a second electrode connected to the first power line, and a gate electrode connected to the QB node; …
Takasugi: element T7crb in figure 5 and ¶ 67
16. The scan driver of claim 13, wherein each of the first and second scan stages further includes:
a second capacitor electrically connected between the Q node and the corresponding scan line;
a seventeenth transistor including a first electrode electrically connected to the corresponding scan line, a second electrode electrically connected to a second power line, and a gate electrode electrically connected to a QB node of the first scan stage; and
an eighteenth transistor including a first electrode electrically connected to the corresponding scan line, a second electrode electrically connected to the second power line, and a gate electrode electrically connected to a QB node of the second scan stage.
4. The scan driver of claim 1, wherein the first stage further includes:
a second capacitor connected between the gate electrode of the first transistor and the scan line.
1. A scan driver comprising: …
a seventeenth transistor including a first electrode connected to the scan line, a second electrode connected to a second power supply line, and a gate electrode connected to the QB node.
Takasugi: element T7b in figure 5 and ¶ 67
17. The scan driver of claim 13, wherein each of the first and second scan stages further includes:
an eleventh transistor including a first electrode electrically connected to the Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a QB node of the first scan stage;
a twelfth transistor including a first electrode electrically connected to the Q node, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a QB node of the second scan stage;
a twenty-first transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the QB node, and a gate electrode electrically connected to a corresponding QB node of one of the first and second scan stages; and
a twenty-second transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the corresponding QB node, and a gate electrode electrically connected to the corresponding previous carry line.
9. The scan driver of claim 1, wherein the first stage further includes:
an eleventh transistor including a first electrode connected to the Q node, a second electrode connected to the first power line, and a gate electrode connected to the QB node.
Takasugi: elements T32a and T32b in figure 5 and ¶ 63
7. The scan driver of claim 1, wherein the first stage further includes:
a twenty-first transistor including a first electrode connected to the first power line, a second electrode connected to the QB node, and a gate electrode connected to the Q node.
8. The scan driver of claim 1, wherein the first stage further includes:
a twenty-second transistor including a first electrode connected to the first power line, a second electrode connected to the QB node, and a gate electrode connected to a next carry line.
19. The scan driver of claim 13, wherein each of the first and second scan stages further includes:
a twenty-third transistor including a first electrode electrically connected to a first power line, a second electrode, and a gate electrode electrically connected to the gate electrode of the fifth transistor;
a twenty-fourth transistor including a first electrode electrically connected to the second electrode of the twenty-third transistor, a second electrode electrically connected to a QB node, and a gate electrode electrically connected to the third control line;
a tenth transistor including a first electrode electrically connected to the Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a next carry line; and
a twentieth transistor including a first electrode electrically connected to the Q node, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a fourth control line.
1. A scan driver comprising: …
a twenty-third transistor including a first electrode connected to a first power line, a second electrode, and a gate electrode connected to the second electrode of the third transistor;
a twenty-fourth transistor including a first electrode connected to the second electrode of the twenty-third transistor, a second electrode connected to a QB node, and a gate electrode connected to a third control line; …
11. The scan driver of claim 1, wherein the first stage further includes:
a tenth transistor including a first electrode connected to the Q node, a second electrode connected to the first power supply line, and a gate electrode connected to a next carry line.
13. The scan driver of claim 12, wherein the first stage further includes:
a twentieth transistor including a first electrode connected to the Q node, a second electrode connected to the first power line, and a gate electrode connected to a fourth control line.
20. The scan driver of claim 13, wherein
the second transistor includes a first sub-transistor electrically connected between the corresponding previous carry line and a third node and a second sub-transistor electrically connected between the third node and the Q node,
wherein each of the first and second scan stages further includes a seventh transistor including a gate electrode electrically connected to the Q node, a first electrode electrically connected to the second control line, and a second electrode electrically connected to the third node.
Takasugi: elements T1 and T1a in figure 5 and ¶ 86
16. The scan driver of claim 15, wherein the first stage further includes:
a seventh transistor including a first electrode connected to the second control line, a second electrode connected to the second electrode of the fifth sub-transistor, and a gate electrode connected to the Q node.
Claims 1-7 and 13-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 4-13 of U.S. Patent No. 11,348,513 (resulting from parent application 16/941,140). Although the claims at issue are not identical, they are not patentably distinct from each other because the patent claims, as a whole, include all of the limitations of the instant application claims, respectively. The patent claims, as a whole, also include additional limitations. Hence, the instant application claims are generic to the species of invention covered by the respective patent claims, as a whole. As such, the instant application claims are anticipated by the patent claims, as a whole, and are therefore not patentably distinct therefrom. (See Eli Lilly and Co. v. Barr Laboratories Inc., 58 USPQ2D 1869, "a later genus claim limitation is anticipated by, and therefore not patentably distinct from, an earlier species claim", In re Goodman, 29 USPQ2d 2010, "Thus, the generic invention is 'anticipated' by the species of the patented invention" and the instant “application claims are generic to species of invention covered by the patent claim, and since without terminal disclaimer, extant species claims preclude issuance of generic application claims”). See the following table.
Claims 8-12 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2, 14-19, and 21 of U.S. Patent No. 11,348,513, in view of Takasugi.
• Regarding claims 8-12 and 20, US 11,348,513 claims everything in claims 2, 14-19, and 21 except the additional details of the scan driver.
In the same field of endeavor, Takasugi discloses the additional details of the scan driver, as shown in the following table, and further the reasons previously indicated in this Office action.
US 19/083,438
US 11,348,513 (16/941,140)
1. A scan driver comprising:
stage groups each including a first scan stage and a second scan stage,
wherein each of the first and second scan stages outputs a carry signal and a scan signal in response to a previous carry signal provided from a previous stage group,
wherein each of the stage groups stores the previous carry signal provided from the previous stage group in a first capacitor,
wherein each of the stage groups discharges a voltage stored in the first capacitor for the first and second scan stages to a second voltage level in response to a fourth control signal of a fourth control line, and
wherein the first scan stage includes:
a second transistor including a first electrode electrically connected to a first previous carry line, a second electrode electrically connected to a first Q node, and a gate electrode electrically connected to the first electrode of the second transistor;
a ninth transistor including a first electrode electrically connected to a first carry clock line, a second electrode electrically connected to a first carry line, and a gate electrode electrically connected to the first Q node;
a first transistor including a first electrode electrically connected to a first scan clock line, a second electrode electrically connected to a first scan line, and a gate electrode electrically connected to the first Q node;
a sixth transistor including a first electrode electrically connected to a first node, a second electrode electrically connected to the first Q node, and a gate electrode electrically connected to a third control line;
a fifth transistor including a first electrode electrically connected to a second control line, a second electrode electrically connected to the first node, and a gate electrode;
a nineteenth transistor electrically connected to the gate electrode of the fifth transistor and including a gate electrode electrically connected to the fourth control line;
a twenty-fifth transistor including a first electrode electrically connected to a fifth control line, a second electrode, and a gate electrode electrically connected to the fifth control line; and
a twenty-sixth transistor including a first electrode electrically connected to the fifth control line, a second electrode electrically connected to a first QB node, and a gate electrode electrically connected to the second electrode of the twenty-fifth transistor, and
wherein the first capacitor electrically connected between the second control line and the gate electrode of the fifth transistor.
1 (rearranged). A scan driver comprising:
scan stages, wherein a first scan stage among the scan stages includes:
see the first and ninth transistors below
see the third and fifth transistors below
see the fourth and nineteenth transistors below
a second transistor including a gate electrode, a first electrode, and a second electrode, the gate electrode and the first electrode of the second transistor being coupled to a first scan carry line, the second electrode of the second transistor being coupled to the first Q node;
see claim 4 below
a first transistor including a gate electrode coupled to a first Q node, a first electrode coupled to a first scan clock line, and a second electrode coupled to a first scan line;
a third transistor including a gate electrode coupled to a first control line and a first electrode coupled to a first sensing carry line;
a fourth transistor including a gate electrode coupled to the first sensing carry line and a first electrode coupled to the first electrode of the third transistor;
a sixth transistor including a gate electrode coupled to a third control line, a first electrode coupled to the first node, and a second electrode coupled to the first Q node.
a fifth transistor including a gate electrode coupled to a second electrode of the fourth transistor, a first electrode coupled to a second control line, and a second electrode coupled to a first node;
see claim 8 below
see claim 11 below
see claim 11 below
a first capacitor including a first electrode coupled to the first electrode of the fifth transistor and a second electrode coupled to the gate electrode of the fifth transistor; and
4. The scan driver of claim 1, wherein the first scan stage further includes:
a second capacitor including a first electrode coupled to the gate electrode of the first transistor and a second electrode coupled to the second electrode of the first transistor;
an eighth transistor including a gate electrode coupled to the first Q node, a first electrode coupled to a first sensing clock line, and a second electrode coupled to a first sensing line;
a third capacitor including a first electrode coupled to the gate electrode of the eighth transistor and a second electrode coupled to the second electrode of the eighth transistor; and
a ninth transistor including a gate electrode coupled to the first Q node, a first electrode coupled to a first carry clock line, and a second electrode coupled to a first carry line.
8. The scan driver of claim 7, wherein the first scan stage further includes:
a nineteenth transistor including a gate electrode coupled to a fourth control line, a first electrode coupled to the gate electrode of the fifth transistor, and a second electrode coupled to the first power line.
11. The scan driver of claim 10, wherein the first scan stage further includes:
a twenty-fifth transistor including a gate electrode and a first electrode, the gate electrode and the first electrode of the twenty-fifth transistor being coupled to a fifth control line; and
a twenty-sixth transistor including a gate electrode coupled to the second electrode of the twenty-fifth transistor, a first electrode coupled to the fifth control line, and a second electrode coupled to the first QB node.
2. The scan driver of claim 1, wherein the first scan stage further includes:
a thirteenth transistor including a first electrode electrically connected to the first carry line, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a first QB node; and
a fourteenth transistor including a first electrode electrically connected to the first carry line, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a second QB node of the second scan stage.
7. The scan driver of claim 6, wherein the first scan stage further includes:
a thirteenth transistor including a gate electrode coupled to the first QB node, a first electrode coupled to the first carry line, and a second electrode coupled to the first power line;
a fourteenth transistor including a gate electrode coupled to the second QB node, a first electrode coupled to the first carry line, and a second electrode coupled to the first power line;
a fifteenth transistor including a gate electrode coupled to the first QB node, a first electrode coupled to the first sensing line, and a second electrode coupled to a second power line;
a sixteenth transistor including a gate electrode coupled to the second QB node, a first electrode coupled to the first sensing line, and a second electrode coupled to the second power line;
a seventeenth transistor including a gate electrode coupled to the first QB node, a first electrode coupled to the first scan line, and a second electrode coupled to the second power line; and
an eighteenth transistor including a gate electrode coupled to the second QB node, a first electrode coupled to the first scan line, and a second electrode coupled to the second power line.
3. The scan driver of claim 1, wherein the first scan stage further includes:
a second capacitor electrically connected between the first Q node and the first scan line;
a seventeenth transistor including a first electrode electrically connected to the first scan line, a second electrode electrically connected to a second power line, and a gate electrode electrically connected to a first QB node; and
an eighteenth transistor including a first electrode electrically connected to the first scan line, a second electrode electrically connected to the second power line, and a gate electrode electrically connected to a second QB node of the second scan stage.
7. The scan driver of claim 6, wherein the first scan stage further includes: …
See claim 4 above
a seventeenth transistor including a gate electrode coupled to the first QB node, a first electrode coupled to the first scan line, and a second electrode coupled to the second power line; and
an eighteenth transistor including a gate electrode coupled to the second QB node, a first electrode coupled to the first scan line, and a second electrode coupled to the second power line.
4. The scan driver of claim 1, wherein the first scan stage further includes:
an eleventh transistor including a first electrode electrically connected to the first Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a first QB node;
a twelfth transistor including a first electrode electrically connected to the first Q node, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a second QB node of the second scan stage;
a twenty-first transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the first QB node, and a gate electrode electrically connected to the first QB node; and
a twenty-second transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the first QB node, and a gate electrode electrically connected to the first previous carry line.
6. The scan driver of claim 5, wherein the first scan stage further includes:
an eleventh transistor including a gate electrode coupled to a first QB node, a first electrode coupled to the first Q node, and a second electrode coupled to the first power line; and
a twelfth transistor including a gate electrode coupled to a second QB node, a first electrode coupled to the first Q node, and a second electrode coupled to the first power line.
9. The scan driver of claim 8, wherein the first scan stage further includes:
a twentieth transistor including a gate electrode coupled to the fourth control line, a first electrode coupled to the first Q node, and a second electrode coupled to the first power line;
a twenty-first transistor including a gate electrode coupled to the first Q node, a first electrode coupled to the first power line, and a second electrode coupled to the first QB node; and
a twenty-second transistor including a gate electrode coupled to the first scan carry line, a first electrode coupled to the first power line, and a second electrode coupled to the first QB node.
5. The scan driver of claim 1, wherein the first scan stage further includes:
a twenty-seventh transistor including a first electrode electrically connected to the second electrode of the twenty-fifth transistor, a second electrode electrically connected to a third power line, and a gate electrode electrically connected to the first Q node; and
a twenty-eighth transistor including a first electrode electrically connected to the second electrode of the twenty-fifth transistor, a second electrode electrically connected to the third power line, and a gate electrode electrically connected to a second Q node of the second scan stage.
12. The scan driver of claim 11, wherein the first scan stage further includes:
a twenty-seventh transistor including a gate electrode coupled to the first Q node, a first electrode coupled to the gate electrode of the twenty-sixth transistor, and a second electrode coupled to a third power line; and
a twenty-eighth transistor including a gate electrode coupled to a second Q node, a first electrode coupled to the gate electrode of the twenty-sixth transistor, and a second electrode coupled to the third power line.
6. The scan driver of claim 1, wherein the first scan stage further includes:
a twenty-third transistor including a first electrode electrically connected to a first power line, a second electrode, and a gate electrode electrically connected to the gate electrode of the fifth transistor; and
a twenty-fourth transistor including a first electrode electrically connected to the second electrode of the twenty-third transistor, a second electrode electrically connected to a first QB node, and a gate electrode electrically connected to the third control line.
10. The scan driver of claim 9, wherein the first scan stage further includes:
a twenty-third transistor including a gate electrode coupled to the second electrode of the third transistor and a first electrode coupled to the first power line; and
a twenty-fourth transistor including a gate electrode coupled to the third control line, a first electrode coupled to the second electrode of the twenty-third transistor, and a second electrode coupled to the first QB node.
7. The scan driver of claim 1, wherein the first scan stage further includes:
a tenth transistor including a first electrode electrically connected to the first Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a next carry line.
5. The scan driver of claim 4, wherein the first scan stage further includes:
a tenth transistor including a gate electrode coupled to a first reset carry line, a first electrode coupled to the first Q node, and a second electrode coupled to a first power line.
8. The scan driver of claim 1, wherein
the second transistor includes a first sub-transistor electrically connected between the first previous carry line and a third node and a second sub-transistor electrically connected between the third node and the first Q node,
wherein the first scan stage further includes a seventh transistor including a gate electrode electrically connected to the first Q node, a first electrode electrically connected to the second control line, and a second electrode electrically connected to the third node.
Takasugi: elements T1 and T1a in figure 5 and ¶ 86
2. The scan driver of claim 1, wherein the first scan stage further includes
a seventh transistor including a gate electrode coupled to the first Q node, a first electrode coupled to the second control line, and a second electrode coupled to the first node.
9. The scan driver of claim 1, wherein the second scan stage includes:
wherein the first scan stage includes:
a forty-ninth transistor including a first electrode electrically connected to a second previous carry line, a second electrode electrically connected to a second Q node, and a gate electrode electrically connected to the first electrode of the forty-ninth transistor;
a thirty-second transistor including a first electrode electrically connected to a second carry clock line, a second electrode electrically connected to a second carry line, and a gate electrode electrically connected to the first Q node;
a thirtieth transistor including a first electrode electrically connected to a second scan clock line, a second electrode electrically connected to a second scan line, and a gate electrode electrically connected to the second Q node;
a forty-seventh transistor including a first electrode electrically connected to a second node, a second electrode electrically connected to the second Q node, and a gate electrode electrically connected to the third control line; and
a fiftieth transistor including a gate electrode electrically connected to the second Q node, a first electrode electrically connected to the second control line, and a second electrode electrically connected to a fourth node, and
wherein the forty-ninth transistor includes a third sub-transistor electrically connected between the second Q node and the fourth node and
a fourth sub-transistor electrically connected between the fourth node and the second previous carry line.
19. The scan driver of claim 18, wherein the second scan stage further includes:
a forty-ninth transistor including a first electrode, a gate electrode, and a second electrode, the first electrode of the forty-ninth transistor being coupled to the second Q node, the gate electrode and the second electrode of the forty-ninth transistor being coupled to a second scan carry line; and …
14. The scan driver of claim 13, wherein a second scan stage among the scan stages includes:
a thirty-second transistor including a gate electrode coupled to the second Q node, a first electrode coupled to a second carry line, and a second electrode coupled to a second carry clock line.
a thirtieth transistor including a gate electrode coupled to the second Q node, a first electrode coupled to a second scan line, and a second electrode coupled to a second scan clock line; …
18. The scan driver of claim 17, wherein the second scan stage further includes: …
a forty-seventh transistor including a gate electrode coupled to the third control line, a first electrode coupled to the second Q node, and a second electrode coupled to a second node; …
19. The scan driver of claim 18, wherein the second scan stage further includes: …
a fiftieth transistor including a gate electrode coupled to the second Q node, a first electrode coupled to the second control line, and a second electrode coupled to the second node.
Takasugi: figure 5 shows two adjacent shift register stages having similar structures and sharing certain signal lines and being connected to Q and Qb nodes of both stages
10. The scan driver of claim 9, wherein the second scan stage further includes:
a thirty-ninth transistor including a first electrode electrically connected to the second carry line, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a first QB node of the first scan stage; and
a fortieth transistor including a first electrode electrically connected to the second carry line, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a second QB node.
17. The scan driver of claim 16, wherein the second scan stage further includes:
a thirty-ninth transistor including a gate electrode coupled to the first QB node, a first electrode coupled to the first power line, and a second electrode coupled to the second carry line;
a fortieth transistor including a gate electrode coupled to the second QB node, a first electrode coupled to the first power line, and a second electrode coupled to the second carry line; …
11. The scan driver of claim 9, wherein the second scan stage further includes:
a fourth capacitor electrically connected between the second Q node and the second scan line;
a forty-third transistor including a first electrode electrically connected to the second scan line, a second electrode electrically connected to a second power line, and a gate electrode electrically connected to a first QB node of the first scan stage; and
a forty-fourth transistor including a first electrode electrically connected to the scan line, a second electrode electrically connected to the second power line, and a gate electrode electrically connected to a second QB node.
17. The scan driver of claim 16, wherein the second scan stage further includes:
See claim 14
…a forty-third transistor including a gate electrode coupled to the first QB node, a first electrode coupled to the second power line, and a second electrode coupled to the second scan line; and
a forty-fourth transistor including a gate electrode coupled to the second QB node, a first electrode coupled to the second power line, and a second electrode coupled to the second scan line.
12. The scan driver of claim 9, wherein the second scan stage further includes:
a thirty-third transistor including a first electrode electrically connected to the second Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a first QB node of the first scan stage;
a thirty-fourth transistor including a first electrode electrically connected to the first Q node, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a second QB node;
a fifty-third transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the second QB node, and a gate electrode electrically connected to the second QB node;
a fifty-fourth transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the second QB node, and a gate electrode electrically connected to the second previous carry line,
a thirty-fifth transistor including a first electrode electrically connected to a sixth control line, a second electrode, and a gate electrode electrically connected to the sixth control line;
a thirty-sixth transistor including a first electrode electrically connected to the sixth control line, a second electrode electrically connected to the second QB node, and a gate electrode electrically connected to the second electrode of the thirty-fifth transistor;
a thirty-seventh transistor including a first electrode electrically connected to the second electrode of the thirty-fifth transistor, a second electrode electrically connected to a third power line, and a gate electrode electrically connected to the first Q node of the first scan stage; and
a thirty-eighth transistor including a first electrode electrically connected to the second electrode of the thirty-fifth transistor, a second electrode electrically connected to the third power line, and a gate electrode electrically connected to the second Q node.
15. The scan driver of claim 14, wherein the second scan stage further includes:
a thirty-third transistor including a gate electrode coupled to the first QB node, a first electrode coupled to the first power line, and a second electrode coupled to the second Q node; and
a thirty-fourth transistor including a gate electrode coupled to the second QB node, a first electrode coupled to the first power line, and a second electrode coupled to the second Q node.
21. The scan driver of claim 20, wherein the second scan stage further includes:
a fifty-third transistor including a gate electrode coupled to the second Q node, a first electrode coupled to the second QB node, and a second electrode coupled to the first power line; and
a fifty-fourth transistor including a gate electrode coupled to the first scan carry line, a first electrode coupled to the second QB node, and a second electrode coupled to the first power line.
16. The scan driver of claim 15, wherein the second scan stage further includes:
a thirty-fifth transistor including a gate electrode, a first electrode, and a second electrode, wherein the gate electrode and the second electrode of the thirty-fifth transistor are coupled to a sixth control line;
a thirty-sixth transistor including a gate electrode coupled to the first electrode of the thirty-fifth transistor, a first electrode coupled to the second QB node, and a second electrode coupled to the sixth control line;
a thirty-seventh transistor including a gate electrode coupled to the first Q node, a first electrode coupled to the third power line, and a second electrode coupled to the gate electrode of the thirty-sixth transistor; and
a thirty-eighth transistor including a gate electrode coupled to the second Q node, a first electrode coupled to the third power line, and a second electrode coupled to the gate electrode of the thirty-sixth transistor.
13. A scan driver comprising:
stage groups each including a first scan stage and a second scan stage,
wherein each of the first and second scan stages outputs a carry signal and a scan signal in response to a previous carry signal provided from a previous stage group,
wherein each of the stage groups stores the previous carry signal provided from the previous stage group in a first capacitor,
wherein each of the stage groups discharges a voltage stored in the first capacitor for the first and second scan stages to a second voltage level in response to a first control signal of a first control line, and
wherein each of the stage groups includes:
a fifth transistor including a first electrode electrically connected to a second control line, a second electrode electrically connected to a first node, and a gate electrode;
the first capacitor electrically connected between the second control line and the gate electrode of the fifth transistor; and
a third transistor including a first electrode electrically connected to a previous carry line, a second electrode electrically connected to the gate electrode of the fifth transistor, and a gate electrode electrically connected to the first control line, and
wherein each of the first and second scan stages includes:
a second transistor including a first electrode electrically connected to a corresponding previous carry line, a second electrode electrically connected to a Q node, and a gate electrode electrically connected to the first electrode of the second transistor;
a ninth transistor including a first electrode electrically connected to a carry clock line, a second electrode electrically connected to a corresponding carry line, and a gate electrode electrically connected to the Q node;
a first transistor including a first electrode electrically connected to a scan clock line, a second electrode electrically connected to a corresponding scan line, and a gate electrode electrically connected to the Q node;
a sixth transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the Q node, and a gate electrode electrically connected to a third control line;
a twenty-fifth transistor including a first electrode electrically connected to a fifth control line, a second electrode, and a gate electrode electrically connected to the fifth control line; and
a twenty-sixth transistor including a first electrode electrically connected to the fifth control line, a second electrode electrically connected to a QB node, and a gate electrode electrically connected to the second electrode of the twenty-fifth transistor.
1 (rearranged). A scan driver comprising:
scan stages, wherein a first scan stage among the scan stages includes:
see the first and ninth transistors below
see the third and fifth transistors below
see the fourth and nineteenth transistors below
a fifth transistor including a gate electrode coupled to a second electrode of the fourth transistor, a first electrode coupled to a second control line, and a second electrode coupled to a first node;
a first capacitor including a first electrode coupled to the first electrode of the fifth transistor and a second electrode coupled to the gate electrode of the fifth transistor; and
a third transistor including a gate electrode coupled to a first control line and a first electrode coupled to a first sensing carry line;
a second transistor including a gate electrode, a first electrode, and a second electrode, the gate electrode and the first electrode of the second transistor being coupled to a first scan carry line, the second electrode of the second transistor being coupled to the first Q node;
see claim 4
a first transistor including a gate electrode coupled to a first Q node, a first electrode coupled to a first scan clock line, and a second electrode coupled to a first scan line;
a sixth transistor including a gate electrode coupled to a third control line, a first electrode coupled to the first node, and a second electrode coupled to the first Q node.
a fourth transistor including a gate electrode coupled to the first sensing carry line and a first electrode coupled to the first electrode of the third transistor;
see claim 11
see claim 11
14. The scan driver of claim 13, wherein the third transistor includes:
a fifth sub-transistor including a gate electrode electrically connected to the first control line and a first electrode electrically connected to the previous carry line; and
a sixth sub-transistor including a gate electrode electrically connected to the first control line, a first electrode electrically connected to a second electrode of the fifth sub-transistor, and a second electrode electrically connected to the gate electrode of the fifth transistor, and
wherein each of the stage groups further includes:
a twenty-ninth transistor including a gate electrode electrically connected to the second electrode of the sixth sub-transistor, a first electrode electrically connected to the first electrode of the sixth sub-transistor, and a second electrode electrically connected to the second control line.
13. The scan driver of claim 12, wherein the third transistor includes:
a first sub-transistor including a gate electrode coupled to the first control line and a first electrode coupled to the first sensing carry line; and
a second sub-transistor including a gate electrode coupled to the first control line, a first electrode coupled to a second electrode of the first sub-transistor, and a second electrode coupled to the second electrode of the first capacitor,
wherein the first scan stage further includes:
a twenty-ninth transistor including a gate electrode coupled to the second electrode of the second sub-transistor, a first electrode coupled to the first electrode of the second sub-transistor, and a second electrode coupled to the second control line.
15. The scan driver of claim 13, wherein each of the first and second scan stages further includes:
a thirteenth transistor including a first electrode electrically connected to the corresponding carry line, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a QB node of the first scan stage; and
a fourteenth transistor including a first electrode electrically connected to the corresponding carry line, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a QB node of the second scan stage.
7. The scan driver of claim 6, wherein the first scan stage further includes:
a thirteenth transistor including a gate electrode coupled to the first QB node, a first electrode coupled to the first carry line, and a second electrode coupled to the first power line;
a fourteenth transistor including a gate electrode coupled to the second QB node, a first electrode coupled to the first carry line, and a second electrode coupled to the first power line; …
16. The scan driver of claim 13, wherein each of the first and second scan stages further includes:
a second capacitor electrically connected between the Q node and the corresponding scan line;
a seventeenth transistor including a first electrode electrically connected to the corresponding scan line, a second electrode electrically connected to a second power line, and a gate electrode electrically connected to a QB node of the first scan stage; and
an eighteenth transistor including a first electrode electrically connected to the corresponding scan line, a second electrode electrically connected to the second power line, and a gate electrode electrically connected to a QB node of the second scan stage.
4. The scan driver of claim 1, wherein the first scan stage further includes:
a second capacitor including a first electrode coupled to the gate electrode of the first transistor and a second electrode coupled to the second electrode of the first transistor; …
7. The scan driver of claim 6, wherein the first scan stage further includes: …
a seventeenth transistor including a gate electrode coupled to the first QB node, a first electrode coupled to the first scan line, and a second electrode coupled to the second power line; and
an eighteenth transistor including a gate electrode coupled to the second QB node, a first electrode coupled to the first scan line, and a second electrode coupled to the second power line.
17. The scan driver of claim 13, wherein each of the first and second scan stages further includes:
an eleventh transistor including a first electrode electrically connected to the Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a QB node of the first scan stage;
a twelfth transistor including a first electrode electrically connected to the Q node, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a QB node of the second scan stage;
a twenty-first transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the QB node, and a gate electrode electrically connected to a corresponding QB node of one of the first and second scan stages; and
a twenty-second transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the corresponding QB node, and a gate electrode electrically connected to the corresponding previous carry line.
6. The scan driver of claim 5, wherein the first scan stage further includes:
an eleventh transistor including a gate electrode coupled to a first QB node, a first electrode coupled to the first Q node, and a second electrode coupled to the first power line; and
a twelfth transistor including a gate electrode coupled to a second QB node, a first electrode coupled to the first Q node, and a second electrode coupled to the first power line.
9. The scan driver of claim 8, wherein the first scan stage further includes:
a twentieth transistor including a gate electrode coupled to the fourth control line, a first electrode coupled to the first Q node, and a second electrode coupled to the first power line;
a twenty-first transistor including a gate electrode coupled to the first Q node, a first electrode coupled to the first power line, and a second electrode coupled to the first QB node; and
a twenty-second transistor including a gate electrode coupled to the first scan carry line, a first electrode coupled to the first power line, and a second electrode coupled to the first QB node.
18. The scan driver of claim 13, wherein each of the first and second scan stages further includes:
a twenty-seventh transistor including a first electrode electrically connected to the second electrode of the twenty-fifth transistor, a second electrode electrically connected to a third power line, and a gate electrode electrically connected to the Q node of the first scan stage; and
a twenty-eighth transistor including a first electrode electrically connected to the second electrode of the twenty-fifth transistor, a second electrode electrically connected to the third power line, and a gate electrode electrically connected to the Q node of the second scan stage.
12. The scan driver of claim 11, wherein the first scan stage further includes:
a twenty-seventh transistor including a gate electrode coupled to the first Q node, a first electrode coupled to the gate electrode of the twenty-sixth transistor, and a second electrode coupled to a third power line; and
a twenty-eighth transistor including a gate electrode coupled to a second Q node, a first electrode coupled to the gate electrode of the twenty-sixth transistor, and a second electrode coupled to the third power line.
19. The scan driver of claim 13, wherein each of the first and second scan stages further includes:
a twenty-third transistor including a first electrode electrically connected to a first power line, a second electrode, and a gate electrode electrically connected to the gate electrode of the fifth transistor;
a twenty-fourth transistor including a first electrode electrically connected to the second electrode of the twenty-third transistor, a second electrode electrically connected to a QB node, and a gate electrode electrically connected to the third control line
a tenth transistor including a first electrode electrically connected to the Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a next carry line; and
a twentieth transistor including a first electrode electrically connected to the Q node, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a fourth control line.
10. The scan driver of claim 9, wherein the first scan stage further includes:
a twenty-third transistor including a gate electrode coupled to the second electrode of the third transistor and a first electrode coupled to the first power line; and
a twenty-fourth transistor including a gate electrode coupled to the third control line, a first electrode coupled to the second electrode of the twenty-third transistor, and a second electrode coupled to the first QB node.
5. The scan driver of claim 4, wherein the first scan stage further includes:
a tenth transistor including a gate electrode coupled to a first reset carry line, a first electrode coupled to the first Q node, and a second electrode coupled to a first power line.
9. The scan driver of claim 8, wherein the first scan stage further includes:
a twentieth transistor including a gate electrode coupled to the fourth control line, a first electrode coupled to the first Q node, and a second electrode coupled to the first power line; …
20. The scan driver of claim 13, wherein
the second transistor includes a first sub-transistor electrically connected between the corresponding previous carry line and a third node and a second sub-transistor electrically connected between the third node and the Q node,
wherein each of the first and second scan stages further includes
a seventh transistor including a gate electrode electrically connected to the Q node, a first electrode electrically connected to the second control line, and a second electrode electrically connected to the third node.
Takasugi: elements T1 and T1a in figure 5 and ¶ 86
2. The scan driver of claim 1, wherein the first scan stage further includes
a seventh transistor including a gate electrode coupled to the first Q node, a first electrode coupled to the second control line, and a second electrode coupled to the first node.
Claims 1-7 and 9-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 4-13 of U.S. Patent No. 11,227,552 (resulting from application 16/903,307). Although the claims at issue are not identical, they are not patentably distinct from each other because the patent claims, as a whole, include all of the limitations of the instant application claims, respectively. The patent claims, as a whole, also include additional limitations. Hence, the instant application claims are generic to the species of invention covered by the respective patent claims, as a whole. As such, the instant application claims are anticipated by the patent claims, as a whole, and are therefore not patentably distinct therefrom. (See Eli Lilly and Co. v. Barr Laboratories Inc., 58 USPQ2D 1869, "a later genus claim limitation is anticipated by, and therefore not patentably distinct from, an earlier species claim", In re Goodman, 29 USPQ2d 2010, "Thus, the generic invention is 'anticipated' by the species of the patented invention" and the instant “application claims are generic to species of invention covered by the patent claim, and since without terminal disclaimer, extant species claims preclude issuance of generic application claims”). See the following table.
Claims 8-12 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2, 14-19, and 21 of U.S. Patent No. 11,227,552, in view of Takasugi.
• Regarding claims 8-12 and 20, US 11,227,552 claims everything in claims 2, 14-19, and 21 except the additional details of the scan driver.
In the same field of endeavor, Takasugi discloses the additional details of the scan driver, as shown in the following table, and further the reasons previously indicated in this Office action.
US 19/083,438
US 11,227,552 (16/903,307)
1. A scan driver comprising:
stage groups each including a first scan stage and a second scan stage,
wherein each of the first and second scan stages outputs a carry signal and a scan signal in response to a previous carry signal provided from a previous stage group,
wherein each of the stage groups stores the previous carry signal provided from the previous stage group in a first capacitor,
wherein each of the stage groups discharges a voltage stored in the first capacitor for the first and second scan stages to a second voltage level in response to a fourth control signal of a fourth control line, and
wherein the first scan stage includes:
a second transistor including a first electrode electrically connected to a first previous carry line, a second electrode electrically connected to a first Q node, and a gate electrode electrically connected to the first electrode of the second transistor;
a ninth transistor including a first electrode electrically connected to a first carry clock line, a second electrode electrically connected to a first carry line, and a gate electrode electrically connected to the first Q node;
a first transistor including a first electrode electrically connected to a first scan clock line, a second electrode electrically connected to a first scan line, and a gate electrode electrically connected to the first Q node;
a sixth transistor including a first electrode electrically connected to a first node, a second electrode electrically connected to the first Q node, and a gate electrode electrically connected to a third control line;
a fifth transistor including a first electrode electrically connected to a second control line, a second electrode electrically connected to the first node, and a gate electrode;
a nineteenth transistor electrically connected to the gate electrode of the fifth transistor and including a gate electrode electrically connected to the fourth control line;
a twenty-fifth transistor including a first electrode electrically connected to a fifth control line, a second electrode, and a gate electrode electrically connected to the fifth control line; and
a twenty-sixth transistor including a first electrode electrically connected to the fifth control line, a second electrode electrically connected to a first QB node, and a gate electrode electrically connected to the second electrode of the twenty-fifth transistor, and
wherein the first capacitor electrically connected between the second control line and the gate electrode of the fifth transistor.
1 (rearranged). A scan driver comprising:
a plurality of scan stages,
see the first and ninth transistors below
see the third and fifth transistors below
see the fourth and nineteenth transistors below
wherein a first scan stage among the plurality of scan stages comprises:
a second transistor having a gate electrode and one electrode connected to a first scan carry line, and another electrode connected to the first Q node;
see claim 4 below
a first transistor having a gate electrode connected to a first Q node, one electrode connected to a first scan clock line, and another electrode connected to a first scan line;
a sixth transistor having a gate electrode connected to a third control line, one electrode connected to the first node, and another electrode connected to the first Q node.
a fifth transistor having a gate electrode connected to another electrode of the fourth transistor, one electrode connected to a second control line, and another electrode connected to a first node;
a third transistor having a gate electrode connected to a first sensing carry line and one electrode connected to a second sensing carry line;
a fourth transistor having a gate electrode connected to a first control line, and one electrode connected to another electrode of the third transistor;
a first capacitor having one electrode connected to the one electrode of the fifth transistor, and another electrode connected to the gate electrode of the fifth transistor; and
see claim 8 below
see claim 11 below
See claim 11 below
See claim 1 above
4. The scan driver according to claim 2, wherein the first scan stage further comprises:
a second capacitor having one electrode connected to the gate electrode of the first transistor and another electrode connected to the other electrode of the first transistor;
an eighth transistor having a gate electrode connected to the first Q node, one electrode connected to a first sensing clock line, and another electrode connected to a first sensing line;
a third capacitor having one electrode connected to the gate electrode of the eighth transistor and another electrode connected to another electrode of the eighth transistor; and
a ninth transistor having a gate electrode connected to the first Q node, one electrode connected to a first carry clock line, and another electrode connected to a first carry line.
8. The scan driver according to claim 7, wherein the first scan stage further comprises
a nineteenth transistor having a gate electrode connected to a fourth control line, one electrode connected to the gate electrode of the fifth transistor, and another electrode connected to the first power line.
11. The scan driver according to claim 10, wherein the first scan stage further comprises:
a twenty-fifth transistor having a gate electrode and one electrode connected to a fifth control line; and
a twenty-sixth transistor having a gate electrode connected to another electrode of the twenty-fifth transistor, one electrode connected to the fifth control line, and another electrode connected to the first QB node.
2. The scan driver of claim 1, wherein the first scan stage further includes:
a thirteenth transistor including a first electrode electrically connected to the first carry line, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a first QB node; and
a fourteenth transistor including a first electrode electrically connected to the first carry line, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a second QB node of the second scan stage.
7. The scan driver according to claim 6, wherein the first scan stage further comprises:
a thirteenth transistor having a gate electrode connected to the first QB node, one electrode connected to the first carry line, and another electrode connected to the first power line;
a fourteenth transistor having a gate electrode connected to the second QB node, one electrode connected to the first carry line, and another electrode connected to the first power line;
a fifteenth transistor having a gate electrode connected to the first QB node, one electrode connected to the first sensing line, and another electrode connected to a second power line;
a sixteenth transistor having a gate electrode connected to the second QB node, one electrode connected to the first sensing line, and another electrode connected to the second power line;
a seventeenth transistor having a gate electrode connected to the first QB node, one electrode connected to the first scan line, and another electrode connected to the second power line; and
an eighteenth transistor having a gate electrode connected to the second QB node, one electrode connected to the first scan line, and another electrode connected to the second power line.
3. The scan driver of claim 1, wherein the first scan stage further includes:
a second capacitor electrically connected between the first Q node and the first scan line;
a seventeenth transistor including a first electrode electrically connected to the first scan line, a second electrode electrically connected to a second power line, and a gate electrode electrically connected to a first QB node; and
an eighteenth transistor including a first electrode electrically connected to the first scan line, a second electrode electrically connected to the second power line, and a gate electrode electrically connected to a second QB node of the second scan stage.
4. The scan driver according to claim 2, wherein the first scan stage further comprises:
a second capacitor having one electrode connected to the gate electrode of the first transistor and another electrode connected to the other electrode of the first transistor; …
7. The scan driver according to claim 6, wherein the first scan stage further comprises: …
a seventeenth transistor having a gate electrode connected to the first QB node, one electrode connected to the first scan line, and another electrode connected to the second power line; and
an eighteenth transistor having a gate electrode connected to the second QB node, one electrode connected to the first scan line, and another electrode connected to the second power line.
4. The scan driver of claim 1, wherein the first scan stage further includes:
an eleventh transistor including a first electrode electrically connected to the first Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a first QB node;
a twelfth transistor including a first electrode electrically connected to the first Q node, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a second QB node of the second scan stage;
a twenty-first transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the first QB node, and a gate electrode electrically connected to the first QB node; and
a twenty-second transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the first QB node, and a gate electrode electrically connected to the first previous carry line.
6. The scan driver according to claim 5, wherein the first scan stage further comprises:
an eleventh transistor having a gate electrode connected to a first QB node, one electrode connected to the first Q node, and another electrode connected to the first power line; and
a twelfth transistor having a gate electrode connected to a second QB node, one electrode connected to the first Q node, and another electrode connected to the first power line.
9. The scan driver according to claim 8, wherein the first scan stage further comprises: …
…a twenty-first transistor having a gate electrode connected to the first Q node, one electrode connected to the first power line, and another electrode connected to the first QB node; and
a twenty-second transistor having a gate electrode connected to the first scan carry line, one electrode connected to the first power line, and another electrode connected to the first QB node.
5. The scan driver of claim 1, wherein the first scan stage further includes:
a twenty-seventh transistor including a first electrode electrically connected to the second electrode of the twenty-fifth transistor, a second electrode electrically connected to a third power line, and a gate electrode electrically connected to the first Q node; and
a twenty-eighth transistor including a first electrode electrically connected to the second electrode of the twenty-fifth transistor, a second electrode electrically connected to the third power line, and a gate electrode electrically connected to a second Q node of the second scan stage.
12. The scan driver according to claim 11, wherein the first scan stage further comprises:
a twenty-seventh transistor having a gate electrode connected to the first Q node, one electrode connected to the gate electrode of the twenty-sixth transistor, and another electrode connected to a third power line; and
a twenty-eighth transistor having a gate electrode connected to a second Q node, one electrode connected to the gate electrode of the twenty-sixth transistor, and another electrode connected to the third power line.
6. The scan driver of claim 1, wherein the first scan stage further includes:
a twenty-third transistor including a first electrode electrically connected to a first power line, a second electrode, and a gate electrode electrically connected to the gate electrode of the fifth transistor; and
a twenty-fourth transistor including a first electrode electrically connected to the second electrode of the twenty-third transistor, a second electrode electrically connected to a first QB node, and a gate electrode electrically connected to the third control line.
10. The scan driver according to claim 9, wherein the first scan stage further comprises:
a twenty-third transistor having a gate electrode connected to the other electrode of the fourth transistor, and one electrode connected to the first power line; and
a twenty-fourth transistor having a gate electrode connected to the third control line, one electrode connected to another electrode of the twenty-third transistor, and another electrode connected to the first QB node.
7. The scan driver of claim 1, wherein the first scan stage further includes:
a tenth transistor including a first electrode electrically connected to the first Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a next carry line.
5. The scan driver according to claim 4, wherein the first scan stage further comprises
a tenth transistor having a gate electrode connected to a first reset carry line, one electrode connected to the first Q node, and another electrode connected to a first power line.
8. The scan driver of claim 1, wherein
the second transistor includes a first sub-transistor electrically connected between the first previous carry line and a third node and a second sub-transistor electrically connected between the third node and the first Q node,
wherein the first scan stage further includes
a seventh transistor including a gate electrode electrically connected to the first Q node, a first electrode electrically connected to the second control line, and a second electrode electrically connected to the third node.
Takasugi: elements T1 and T1a in figure 5 and ¶ 86
2. The scan driver according to claim 1, wherein the first scan stage further comprises
a seventh transistor having a gate electrode connected to the first Q node, one electrode connected to the second control line, and another electrode connected to the first node.
9. The scan driver of claim 1, wherein the second scan stage includes:
wherein the first scan stage includes:
a forty-ninth transistor including a first electrode electrically connected to a second previous carry line, a second electrode electrically connected to a second Q node, and a gate electrode electrically connected to the first electrode of the forty-ninth transistor;
a thirty-second transistor including a first electrode electrically connected to a second carry clock line, a second electrode electrically connected to a second carry line, and a gate electrode electrically connected to the first Q node;
a thirtieth transistor including a first electrode electrically connected to a second scan clock line, a second electrode electrically connected to a second scan line, and a gate electrode electrically connected to the second Q node;
a forty-seventh transistor including a first electrode electrically connected to a second node, a second electrode electrically connected to the second Q node, and a gate electrode electrically connected to the third control line; and
a fiftieth transistor including a gate electrode electrically connected to the second Q node, a first electrode electrically connected to the second control line, and a second electrode electrically connected to a fourth node, and
wherein the forty-ninth transistor includes a third sub-transistor electrically connected between the second Q node and the fourth node and
a fourth sub-transistor electrically connected between the fourth node and the second previous carry line.
19. The scan driver according to claim 18, wherein the second scan stage further comprises:
a forty-ninth transistor having one electrode connected to the second Q node, and a gate electrode and another electrode connected to a second scan carry line; and
a fiftieth transistor having a gate electrode connected to the second Q node, one electrode connected to the second control line, and another electrode connected to the second node.
14 (rearranged). The scan driver according to claim 13, wherein a second scan stage among the plurality of scan stages comprises:
a thirty-second transistor having a gate electrode connected to the second Q node, one electrode connected to a second carry line, and another electrode connected to a second carry clock line.
a thirtieth transistor having a gate electrode connected to the second Q node, one electrode connected to a second scan line, and another electrode connected to a second scan clock line; …
18 (rearranged). The scan driver according to claim 17, wherein the second scan stage further comprises: …
a forty-seventh transistor having a gate electrode connected to the third control line, one electrode connected to the second Q node, and another electrode connected to a second node; …
see claim 19 above
Takasugi: figure 5 shows two adjacent shift register stages having similar structures and sharing certain signal lines and being connected to Q and Qb nodes of both stages
10. The scan driver of claim 9, wherein the second scan stage further includes:
a thirty-ninth transistor including a first electrode electrically connected to the second carry line, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a first QB node of the first scan stage; and
a fortieth transistor including a first electrode electrically connected to the second carry line, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a second QB node.
17. The scan driver according to claim 16, wherein the second scan stage further comprises:
a thirty-ninth transistor having a gate electrode connected to the first QB node, one electrode connected to the first power line, and another electrode connected to the second carry line;
a fortieth transistor having a gate electrode connected to the second QB node, one electrode connected to the first power line, and another electrode connected to the second carry line; …
11. The scan driver of claim 9, wherein the second scan stage further includes:
a fourth capacitor electrically connected between the second Q node and the second scan line;
a forty-third transistor including a first electrode electrically connected to the second scan line, a second electrode electrically connected to a second power line, and a gate electrode electrically connected to a first QB node of the first scan stage; and
a forty-fourth transistor including a first electrode electrically connected to the scan line, a second electrode electrically connected to the second power line, and a gate electrode electrically connected to a second QB node.
14. The scan driver according to claim 13, wherein a second scan stage among the plurality of scan stages comprises: …
a fourth capacitor connecting the gate electrode and the one electrode of the thirtieth transistor to each other; …
17. The scan driver according to claim 16, wherein the second scan stage further comprises: …
a forty-third transistor having a gate electrode connected to the first QB node, one electrode connected to the second power line, and another electrode connected to the second scan line; and
a forty-forth transistor having a gate electrode connected to the second QB node, one electrode connected to the second power line, and another electrode connected to the second scan line.
12. The scan driver of claim 9, wherein the second scan stage further includes:
a thirty-third transistor including a first electrode electrically connected to the second Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a first QB node of the first scan stage;
a thirty-fourth transistor including a first electrode electrically connected to the first Q node, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a second QB node;
a fifty-third transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the second QB node, and a gate electrode electrically connected to the second QB node;
a fifty-fourth transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the second QB node, and a gate electrode electrically connected to the second previous carry line,
a thirty-fifth transistor including a first electrode electrically connected to a sixth control line, a second electrode, and a gate electrode electrically connected to the sixth control line;
a thirty-sixth transistor including a first electrode electrically connected to the sixth control line, a second electrode electrically connected to the second QB node, and a gate electrode electrically connected to the second electrode of the thirty-fifth transistor;
a thirty-seventh transistor including a first electrode electrically connected to the second electrode of the thirty-fifth transistor, a second electrode electrically connected to a third power line, and a gate electrode electrically connected to the first Q node of the first scan stage; and
a thirty-eighth transistor including a first electrode electrically connected to the second electrode of the thirty-fifth transistor, a second electrode electrically connected to the third power line, and a gate electrode electrically connected to the second Q node.
15. The scan driver according to claim 14, wherein the second scan stage further comprises:
a thirty-third transistor having a gate electrode connected to the first QB node, one electrode connected to the first power line, and another electrode connected to the second Q node; and
a thirty-fourth transistor having a gate electrode connected to the second QB node, one electrode connected to the first power line, and another electrode connected to the second Q node.
21. The scan driver according to claim 20, wherein the second scan stage further comprises:
a fifty-third transistor having a gate electrode connected to the second Q node, one electrode connected to the second QB node, and another electrode connected to the first power line; and
a fifty-fourth transistor having a gate electrode connected to the first scan carry line, one electrode connected to the second QB node, and another electrode connected to the first power line.
16. The scan driver according to claim 15, wherein the second scan stage further comprises:
a thirty-fifth transistor having a gate electrode, one electrode, and another electrode, the gate electrode and the other electrode being connected to a sixth control line;
a thirty-sixth transistor having a gate electrode connected to the one electrode of the thirty-fifth transistor, one electrode connected to the second QB node, and another electrode connected to the sixth control line;
a thirty-seventh transistor having a gate electrode connected to the first Q node, one electrode connected to the third power line, and another electrode connected to the gate electrode of the thirty-sixth transistor; and
a thirty-eighth transistor having a gate electrode connected to the second Q node, one electrode connected to the third power line, and another electrode connected to the gate electrode of the thirty-sixth transistor.
13. A scan driver comprising:
stage groups each including a first scan stage and a second scan stage,
wherein each of the first and second scan stages outputs a carry signal and a scan signal in response to a previous carry signal provided from a previous stage group,
wherein each of the stage groups stores the previous carry signal provided from the previous stage group in a first capacitor,
wherein each of the stage groups discharges a voltage stored in the first capacitor for the first and second scan stages to a second voltage level in response to a first control signal of a first control line, and
wherein each of the stage groups includes:
a fifth transistor including a first electrode electrically connected to a second control line, a second electrode electrically connected to a first node, and a gate electrode;
the first capacitor electrically connected between the second control line and the gate electrode of the fifth transistor; and
a third transistor including a first electrode electrically connected to a previous carry line, a second electrode electrically connected to the gate electrode of the fifth transistor, and a gate electrode electrically connected to the first control line, and
wherein each of the first and second scan stages includes:
a second transistor including a first electrode electrically connected to a corresponding previous carry line, a second electrode electrically connected to a Q node, and a gate electrode electrically connected to the first electrode of the second transistor;
a ninth transistor including a first electrode electrically connected to a carry clock line, a second electrode electrically connected to a corresponding carry line, and a gate electrode electrically connected to the Q node;
a first transistor including a first electrode electrically connected to a scan clock line, a second electrode electrically connected to a corresponding scan line, and a gate electrode electrically connected to the Q node;
a sixth transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the Q node, and a gate electrode electrically connected to a third control line;
a twenty-fifth transistor including a first electrode electrically connected to a fifth control line, a second electrode, and a gate electrode electrically connected to the fifth control line; and
a twenty-sixth transistor including a first electrode electrically connected to the fifth control line, a second electrode electrically connected to a QB node, and a gate electrode electrically connected to the second electrode of the twenty-fifth transistor.
1 (rearranged). A scan driver comprising:
a plurality of scan stages,
see the first and ninth transistors below
see the third and fifth transistors below
see the fourth and nineteenth transistors below
wherein a first scan stage among the plurality of scan stages comprises:
a fifth transistor having a gate electrode connected to another electrode of the fourth transistor, one electrode connected to a second control line, and another electrode connected to a first node;
a first capacitor having one electrode connected to the one electrode of the fifth transistor, and another electrode connected to the gate electrode of the fifth transistor; and
a third transistor having a gate electrode connected to a first sensing carry line and one electrode connected to a second sensing carry line;
a second transistor having a gate electrode and one electrode connected to a first scan carry line, and another electrode connected to the first Q node;
see claim 4
a first transistor having a gate electrode connected to a first Q node, one electrode connected to a first scan clock line, and another electrode connected to a first scan line;
a sixth transistor having a gate electrode connected to a third control line, one electrode connected to the first node, and another electrode connected to the first Q node.
a fourth transistor having a gate electrode connected to a first control line, and one electrode connected to another electrode of the third transistor;
see claim 11
see claim 11
14. The scan driver of claim 13, wherein the third transistor includes:
a fifth sub-transistor including a gate electrode electrically connected to the first control line and a first electrode electrically connected to the previous carry line; and
a sixth sub-transistor including a gate electrode electrically connected to the first control line, a first electrode electrically connected to a second electrode of the fifth sub-transistor, and a second electrode electrically connected to the gate electrode of the fifth transistor, and
wherein each of the stage groups further includes:
a twenty-ninth transistor including a gate electrode electrically connected to the second electrode of the sixth sub-transistor, a first electrode electrically connected to the first electrode of the sixth sub-transistor, and a second electrode electrically connected to the second control line.
Takasugi: elements Ta and Tb in figure 5 and ¶ 59
13. The scan driver according to claim 12, wherein … the first scan stage further comprises:
a twenty-ninth transistor having a gate electrode connected to the other electrode of the fourth transistor, one electrode connected to the one electrode of the fourth transistor, and another electrode connected to the second control line.
15. The scan driver of claim 13, wherein each of the first and second scan stages further includes:
a thirteenth transistor including a first electrode electrically connected to the corresponding carry line, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a QB node of the first scan stage; and
a fourteenth transistor including a first electrode electrically connected to the corresponding carry line, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a QB node of the second scan stage.
7. The scan driver according to claim 6, wherein the first scan stage further comprises:
a thirteenth transistor having a gate electrode connected to the first QB node, one electrode connected to the first carry line, and another electrode connected to the first power line;
a fourteenth transistor having a gate electrode connected to the second QB node, one electrode connected to the first carry line, and another electrode connected to the first power line; …
16. The scan driver of claim 13, wherein each of the first and second scan stages further includes:
a second capacitor electrically connected between the Q node and the corresponding scan line;
a seventeenth transistor including a first electrode electrically connected to the corresponding scan line, a second electrode electrically connected to a second power line, and a gate electrode electrically connected to a QB node of the first scan stage; and
an eighteenth transistor including a first electrode electrically connected to the corresponding scan line, a second electrode electrically connected to the second power line, and a gate electrode electrically connected to a QB node of the second scan stage.
4. The scan driver according to claim 2, wherein the first scan stage further comprises:
a second capacitor having one electrode connected to the gate electrode of the first transistor and another electrode connected to the other electrode of the first transistor; …
7. The scan driver according to claim 6, wherein the first scan stage further comprises: …
a seventeenth transistor having a gate electrode connected to the first QB node, one electrode connected to the first scan line, and another electrode connected to the second power line; and
an eighteenth transistor having a gate electrode connected to the second QB node, one electrode connected to the first scan line, and another electrode connected to the second power line.
17. The scan driver of claim 13, wherein each of the first and second scan stages further includes:
an eleventh transistor including a first electrode electrically connected to the Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a QB node of the first scan stage;
a twelfth transistor including a first electrode electrically connected to the Q node, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a QB node of the second scan stage;
a twenty-first transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the QB node, and a gate electrode electrically connected to a corresponding QB node of one of the first and second scan stages; and
a twenty-second transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the corresponding QB node, and a gate electrode electrically connected to the corresponding previous carry line.
6. The scan driver according to claim 5, wherein the first scan stage further comprises:
an eleventh transistor having a gate electrode connected to a first QB node, one electrode connected to the first Q node, and another electrode connected to the first power line; and
a twelfth transistor having a gate electrode connected to a second QB node, one electrode connected to the first Q node, and another electrode connected to the first power line.
9. The scan driver according to claim 8, wherein the first scan stage further comprises: …
a twenty-first transistor having a gate electrode connected to the first Q node, one electrode connected to the first power line, and another electrode connected to the first QB node; and
a twenty-second transistor having a gate electrode connected to the first scan carry line, one electrode connected to the first power line, and another electrode connected to the first QB node.
18. The scan driver of claim 13, wherein each of the first and second scan stages further includes:
a twenty-seventh transistor including a first electrode electrically connected to the second electrode of the twenty-fifth transistor, a second electrode electrically connected to a third power line, and a gate electrode electrically connected to the Q node of the first scan stage; and
a twenty-eighth transistor including a first electrode electrically connected to the second electrode of the twenty-fifth transistor, a second electrode electrically connected to the third power line, and a gate electrode electrically connected to the Q node of the second scan stage.
12. The scan driver according to claim 11, wherein the first scan stage further comprises:
a twenty-seventh transistor having a gate electrode connected to the first Q node, one electrode connected to the gate electrode of the twenty-sixth transistor, and another electrode connected to a third power line; and
a twenty-eighth transistor having a gate electrode connected to a second Q node, one electrode connected to the gate electrode of the twenty-sixth transistor, and another electrode connected to the third power line.
19. The scan driver of claim 13, wherein each of the first and second scan stages further includes:
a twenty-third transistor including a first electrode electrically connected to a first power line, a second electrode, and a gate electrode electrically connected to the gate electrode of the fifth transistor;
a twenty-fourth transistor including a first electrode electrically connected to the second electrode of the twenty-third transistor, a second electrode electrically connected to a QB node, and a gate electrode electrically connected to the third control line
a tenth transistor including a first electrode electrically connected to the Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a next carry line; and
a twentieth transistor including a first electrode electrically connected to the Q node, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a fourth control line.
10. The scan driver according to claim 9, wherein the first scan stage further comprises:
a twenty-third transistor having a gate electrode connected to the other electrode of the fourth transistor, and one electrode connected to the first power line; and
a twenty-fourth transistor having a gate electrode connected to the third control line, one electrode connected to another electrode of the twenty-third transistor, and another electrode connected to the first QB node.
5. The scan driver according to claim 4, wherein the first scan stage further comprises
a tenth transistor having a gate electrode connected to a first reset carry line, one electrode connected to the first Q node, and another electrode connected to a first power line.
9. The scan driver according to claim 8, wherein the first scan stage further comprises:
a twentieth transistor having a gate electrode connected to the fourth control line, one electrode connected to the first Q node, and another electrode connected to the first power line; …
20. The scan driver of claim 13, wherein
the second transistor includes a first sub-transistor electrically connected between the corresponding previous carry line and a third node and a second sub-transistor electrically connected between the third node and the Q node,
wherein each of the first and second scan stages further includes a seventh transistor including a gate electrode electrically connected to the Q node, a first electrode electrically connected to the second control line, and a second electrode electrically connected to the third node.
Takasugi: elements T1 and T1a in figure 5 and ¶ 86
2. The scan driver according to claim 1, wherein the first scan stage further comprises
a seventh transistor having a gate electrode connected to the first Q node, one electrode connected to the second control line, and another electrode connected to the first node.
Allowable Subject Matter
Claims 1-4, 6-17, 19, and 20 would be allowable if rewritten or amended to overcome the Double Patenting rejections set forth in this Office action, or upon the filing of at least one proper Terminal Disclaimer cumulatively listing every US Patent and US Application forming the basis of the Double Patenting rejections set forth in this Office action. See MPEP §§ 804.02(II) and 804.02(IV).
Claims 5 and 18 would be allowable if rewritten to overcome the Double Patenting rejections set forth in this Office action or upon the filing of at least one proper Terminal Disclaimer cumulatively listing every US Patent and US Application forming the basis of the Double Patenting rejections set forth in this Office action, and to include all of the limitations of the base claim and any intervening claims. See MPEP §§ 804.02(II) and 804.02(IV).
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, either alone or in combination, fails to teach or fairly suggest:
a. In claim 1, where “the first scan stage includes: … a nineteenth transistor electrically connected to the gate electrode of the fifth transistor and including a gate electrode electrically connected to the fourth control line”, in combination with all the remaining limitations in each claim. See also section 10b in the Office action mailed 09 July 2021 in parent application 16/941,140.
b. In claims 5 and 18, where “the first and second scan stages further includes: …a twenty-eighth transistor including a first electrode electrically connected to the second electrode of the twenty-fifth transistor, a second electrode electrically connected to the third power line, and a gate electrode electrically connected to the Q node of the second scan stage”, in combination with all the remaining limitations in each claim and all the limitations in the claim from which each depends.
c. In claim 13, where “wherein each of the first and second scan stages includes: … a twenty-fifth transistor including a first electrode electrically connected to a fifth control line, a second electrode, and a gate electrode electrically connected to the fifth control line; and a twenty-sixth transistor including a first electrode electrically connected to the fifth control line, a second electrode electrically connected to a QB node, and a gate electrode electrically connected to the second electrode of the twenty-fifth transistor”, in combination with all the remaining limitations in the claim.
d. Claims 2-4, 6-12, 14-17, 19, and 20 would be allowable based on their dependence from one of claims 1 and 13.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
a. Park et al (US 2020/0193912) disclose a shift register circuit in which a QB node (N2) is connected to a reference voltage by a control signal (see at least elements T6 and T7 in figure 3), but does not disclose the details of the claimed twenty-eighth transistor.
Closing Remarks/Comments
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/NATHAN DANIELSEN/Primary Examiner, Art Unit 2622