ADAPTING A LOG-LIKELIHOOD RATIO TO A CODEWORD USING A MACHINE LEARNING MODEL

DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This is a NON-FINAL OFFICE ACTION in response to the present Application filed 03/19/2025. Claims 1-20 are pending in the Application, of which Claims 1, 9 and 17 are independent. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by WANG et al. (PgPub. US 20220231706) Pub. Date: 2022-07-21. Regarding independent Claims1, 9 and 17, WANG discloses Estimation of read parameters for a read channel of a solid-state storage device using a machine learning apparatus, comprising: a processing device, operatively coupled with the memory device, configured to perform operations; [0026] In some embodiments, exemplary error recovery techniques are provided that process inputs to a machine learning apparatus to determine read parameters comprising (i) LLR values, and/or (ii) reference threshold voltage values for the codeword to be read from the storage device as discussed further below. The machine learning apparatus may comprise any appropriate machine learning module executed by a processor. performing a read operation on the memory device to determine a codeword; [0027] FIG. 1 illustrates an example read channel 100 for a solid-state memory device. The read channel 100 may include a reference threshold voltage value estimator 102. The reference threshold voltage value estimator 102 may estimate a reference threshold voltage value or “V.sub.ref” 104 for a memory cell to be read by the read channel 100. In any regard, the reference threshold voltage value V.sub.ref 104 may be applied by a read module 106 to obtain hard bit information in a read bit sequence 106 composed of 0s and 1s from the memory cell. generating, from the read operation, a set of count values representing respective characteristics associated with the codeword; [0029] However, even an optimal reference threshold voltage value V.sub.ref 104 does not always eliminate erroneous bits (errors) in the bit sequence 108. As such, an ECC, such as a LDPC code, is usually applied to the bit sequence 108 to correct any remaining errors in the bit sequence 108. To improve performance of the ECC, the raw bit sequence 108 may be first mapped into a log likelihood ratio (LLR) sequence 116 by a LLR mapping module 110, which is then passed into the ECC decoder 118 for recovery of recovered bits 120. providing the set of count values as an input to a log-likelihood ratio (LLR) estimator machine learning (ML) model; and receiving an output from the LLR estimator ML model; [0039] In FIG. 5, a machine learning apparatus 500 receives multiple inputs 502 to estimate LLR values 504. As way of illustration and not limitation, such inputs 502 may include signal count metrics as described above, syndrome weights as described above, read/write temperature, page number, program/erase cycle, data retention time, page type, etc. In any regard, the inputs 502 are passed through the machine learning apparatus 502 which generates the estimation of LLR values 504 for the memory to be read. performing an error correction code (ECC) operation on the codeword using the LLR output. [0029] FIG. 1,The LLR values 114 generally indicate the confidence levels of the input bits from the bit sequence 108. In an example, the LLR values 114 may comprise a look up table (LUT) that may be provided with corresponding LLR values 114 to the LLR mapping module 110. The choice of the LLR values 114 can greatly impact the ECC decoding performance of the ECC decoder 118. Regarding Claims 2, 10,18, WANG discloses updating a count of memory cells for a plurality of bins based on hard bit read information and soft bit read information. [0057] FIG. 15. The operations 1500 may include a mapping operation 1504 in which hard data read in the read operation 1502 is mapped to default LLR values in a default LLR LUT. In turn, a LLR sequence may be provided to an ECC decoder which may perform a decoding operation 1506. [0059] If the determining operation 1514 determines that the soft decoding operation 1512 fails, the operation 1500 may include an obtaining operation 1516 in which the metrics for use as input to a machine learning apparatus are obtained. This may include collecting signal count metrics for regions in the signal space of the memory as described above. Regarding Claims 3, 11, WANG discloses the ECC operation comprises a low density parity check (LDPC) operation. [0029] However, even an optimal reference threshold voltage value V.sub.ref 104 does not always eliminate erroneous bits (errors) in the bit sequence 108. As such, an ECC, such as a LDPC code, is usually applied to the bit sequence 108 to correct any remaining errors in the bit sequence 108. Regarding Claims 4, 5, 12, 13, 19, WANG discloses an LLR mapper with the LLR output, wherein the LLR field corresponds to the codeword; retrieving the LLR output from the LLR mapper in performing the ECC operation. [0029] To improve performance of the ECC, the raw bit sequence 108 may be first mapped into a log likelihood ratio (LLR) sequence 116 by a LLR mapping module 110, which is then passed into the ECC decoder 118 for recovery of recovered bits 120. The LLR mapping module 110 may, for example, utilize LLR values 114 provided by an LLR value estimator 112. The LLR values 114 generally indicate the confidence levels of the input bits from the bit sequence 180. In an example, the LLR values 114 may comprise a look up table (LUT) that may be provided with corresponding LLR values 114 to the LLR mapping module 110. The choice of the LLR values 114 can greatly impact the ECC decoding performance of the ECC decoder 118. Regarding Claims 6-8, 14-16, 20, WANG discloses LLR estimator ML model comprises a multi-layer neural network; and set of count values [0042] As shown in FIG. 7, a fully connected feedforward neural network 700 is illustrated. The neural network 700 includes N input nodes 702. The neural network 700 also includes M output nodes 704. The neural network 700 may also include a hidden layer 706. The hidden layer comprises various hidden layers 706 each comprising hidden nodes. In this example, a first hidden layer 708, a second hidden layer 710, and a third hidden layer 712 are provided with H.sub.1, H.sub.2, and H.sub.3 hidden nodes, respectively. [0039] In FIG. 5, a machine learning apparatus 500 receives multiple inputs 502 to estimate LLR values 504. As way of illustration and not limitation, such inputs 502 may include signal count metrics “count values” as described above, syndrome weights as described above, read/write temperature, page number, program/erase cycle, data retention time, page type, etc. Prior Art References Cited The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAMES C KERVEROS/Primary Examiner, Art Unit 2111 Date: September 18, 2026 Non-Final Rejection 20260918 JAMES C. KERVEROS Primary Examiner, Art Unit 2111 James.Kerveros@USPTO.GOV