DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statements (IDS) submitted on December 11, 2025 and March 26, 2026 have been fully considered by the examiner.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claims 22 and 25-28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 22 recites the limitation “a plurality of second conductive pads” in lines 2-3, which is indefinite. For the purposes of this action, the aforementioned limitation shall be interpreted as “[[a]] the plurality of second conductive pads,” which find antecedent basis in claim 20, line 3.
Claim 25 recites the limitation “the result of the read operation” in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purposes of this action, the aforementioned limitation shall be interpreted as “[[the]] a result of the read operation”
Claim 26 recites the limitation “the second process node” in line 5. There is insufficient antecedent basis for this limitation in the claim. For the purposes of this action, lines 4-5 of the claim shall be interpreted as, “a control chip comprising a control circuit made at a second process node, wherein the first process node is more advanced than the second process node.” Claims 27-28 depend on claim 26.
Claim 28 is unclear as written. Examiner believes the lack of clarity may be related to using the word “comprising” where perhaps “comprises” was intended. For the purposes of this action, the claim shall be interpreted as: “The method of claim 27, wherein performing [[a]] the write operation on the memory cell after the read operation comprises performing a writing operation on the memory cell after the read operation only if the data to be written does not match the result of the read operation.”
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. Claims 1, 4-10, 16-18, and 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu, et al (US 20230083903 A1), hereinafter Hsu, in view of Yu, et al (US 20240389363 A1), hereinafter Yu.
Regarding independent claim 1, Hsu teaches a memory device, comprising:
a memory chip (FIG. 2B, 201; ¶[0063]), comprising a plurality of memory cells (FIG. 4J) made at a first process node (¶[0061] teaches different processes for fabricating the memory dies from those used in fabricating the control die); and
a control chip (FIG. 2B, Control Die 211) comprising a control circuit (FIG. 2B, e.g., System Control Logic 260) made at a second process node (¶[0061] teaches different processes for fabricating the memory dies from those used in fabricating the control die);
wherein the control chip and the memory chip are bonded together to form the memory device (FIG. 2D; ¶[0069] teaches “Each control die 211 is affixed (e.g., bonded) to at least one of the memory dies 201”), and the control circuit is configured to control an operation of the plurality of the memory cells in the memory chip (¶[0050] teaches “system control logic 260 (which comprises one or more electrical circuits) include state machine 262 that provides die-level control of memory operations”).
Hsu does not explicitly teach the first process node is more advanced than the second process node.
Yu teaches the first process node is more advanced than the second process node (¶[0115] teaches “the memory cells MC is formed using a more advanced technology node than the peripheral device elements”).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Yu into the method of Hsu to include a more advanced process node in the memory die than in the peripheral (control) die. The ordinary artisan would have been motivated to modify Hsu in the above manner for the purpose of individual optimization and lowering manufacturing costs (Yu ¶[0115]).
Regarding claim 4, Hsu as modified by Yu teaches the limitations of claim 1.
Hsu further teaches the control circuit further comprises a decoder (FIG. 2B, row decoder 222) configured to control a word line (FIG. 2B, WLs 208; ¶[0049]) for a memory cell.
Regarding claim 5, Hsu as modified by Yu teaches the limitations of claim 4.
Hsu further teaches the memory chip does not comprise a decoder configured to control a word line for a memory cell (¶[0065] teaches “moving such circuits from a die such as memory 2 die 201 may reduce the number of steps needed to fabricate such a die, adding such circuits to a die such as control die”).
Regarding claim 6, Hsu as modified by Yu teaches the limitations of claim 1.
Hsu further teaches the control circuit further comprises a sense amplifier configured to amplify a signal from a memory cell (FIG. 2B, Sense Amp(s) 230).
Regarding claim 7, Hsu as modified by Yu teaches the limitations of claim 1.
Hsu further teaches the control circuit further comprises a charge pump configured to generate voltage required to program a memory cell (¶[0061] teaches “elements such sense amplifier circuits, charge pumps, logic elements in a state machine, and other peripheral circuitry in system control logic 260,” which is shown in Control Die 211 in FIG. 2B).
Regarding claim 8, Hsu as modified by Yu teaches the limitations of claim 1.
Hsu further teaches the control chip further comprises a processor (FIG. 2B, 262; ¶[0067]; FIG. 3, 330).
Regarding claim 9, Hsu as modified by Yu teaches the limitations of claim 1.
Hsu further teaches the control chip further comprises an analog circuit (e.g., analog circuit of FIG. 13; ¶[0165] teaches “sense amplifier circuit of FIG. 13 can correspond to the sense amp(s) 230 of FIG. 2A or 2B”).
Regarding claim 10, Hsu as modified by Yu teaches the limitations of claim 1.
Hsu further teaches the control chip further comprises a transmitter (¶[0050] of the present application teaches “transmitter 311 may transmit communication signals”; Hsu ¶[0048] teaches “transmitting data to and receiving data from one or more memory die” (written from the perspective of the Memory Controller, which means from the perspective of Control Die Interface 268 in FIG. 2B, transmitting data to and receiving data from the Memory Controller)).
Regarding claim 16, Hsu as modified by Yu teaches the limitations of claim 1.
Hsu further teaches each memory cell comprises a memory element formed above a substrate (e.g., FIG. 4C, memory cells shown formed above substrate 453).
Regarding claim 17, Hsu as modified by Yu teaches the limitations of claim 16.
Hsu further teaches the memory element is selected from a group consisting of:
a Resistive Random Access Memory (RRAM);
a Conductive-Bridge Random Access Memory (CBRAM);
a Magnetic Random Access Memory (MRAM);
a Ferroelectric Random Access Memory (FeRAM); and
a Phase Change Random Access Memory (PCRAM) (¶[0062] teaches “a memory die can be formed of just the memory elements, such as the array of memory cells of flash NAND memory, MRAM memory, PCM memory, ReRAM”).
Regarding claim 18, Hsu as modified by Yu teaches the limitations of claim 1.
Hsu further teaches each memory cell comprises a resistive memory element formed above a substrate (¶[0062] teaches “the memory structure 202 can be formed on one die (referred to as the memory die)” and “a memory die can be formed of just the memory elements, such as the array of memory cells of flash NAND memory, MRAM memory, PCM memory, ReRAM”; see also ¶[0055-0058]).
Regarding claim 20, Hsu as modified by Yu teaches the limitations of claim 18.
Hsu further teaches a top surface of the memory chip comprises a plurality of first conductive pads and a top surface of the control chip comprises a plurality of second conductive pads (FIG. 2D shows surfaces of memory dies 201 and control dies 211 comprise a plurality of conductive bond pads 282 and 284; ¶[0074]).
Yu further teaches a top surface of the memory chip comprises a first insulating region (FIG. 1D, thermal insulating layer 117; ¶[0030] teaches layer 117 may be a known insulator such as boron nitride or diamond) and a top surface of the control chip comprises a second insulating region (FIG. 1D, thermal insulating layer 144; ¶[0065] teaches layer 144 may be a known insulator such as boron nitride or diamond).
Regarding claim 21, Hsu as modified by Yu teaches the limitations of claim 20.
Yu further teaches a first conductive pad (FIG. 1D, bonding pads 118; ¶[0014]) is bonded to a second conductive pad (FIG. 1D, bonding pads 145; ¶[0049]), and the first insulating region is bonded to the second insulating region (¶[0048] teaches “an intermediate chip structure 140 is bonded to the cell chip structure 130 through dielectric-to-dielectric bonding”).
Regarding claim 22, Hsu as modified by Yu teaches the limitations of claim 20.
Yu further teaches the plurality of first conductive pads are connected to a second metal layer in the memory chip by a plurality of memory chip vias (referencing FIGS. 1A-1F, ¶[0022] teaches “conductive vias 116 are electrically connected between the wiring layers 115, the device elements 112 and 113, and the bonding pads 118”), and a plurality of second conductive pads are connected to a second metal layer in the control chip by a plurality of control chip vias (referencing FIG. 1D, ¶[0060] teaches “conductive vias 143c are electrically connected between the wiring layers 143b, the device elements 142, and the bonding pads 145”), wherein the plurality of memory chip vias comprise a same length (e.g., FIG. 1B, memory conductive vias 122 are illustrated having a same length).
7. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu, et al (US 20230083903 A1), hereinafter Hsu, in view of Yu, et al (US 20240389363 A1), hereinafter Yu, and further in view of Oowada, et al (US 20230128177 B1), hereinafter Oowada.
Regarding claim 11, Hsu as modified by Yu teaches the limitations of claim 1.
Hsu does not teach the control chip further comprises a sensor.
Oowada teaches the control chip further comprises a sensor (FIG. 2B, Temperature sensor 228).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Oowada into the method of Hsu to include a temperature sensor on the peripheral (control) chip. The ordinary artisan would have been motivated to modify Hsu in the above manner for the purpose of applying the positive Tco voltage to the control terminal of a dummy select transistor during program operations helps to maintain the Vt of the dummy select transistors (Oowada ¶[0031]).
8. Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu, et al (US 20230083903 A1), hereinafter Hsu, in view of Yu, et al (US 20240389363 A1), hereinafter Yu, and further in view of Sutardja, et al (US 9275731 B1), hereinafter Sutardja.
Regarding claim 13, Hsu as modified by Yu teaches the limitations of claim 1.
Hsu further teaches the control chip comprises a plurality type of transistors (¶[0061] teaches “the peripheral circuitry is often CMOS based,” which includes both PMOS and NMOS).
Hsu does not teach the memory chip comprises only one type of transistors.
Sutardja teaches the memory array comprises only one type of transistors (FIG. 2 shows NMOS transistors; Col. 3, l. 25).
Yu further teaches the memory chips have only the memory cell array (¶[0114]).
Therefore, Hsu as modified by Yu and Sutardja teaches the memory chip comprises only one type of transistors.
Regarding claim 14, Hsu as modified by Yu teaches the limitations of claim 13.
Hsu does not teach the memory chip comprises only NMOS transistors.
Sutardja teaches the memory array comprises only NMOS transistors (FIG. 2 shows NMOS transistors; Col. 3, l. 25).
Yu further teaches the memory chips have only the memory cell array (¶[0114]).
Therefore, Hsu as modified by Yu and Sutardja teaches the memory chip comprises only NMOS transistors.
Regarding claim 15, Hsu as modified by Yu teaches the limitations of claim 13.
Hsu does not teach the memory chip comprises only PMOS transistors.
Sutardja teaches the memory array comprises only PMOS transistors (Referencing FIG. 2, Col. 3, ll. 21-24 teaches “As can be appreciated, while the transistors T.sub.1, T.sub.2, . . . and T.sub.R are shown as NMOS transistors, PMOS transistors or other types of access devices may be used”).
Yu further teaches the memory chips have only the memory cell array (¶[0114]).
Therefore, Hsu as modified by Yu and Sutardja teaches the memory chip comprises only PMOS transistors.
Regarding claim 13-15, because both Hsu and Sutardja teach a die including a resistive RAM memory array (Hsu ¶[0055-0056], [0062]; Sutardja FIGS. 2-3), it would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the resistive RAM array of Sutardja with the resistive RAM array of Hsu to yield predictable results. See MPEP § 2143(I)(B).
9. Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu, et al (US 20230083903 A1), hereinafter Hsu, in view of Yu, et al (US 20240389363 A1), hereinafter Yu, and further in view of Yang, et al (US 20190067373 A1), hereinafter Yang.
Regarding claim 19, Hsu as modified by Yu teaches the limitations of claim 18.
Hsu does not teach the memory cell comprises:
an access transistor formed on the substrate.
Yang teaches the memory cell comprises:
an access transistor formed on the substrate (FIGS. 1, 4, 8a, 112);
Yang further teaches in FIG. 4 a contact (412 coupled to 112 in region 404);
a first metal layer (lower metal layer 414);
a bottom electrode (106a);
the resistive memory element (storage layer 108a);
a first via (416); and
a second metal layer (upper metal layer 414);
wherein the contact is disposed between a terminal of the access transistor (contact is shown coupled to 112 drain region 204a) and the first metal layer (lower metal layer 414 in region 404), the bottom electrode is disposed between the first metal layer and the resistive memory element (electrode 106a is shown between first metal layer and data storage layer 108a), the first via is disposed between the resistive memory element and the second metal layer (via 216a is shown between upper metal layer 414 in region 404 and electrode 110a coupled to storage layer 108a).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Yang into the method of Hsu to include an access transistor coupled to an RRAM cell. The ordinary artisan would have been motivated to modify Hsu in the above manner for the purpose of controlling Forming, Set, Reset, and Read operations (Yang, FIG. 8B; ¶[0052]).
10. Claims 23-25 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu, et al (US 20230083903 A1), hereinafter Hsu, in view of Yu, et al (US 20240389363 A1), hereinafter Yu, and further in view of Balakrishnan, et al (US 20140269106 A1), hereinafter Balakrishnan.
Regarding claim 23, Hsu as modified by Yu teaches the limitations of claim 1.
Hsu does not teach prior to performing a write operation to a memory cell, the control circuit is configured to perform a read operation on the memory cell.
Balakrishnan teaches prior to performing a write operation to a memory cell, the control circuit (FIG.12, 130; ¶[0097]) is configured to perform a read operation on the memory cell (FIG. 13; ¶[0101] teaches “At step 404, the memory system initiates a read before write operation 424 prior to beginning the write operation”).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Balakrishnan into the method of Hsu to include an evaluation of whether to skip programming of portions of groups of memory cells during a read before write operation. The ordinary artisan would have been motivated to modify Hsu in the above manner for the purpose of expediting the write operation (Balakrishnan Abstract).
Regarding claim 24, Hsu as modified by Yu and Balakrishnan teaches the limitations of claim 23.
Balakrishnan further teaches prior to performing a write operation to a memory cell, the control circuit is configured to compare data to be written with a result of a read operation (FIG. 13; ¶[0100] teaches “At step 402, a request to write data to the memory system is received. In one example, the request includes or is provided with the data to be written.” ¶[0102] teaches “the state machine can compare each memory data bit read from the memory array with the corresponding user data bit received at step 402”).
Regarding claim 25, Hsu as modified by Yu and Balakrishnan teaches the limitations of claim 23.
Balakrishnan further teaches the control circuit is configured to perform the write operation only if the data to be written does not match the result of the read operation (¶[0102] teaches “At step 406, the state machine can compare each memory data bit read from the memory array with the corresponding user data bit received at step 402. If the two bits match, the state machine generates and stores SAD skip information indicating that the SAD cycle can be skipped. If the two bits do not match, the state machine generates and stores SAD skip information indicating that the SAD cycle should not be skipped.” ¶[0096] teaches “a memory system and method are provided that enable an evaluation of whether to skip programming of portions of group of memory cells during a read before write operation” and “Skip evaluations in different embodiments may be performed for entire BAD cycles, CAD cycles and/or SAD cycles.”).
11. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu, et al (US 20230083903 A1), hereinafter Hsu, in view of Yu, et al (US 20240389363 A1), hereinafter Yu, and further in view of Chung, et al (US 20230299109 A1), hereinafter Chung.
Regarding claim 12, Hsu as modified by Yu teaches the limitations of claim 1.
Hsu does not teach a gate length of a transistor in the memory chip is smaller than a gate length of a transistor in the control chip.
Chung teaches in ¶[0044] “a bigger technology node may sometimes be referred to as a longer channel or gate length. Similarly, a smaller technology node may sometimes be referred to as a shorter channel or gate length.”
Yu teaches the first process node is more advanced than the second process node (¶[0115] teaches “the memory cells MC is formed using a more advanced technology node than the peripheral device elements”).
Therefore, Yu together with Chung teaches the memory chip, which is a smaller (more advanced) technology node, has a shorter gate length than a gate length of a transistor in the control chip.
11. Claims 26-28 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu, et al (US 20230083903 A1), hereinafter Hsu, in view of Balakrishnan, et al (US 20140269106 A1), hereinafter Balakrishnan.
Regarding independent claim 26, Hsu teaches a method for performing a write operation in a memory device (e.g., FIG. 6), wherein the memory device comprises a memory chip (FIG. 2B, 201; ¶[0063]) comprising a plurality of memory cells (FIG. 4J) made at a first process node (¶[0061] teaches different processes for fabricating the memory dies from those used in fabricating the control die); and
a control chip (FIG. 2B, Control Die 211) comprising a control circuit (FIG. 2B, e.g., System Control Logic 260) made at a second (¶[0061] teaches different processes for fabricating the memory dies from those used in fabricating the control die);
wherein the control chip and the memory chip are bonded together to form the memory device (FIG. 2D; ¶[0069] teaches “Each control die 211 is affixed (e.g., bonded) to at least one of the memory dies 201”), and the control circuit is configured to control an operation of the plurality of the memory cells in the memory chip (¶[0050] teaches “system control logic 260 (which comprises one or more electrical circuits) include state machine 262 that provides die-level control of memory operations”).
Hsu does not teach the method comprising:
receiving an address of a memory cell in the memory chip and data to be written to the memory cell by the control chip;
performing a read operation on the memory cell; and
performing a write operation on the memory cell after the read operation.
Balakrishnan teaches the method comprising:
receiving an address of a memory cell in the memory chip and data to be written to the memory cell by the control chip (FIG. 13; ¶[0100] teaches “At step 402, a request to write data to the memory system is received. In one example, the request includes or is provided with the data to be written.” ¶[0102] teaches “the state machine can compare each memory data bit read from the memory array with the corresponding user data bit received at step 402”).
performing a read operation on the memory cell (FIG. 13; ¶[0101] teaches “At step 404, the memory system initiates a read before write operation 424 prior to beginning the write operation”); and
performing a write operation on the memory cell after the read operation (FIG. 13, 414; ¶[0102] teaches “Step 412 includes writing the user data to the memory array using the bitmap data generated at steps 406-410,” which includes a read).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Balakrishnan into the method of Hsu to include performing a write operation on the memory cell after the read operation (read before write). The ordinary artisan would have been motivated to modify Hsu in the above manner for the purpose of evaluating skip information during a read before write operation so the write operation can be expedited (Balakrishnan Abstract).
Regarding claim 27, Hsu as modified by Balakrishnan teaches the limitations of claim 26.
Balakrishnan further teaches comparing the data to be written with a result of the read operation before performing the write operation on the memory cell (FIG. 13; ¶[0100] teaches “At step 402, a request to write data to the memory system is received. In one example, the request includes or is provided with the data to be written.” ¶[0102] teaches “the state machine can compare each memory data bit read from the memory array with the corresponding user data bit received at step 402”).
Regarding claim 28, Hsu as modified by Balakrishnan teaches the limitations of claim 27.
Balakrishnan further teaches performing a write operation on the memory cell after the read operation comprising performing a writing operation on the memory cell after the read operation only if the data to be written does not match the result of the read operation (¶[0102] teaches “At step 406, the state machine can compare each memory data bit read from the memory array with the corresponding user data bit received at step 402. If the two bits match, the state machine generates and stores SAD skip information indicating that the SAD cycle can be skipped. If the two bits do not match, the state machine generates and stores SAD skip information indicating that the SAD cycle should not be skipped.” ¶[0096] teaches “a memory system and method are provided that enable an evaluation of whether to skip programming of portions of group of memory cells during a read before write operation” and “Skip evaluations in different embodiments may be performed for entire BAD cycles, CAD cycles and/or SAD cycles.”).
12. Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu, et al (US 20230083903 A1), hereinafter Hsu, in view of Yu, et al (US 20240389363 A1), hereinafter Yu, and further in view of Zampaglione (US 5349552 A).
Regarding claim 2, Hsu as modified by Yu teaches the limitations of claim 1.
Hsu further teaches a column control circuitry on a control chip (FIG. 2A, 210) including a column decoder (FIG. 2A, 212) and a bit line selector circuit configured to control a bit line for a memory cell (FIG. 3, 306, 308).
Hsu does not teach the column control circuitry includes a multiplexer.
Zampaglione teaches a column decoder includes a multiplexer (FIG. 1, 10; Col. 1, ll. 32-35).
Therefore, Hsu as modified by Zampaglione teaches the control circuit further comprises a multiplexer configured to control a source line or a bit line for a memory cell.
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Zampaglione into the method of Hsu to include a multiplexer in the column control circuitry. The ordinary artisan would have been motivated to modify Hsu in the above manner for the purpose of selectively accessing a column in the memory cell array so that a cell located at the intersection of an addressed row and column can be selectively accessed (Zampaglione Col. 1, ll. 32-27).
Regarding claim 3, Hsu as modified by Yu and Zampaglione teaches the limitations of claim 2.
Hsu as modified by Zampaglione further teaches the memory chip does not comprise a multiplexer configured to control a source line or a bit line for a memory cell (Hsu as modified by Zampaglione places the bit line multiplexer in the control chip’s column decoder circuitry in claim 2 and there is no need for a duplicate multiplexer in the memory chip).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/ Supervisory Patent Examiner, Art Unit 2827
Prosecution Insights