DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The reference cited in the IDS have been considered by examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SCAN DRIVER AND DISPLAY DEVICE HAVING TRANSISTORS WITH BIAS ELECTRODES ON DIFFERENT LAYERS.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 3-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lai et al (U.S. Patent Pub. No. 2022/0208797).
Regarding claim 1, Lai discloses a display device (000), (fig. 1, [0043]), comprising:
a pixel (40) comprising a light-emitting element (OLED), and a first transistor (i.e. transistor 20 of figure 18 is equivalent to drive transistor M3 of figure 8) configured to supply a driving current to the light-emitting element, (figs. 8 and 18, [0060-0061]);
a scan driver (50) comprising a first oxide transistor (30), and configured to supply a scan signal (scan drive signals) to the pixel (40), (i.e. drive circuit 50 may be a gate drive circuit for providing scan drive signals for the scan lines G of the display panel 000), (fig. 1, [0048-0049]);
a first active layer (201) above a substrate (10), and comprising a first material (polysilicon), (fig. 18, [0049]);
a first gate layer (20G) above the first active layer (201), (fig. 18, [0049]);
a second gate layer (60G2) above the first gate layer (20G), (fig. 18, [0085]); and
a second active layer (601) above the second gate layer (60G2), comprising a second material (i.e. may be amorphous indium gallium zinc oxide) that is different from the first material, and comprising a semiconductor region (i.e. region of active layer 201 is semiconductor) of the first transistor (20) and a semiconductor region (i.e. region of active layer 301 is semiconductor) of the first oxide transistor (30), (fig. 18, [0043 and 0076-0077]),
wherein a bias electrode (20G2) of the first transistor (20) and a bias electrode (30G2) of the first oxide transistor (30) are at different layers, (fig. 18, [0066 and 0068]).
Regarding claim 3, Lai discloses wherein the scan driver (50) further comprises a second oxide transistor (20) comprising a semiconductor region at the second active layer (201), and wherein a bias electrode (20G2) of the second oxide transistor (20) and the bias electrode (30G2) of the first oxide transistor (30) are at different layers, (fig. 13, [0066-0067]).
Regarding claim 4, Lai discloses wherein the bias electrode (20G2) of the second oxide transistor (20) is at the second gate layer, and the bias electrode (30G2) of the first oxide transistor (20) is at the first gate layer, (fig. 13, [0066-0067]).
Regarding claim 5, Lai discloses further comprising a metal layer (20G2) between the substrate (10) and the first active layer (201),
wherein the bias electrode (20G2) of the second oxide transistor (20) is at the first gate layer (i.e. gate layer of gate electrode 20G2), and the bias electrode (30G2) of the first oxide transistor (30) is at the metal layer (i.e. layer of gate electrode 30G2), (fig. 13, [0066-0067]).
Regarding claim 6, Lai discloses further comprising a metal layer (20G2) between the substrate (10) and the first active layer (201), (fig. 13, [0067]),
wherein the bias electrode (20G2) of the first transistor (20) is at the second gate layer, (fig. 18, [0066 and 0068]), and
the bias electrode (30G2) of the first oxide transistor (30) is at the metal layer, (fig. 13, [0066-0067]).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai in view of Park et al (U.S. Patent Pub. No. 2023/0165053; hereinafter referenced as Park’053) and in view of Park et al (U.S. Patent Pub. No. 2020/0321427; hereinafter referenced as Park’427).
Regarding claim 2, Lai discloses everything as specified above in claim 1. However, Lai does not mention the bias electrode of the first transistor is at the second gate layer.
In a similar field of endeavor, Park’053 teaches wherein the bias electrode (BGE) of the first transistor (TFT2) is at the second gate layer (i.e. layer of GE1), (fig. 5, [0119 and 0134]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lai, by specifically providing the bias electrode of the first transistor to be a the second gate layer, as taught by Park’053, for the purpose of reducing a user recognizing the adjacent area, [0008].
However, Lai in view of Park’053 does not mention the bias electrode of the first oxide transistor is at the first gate layer.
In a similar field of endeavor, Park’427 teaches bias electrode (LB1) of the first oxide transistor (TRd) is at the first gate layer (LB2), (fig. 20a, [0318-0320]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lai in view of Park’052, by specifically providing the bias electrode of the first oxide transistor is at the first gate layer, as taught by Park’427, for the purpose of improving image quality, [0007].
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai in view of Kang et al (U.S. Patent Pub. No. 2024/0021165) and in view of Lee et al (U.S. Patent Pub. No. 2023/0146693).
Regarding claim 7, Lai discloses everything as specified above in claim 3. However, Lai does not mention a fifth scan transistor configured to supply a first gate low voltage to an output node for outputting the scan signal based on a voltage of a first scan node.
In a similar field of endeavor, Kang teaches wherein the scan driver (130a), (fig. 7, [0109]), further comprises:
a fifth scan transistor (T7) configured to supply a first gate low voltage (i.e. when clock CLK3 toggles to low power supply voltage VGL2) to an output node (ON2) for outputting the scan signal (EB(k)) based on a voltage of a first scan node (IN2), (figs. 8-9, [0120]);
a sixth scan transistor (T6) configured to supply a first gate high voltage (VGH) to the output node (ON2) based on a voltage of a second scan node (IN3), (figs. 8-9, [0134]);
a third scan transistor (T5) configured to initialize the voltage of the second scan node (IN3) to the first gate low voltage (VGL) based on clock signal CLK1, (figs. 8-9, [0134]);
a second scan transistor (T8) configured to electrically connect the first scan node (IN2) to a third scan node (IN1) based on the first gate low voltage (VGL), (figs. 8-9, [0126]); and
a first scan transistor (T1) configured to supply a start signal (i.e. scan start signal FLM can be applied to node IN(k)) to the third scan node (IN1) based on a first clock signal (CLK1), (figs. 8-9, [0116 and 0126]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lai, by specifically providing the scan driver, as taught by Kang, for the purpose of applying bias voltage so that a high-quality image can be displayed, [0035].
However, Lai in view of Kang does not mention a third scan transistor configured to initialize the voltage of the second scan node to the first gate low voltage based on the voltage of the first scan node.
In a similar field of endeavor, Lee teaches:
a third scan transistor (Tr10) configured to initialize the voltage of the second scan node (Q) to the first gate low voltage (Vin2/Vss2) based on the voltage of the first scan node (Q’), (fig. 3, [0072]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lai in view of Kang, by specifically providing the third scan transistor, as taught by Lee, for the purpose of having a uniform waveform at high temperature output, [0006].
Regarding claim 8, Kang discloses wherein the first oxide transistor is the first scan transistor (T1), and the second oxide transistor is the third scan transistor (T5) (i.e. the transistors T1 and T5 are p-channel metal oxide semiconductors PMOS), (fig. 8, [0085]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lai, by specifically providing the scan driver, as taught by Kang, for the purpose of applying bias voltage so that a high-quality image can be displayed, [0035].
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai in view of Kang in view of Lee and in view of Kim et al (U.S. Patent Pub. No. 2023/0169926; hereinafter referenced as Kim’926).
Regarding claim 9, Kang discloses wherein the scan driver further comprises a seventh scan transistor (T10) for outputting a second gate low voltage (i.e. when clock signal CLK2 is at voltage VGL) as a carry signal (CR(k)) based on the voltage of the first scan node (IN2), (figs. 8-9, [0119 and 0129]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lai, by specifically providing the seventh scan transistor, as taught by Kang, for the purpose of applying bias voltage so that a high-quality image can be displayed, [0035].
However, Lai in view of Kang does not mention the second gate low voltage is lower than the first gate low voltage.
In a similar field of endeavor, Lee teaches the second gate low voltage (Vss2) having an absolute value that is lower than an absolute value of the first gate low voltage (Vss1), (fig. 3, [0057]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lai in view of Kang, by specifically providing second gate low voltage is lower than the first gate low voltage, as taught by Lee, for the purpose of having a uniform waveform at high temperature output, [0006].
However, Lai in view of Kang and in view of Lee does not mention a seventh scan transistor configured to output a second gate low voltage as a carry signal based on the voltage of the second scan node.
In a similar field of endeavor, Kim’926 teaches:
wherein the scan driver (130) further comprises a seventh scan transistor (T9) for outputting a second gate low voltage (VSS1) as a carry signal (CR) based on the voltage of the second scan node (i.e. when node Q is inverted through inverter 133 to node QB), (figs. 4 and 6, [0088, 0104 and 0115]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lai in view of Kang and in view of Lee, by specifically providing the seventh scan transistor, as taught by Kim’926, for the purpose of reducing heat emission, [0005].
Regarding claim 10, Kang discloses wherein the first oxide transistor is the first scan transistor (T7), and the second oxide transistor is the third or seventh scan transistor (T5 or T10), (i.e. the transistors T1, T5 and T10 are p-channel metal oxide semiconductors PMOS), (fig. 8, [0085]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lai, by specifically providing the scan driver, as taught by Kang, for the purpose of applying bias voltage so that a high-quality image can be displayed, [0035].
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai in view of Kim et al (U.S. Patent Pub. No. 2023/0363206; hereinafter referenced as Kim’206).
Regarding claim 11, Lai discloses wherein the pixel (40) further comprises:
a second transistor (M2) configured to supply a data voltage (Vdata);
a third transistor (M5) configured to supply a reference voltage (Vref) to the first node (N1);
a fourth transistor (M7) configured to discharge a first electrode of the light-emitting element (OLED) to an initialization voltage (Vref);
a fifth transistor (M1) configured to supply a driving voltage (PVDD) to a drain electrode of the first transistor (M3); and
a sixth transistor (M6) configured to electrically connect a second node (N3) that is a source electrode of the first transistor (M3) and a third node (N4) that is the first electrode of the light-emitting element (OLED) to each other, (fig. 8, [0061]).
However, Lai does not mention a second transistor configured to supply a data voltage to a first node that is a gate electrode of the first transistor.
In a similar field of endeavor, Kim’206 teaches:
a second transistor (T2) configured to supply a data voltage (DATA) to a first node (N1) that is a gate electrode of the first transistor (T1); and
a fourth transistor (T4) configured to discharge a first electrode of the light-emitting element (OLED) to an initialization voltage (VINT), (fig. 2, [0068-0069 and 0071]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lai, by specifically providing the second transistor, as taught by Kim’206, for the purpose of displaying high quality image, [0005].
Regarding claim 12, Lai discloses wherein a semiconductor region of the second transistor (60) is at the second active layer (601), (fig. 18, [0076]), and
wherein the bias electrode (20G2) of the first transistor (20) and a bias electrode (60G2) of the second transistor (60) are at different layers, (fig. 18, [0068 and 0085]).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai in view of Kim’206 in view of Park’053 and in view of Shin et al (U.S. Patent Pub. No. 2021/0408061).
Regarding claim 13, Lai in view of Kim’206 discloses everything as specified above in claim 11. However, Lai in view of Kim’206 does not mention the bias electrode of the first transistor is at the second gate layer.
In a similar field of endeavor, Park’053 teaches wherein the bias electrode (BGE) of the first transistor (TFT2) is at the second gate layer (i.e. layer of GE1), (fig. 5, [0119 and 0134]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lai in view of Kim’206, by specifically providing the bias electrode of the first transistor to be a the second gate layer, as taught by Park’053, for the purpose of reducing a user recognizing the adjacent area, [0008].
However, Lai in view of Kim’206 and in view of Park’053 does not mention a bias electrode of the second transistor is at the first gate layer.
In as similar field of endeavor, Shin teaches wherein a bias electrode (410) of the second transistor (400) is at the first gate layer (211), (fig. 5, [0091 and 0119]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lai in view of Kim’206 and in view of Park’053, by specifically providing the bias electrode of the second transistor is at the first gate layer, as taught by Shin, for the purpose of improving performance of the display device, [0009].
Claim(s) 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai in view of Kim’206 and in view of Choi et al (U.S. Patent Pub. No. 2024/0071315).
Regarding claim 14, Lai discloses an electronic device comprising a display device (000), (fig. 1, [0043]), comprising:
a light-emitting element (OLED), (fig. 8, [0061]);
a first transistor (i.e. drive transistor M3 of figure 8 is equivalent to transistor 20 of figure 18) configured to supply a driving current to the light-emitting element (OLED);
a second transistor (i.e. transistor M2 of figure 8 is equivalent to transistor 60 of figure 18) configured to supply a data voltage (Vdata);
a third transistor (M5) configured to supply a reference voltage (Vref) to the first node (N1);
a fourth transistor (M7) configured to discharge a first electrode of the light-emitting element (OLED) to a voltage (Vref);
a fifth transistor (M1) configured to supply a driving voltage (PVDD) to a drain electrode of the first transistor (M3);
a sixth transistor (M6) configured to electrically connect a second node (N3) that is a source electrode of the first transistor (M3) and a third node (N4) that is the first electrode of the light-emitting element (OLED) to each other, (figs. 8 and 18, [0060-0061 and 0081]);
a first active layer (201) above a substrate (10);
a first gate layer (20G) above the first active layer (201), (fig. 18, [0049]);
a second gate layer (60G2) above the first gate layer (20G), (fig. 18, [0085]); and
a second active layer (601) above the second gate layer (60G2), and comprising a semiconductor region (i.e. region of active layer 201 is semiconductor) of the first transistor (20) and a semiconductor region (i.e. region of active layer 601 is semiconductor) of the second transistor (60), (fig. 18, [0043 and 0076-0077]),
wherein a bias electrode (20G2) of the first transistor (20) and a bias electrode (60G2) of the second transistor (60) are at different layers, (fig. 18, [0067 and 0085]).
However, Lai does not mention a second transistor configured to supply a data voltage to a first node that is a gate electrode of the first transistor. Furthermore, Lai teaches a fourth transistor (M7) configured to discharge a first electrode of the light-emitting element (OLED) to a reference voltage (Vref), but not to an initialization voltage.
In a similar field of endeavor, Kim’206 teaches:
a second transistor (T2) configured to supply a data voltage (DATA) to a first node (N1) that is a gate electrode of the first transistor (T1); and
a fourth transistor (T4) configured to discharge a first electrode of the light-emitting element (OLED) to an initialization voltage (VINT), (fig. 2, [0068-0069 and 0071]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lai, by specifically providing the second transistor, as taught by Kim’206, for the purpose of displaying high quality image, [0005].
However, Lai in view of Kim’206 does not mention a first active layer above a substrate, and comprising a semiconductor region of the fifth transistor and a semiconductor region of the sixth transistor.
In a similar field of endeavor, Choi teaches
a first active layer (322) above a substrate (110), and comprising a semiconductor region (322) of the fifth transistor (320) and a semiconductor region (332) of the sixth transistor (330), (fig. 6, [0131, 0133-0134 and 0145]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lai in view of Kim’206, by specifically providing the semiconductor regions of the fifth and sixth transistors, as taught by Choi, for the purpose having improved display quality, [0013].
Regarding claim 15, Lai discloses wherein the bias electrode (20G2) of the first transistor (20) is at the second gate layer (i.e. layer of 20G2), and the bias electrode (60G2) of the second transistor (60) is at the first gate layer (i.e. layer of 60G2), and
wherein the display device further comprises a metal layer (20G2) between the substrate (10) and the first active layer (201), (fig. 18, [0067 and 0085]).
However, Lai in view of Kim’206 does not mention a bias electrode of the fifth transistor and a bias electrode of the sixth transistor are at the metal layer.
In a similar field of endeavor, Choi teaches wherein a bias electrode (321) of the fifth transistor (320) and a bias electrode (331) of the sixth transistor (330) are at the metal layer (i.e. layer of light blocking layers 321 and 331), (fig. 6, [0142 and 0146]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lai in view of Kim’206, by specifically providing the semiconductor regions of the fifth and sixth transistors, as taught by Choi, for the purpose having improved display quality, [0013].
Regarding claim 16, Lai discloses wherein the electronic device comprises a mobile phone (111), (fig. 27, [0122]).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Lee in view of Noh et al (U.S. Patent Pub. No. 2024/0194150) in view of Kim’926 and in view of Lai.
Regarding claim 17, Kang discloses a scan driver (130a), (fig. 7, [0109]), comprising:
a fifth scan transistor (T7) configured to supply a first gate low voltage (i.e. when clock CLK3 toggles to low power supply voltage VGL2) to an output node (ON2) based on a voltage of a first scan node (IN2), the output node for outputting a scan signal (EB(k)), (figs. 8-9, [0120]);
a sixth scan transistor (T6) configured to supply a first gate high voltage (VGH) to the output node (ON2) based on a voltage of a second scan node (IN3), (figs. 8-9, [0134]);
a third scan transistor (T5) configured to initialize the voltage of the second scan node (IN3) to the first gate low voltage (VGL) based on clock signal CLK1, (figs. 8-9, [0134]);
a second scan transistor (T8) configured to electrically connect the first scan node (IN2) to a third scan node (IN1) based on the first gate low voltage (VGL), (figs. 8-9, [0126]);
a first scan transistor (T1) configured to supply a start signal (i.e. scan start signal FLM can be applied to node IN(k)) to the third scan node (IN1) based on clock signal CLK1, (figs. 8-9, [0116 and 0126]); and
a seventh scan transistor (T10) configured to output a second gate low voltage (i.e. when clock signal CLK2 is at voltage VGL) as a carry signal (CR(k)) based on the voltage of the first scan node (IN2), (figs. 8-9, [0119 and 0129]).
However, Kang does not mention a third scan transistor configured to initialize the voltage of the second scan node to the first gate low voltage based on the voltage of the first scan node.
In a similar field of endeavor, Lee teaches:
a third scan transistor (Tr10) configured to initialize the voltage of the second scan node (Q) to the first gate low voltage (Vin2/Vss2) based on the voltage of the first scan node (Q’), (fig. 3, [0072]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kang, by specifically providing the third scan transistor, as taught by Lee, for the purpose of having a uniform waveform at high temperature output, [0006].
However, Kang in view of Lee does not mention a first scan transistor configured to supply a start signal to the third scan node based on a second gate high voltage that is lower than the first gate high voltage.
In a similar field of endeavor, Noh teaches:
a first scan transistor (T1) configured to supply a start signal (start pulse Vst) to the third scan node (Qh) based on a second gate high voltage (i.e. when clock CLK is at a high level at VGH2) that is lower than the first gate high voltage (VGH1) (i.e. VGH1>VGH2), (figs. 4-5, [0066 and 0071]),
the second gate low voltage (VGL2) having an absolute value that is lower than an absolute value of the first gate low voltage (VGL1) (i.e. VGL1>VGL2), (fig. 5),
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kang in view of Lee, by specifically providing the first scan transistor, as taught by Noh, for the purpose of having an output loss of a carry signal to be reduced, [0010].
However, Kang in view of Lee and in view of Noh does not mention a seventh scan transistor configured to output a second gate low voltage as a carry signal based on the voltage of the second scan node.
In a similar field of endeavor, Kim’926 teaches:
a seventh scan transistor (T9) configured to output a second gate low voltage (VSS1) as a carry signal (CR) based on the voltage of the second scan node (i.e. when node Q is inverted through inverter 133 to node QB), (fig. 6, [0104 and 0115]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kang in view of Lee in view of Noh, by specifically providing the seventh scan transistor, as taught by Kim’926, for the purpose of reducing heat emission, [0005].
However, Kang in view of Lee in view of Noh and in view of Kim’926 does not mention wherein a bias electrode of the first scan transistor and a bias electrode of the seventh scan transistor are at different layers.
In a similar field of endeavor, Lai teaches wherein a bias electrode (20G2) of the first scan transistor (20) and a bias electrode (30G2) of the seventh scan transistor (30) are at different layers, (fig. 13, [0067 and 0073]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kang in view of Lee in view of Noh and in view of Kim’926, by specifically providing the bias electrodes, as taught by Lai, for the purpose of improving the display effect, [0124].
Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Lee in view of Noh in view of Kim’926 in view of Lai and in view of Park’427.
Regarding claim 18, Lai discloses further comprising:
a first active layer (201) above a substrate (10), and comprising a semiconductor region (i.e. active layer 201 is a semiconductor region) of the first scan transistor (20), (fig. 13, [0066-0067]);
a first gate layer (20G) above the first active layer (201), (fig. 13, [0067]);
a second gate layer (30G2) above the first gate layer (20G), (fig. 13, [0073]); and
a second active layer (301) above the second gate layer (30G2), and comprising a semiconductor region (i.e. active layer 201 is a semiconductor) of the first scan transistor (20) and a semiconductor region (i.e. active layer 301 is a semiconductor) of the seventh scan transistor (30), (fig. 13, [0073]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kang in view of Lee in view of Noh and in view of Kim’926, by specifically providing the active layers, as taught by Lai, for the purpose of improving the display effect, [0124].
However, Kang in view of Lee in view of Noh in view of Kim’926 and in view of Lai does not mention a semiconductor region of the sixth scan transistor.
In a similar field of endeavor, Park’427 teaches
a semiconductor region (semiconductor layer Ad) of the first scan transistor (i.e. left transistor TRd of the gate driver GD) and a semiconductor region (Ad) of the sixth scan transistor (i.e. middle transistor Trd of the gate driver GD), (fig. 20a, [0315, 0318 and 0324]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kang in view of Lee in view of Noh in view of Kim’926 and in view of Lai, by specifically providing the semiconductor regions for the sixth scan transistor, as taught by Park’427, for the purpose of improving image quality, [0007].
Regarding claim 19, Lai discloses wherein the bias electrode (20G2) of the first scan transistor (20) is at the first gate layer, and wherein the bias electrode (30G2) of the seventh scan transistor (30) is at the second gate layer, (fig. 13, [0066-0067]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kang in view of Lee in view of Noh and in view of Kim’926, by specifically providing bias electrodes, as taught by Lai, for the purpose of improving the display effect, [0124].
Regarding claim 20, Lai discloses further comprising a metal layer (20G2) between the substrate (10) and the first active layer (201), (fig. 13, [0066-0067]),
wherein the bias electrode (20G2) of the first scan transistor (20) is at the metal layer (20G2), (fig. 13, [0067]), and
wherein the bias electrode (30G2) of the seventh scan transistor (30) is at the second gate layer, (fig. 13, [0066]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kang in view of Lee in view of Noh and in view of Kim’926, by specifically providing bias electrodes, as taught by Lai, for the purpose of improving the display effect, [0124].
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/LONG D PHAM/Primary Examiner, Art Unit 2623