DETAILED ACTION
Status of the Application
1. Applicant’s Election filed December 29, 2025 is received and entered.
2. Applicant elected Species B and Sub-Species A without traverse and identified claims 1 – 2, 4 – 8, and 17 – 20 as corresponding to this election.
3. Claims 3 and 9 – 16 are withdrawn as being directed to a non-elected species. Claims 1 – 2, 4 – 8, and 17 – 20 are pending and are under examination in this action.
4. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Requirement for Necessary Information
5. The Examiner has become aware of documents that may be material to patentability but have not been included in any IDS submissions even though the Applicant has been aware of these references for a substantial amount of time.
37 CFR 1.56(a) requires that “[e]ach individual associated with the filing and prosecution of a patent application has a duty of candor and good faith in dealing with the Office, which includes a duty to disclose to the Office all information known to that individual to be material to patentability”.
Specifically, Applicant has failed to disclose the existence of prior application 18/978,445 (U.S. Patent 12,475,856) as well as any references cited therein. This prior application presents clear double patenting issues, as set forth below. Due to the almost identical nature of the claimed subject matter, it is clear that any references known to the Applicant that were considered during prosecution of prior application 18/978,445 (U.S. Patent 12,475,856) would also need to be considered in this application to determine whether they are material to the patentability of this application. Therefore, the existence of any co-pending or prior applications with closely related subject matter, as well as each of the references cited therein, may be material to the patentability of this application for prior art and double patenting purposes and thus constitute necessary information that must be submitted to the Office.
6. Required Information: 37 CFR 1.105(a)(1)(viii) – In light of the above findings by the Examiner, Applicant is required to submit a list of every reference of which they are aware that may be material to the patentability of the claimed invention, as defined by 37 CFR 1.56(b). This requirement is being made in view of 37 CFR 1.56 and 1.105 in order to ensure that the most relevant prior art is fully considered.
Failure to provide a detailed list of all information that may be material to patentability of the claimed invention as defined by 37 CFR 1.56(b) will be considered non-responsive.
Accordingly, each piece of information referred to above is necessary material that is required to be submitted in order to properly proceed with the examination of this Application.
Double Patenting
7. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
8. Claims 1, 6 – 7, and 17 – 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 3 and 17 – 20 of U.S. Patent No. 12,475,856.
For Example:
Claim 1 (App. 19/084,764)
Claim 1 (U.S. Patent No. 12,475,856)
A gate driver comprising: first to nth stages, wherein n is a natural number greater than 1 and k is a natural number between 1 and n, wherein a kth stage of the first to nth stages has: (lines 1 – 3)
A gate driver, comprising: first to nth (n is a natural number greater than 2) stages, a kth (k is a natural number greater than 1 and less than n) stage among the first to nth stages including: (col. 14, lines 11 – 14)
a first transistor which transmits an input signal to a first control node; (line 4)
a first transistor including . . . a first terminal which receives an input signal, and a second terminal electrically connected to a first control node; (col. 14, lines 15 – 18)
a fifth transistor including a gate connected to an inverting control node, a first terminal which receives a high gate voltage, and a second terminal connected to an output node which outputs a gate signal; (lines 5 – 7)
a fifth transistor including a gate electrically connected to an inverting control node, a first terminal which receives a high gate voltage, and a second terminal electrically connected to an output node outputting a gate signal; (col. 14, lines 19 – 23)
a sixth transistor including a gate connected to a second control node, a first terminal which receives a first low gate voltage or a clock signal, and a second terminal connected to the output node; and (lines 8 – 10)
a sixth transistor including a gate electrically connected to a second control node, a first terminal which receives a low gate voltage, and a second terminal electrically connected to the output node; (col. 14, lines 24 – 27)
a fourth transistor connected between the first control node and the second control node, the fourth transistor including a gate which receives the first low gate voltage or a low gate voltage higher or lower than the first low gate voltage and a back gate (lines 11 – 14)
a fourth transistor including a gate which receives the low gate voltage, a first terminal electrically connected to the first control node, a second terminal electrically connected to the second control node, and a back gate; (col. 14, lines 28 – 32)
Claim 1 of U.S. Patent No. 12,475,856 fails to explicitly recite that the: back gate receives an input voltage that is a variable voltage, as required by claim 1 of the present application.
However, claim 1 of U.S. Patent No. 12,475,856 recites: a seventh transistor including . . . a first terminal which receives a voltage of the first control node or the second control node of a k-1th stage, and a second terminal electrically connected to the back gate of the fourth transistor (col. 14, lines 33 – 38).
Accordingly, the back gate receives a voltage from the first or second control nodes of the k-1th stage.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of Applicant’s claimed invention that the voltages of the first and second control nodes would be different from one another and would thus vary from one another. Since the back gate of the fourth transistor receives an input voltage from the first or second control nodes, this alternative recitation is sufficient to read on the recitation of the “variable voltage” because this recitation is open ended and includes the possibility of a switch or other mechanism
Additionally, it would have been obvious to try utilizing a variable voltage as an input voltage to the back gate of the fourth transistor. There are only two discernable options for such an input voltage, either the voltage be constant or variable. Accordingly, it would have been obvious to use a variable voltage as a modification of the claimed subject matter of U.S. Patent No. 12,475,856.
Allowable Subject Matter
9. Claims 2, 4 – 5, and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Citation of Pertinent Prior Art
10. The prior art made of record and not relied upon which is considered pertinent to applicant's disclosure includes: Kim et al. (U.S. Patent 11,551,604), No et al. (U.S. Pub. 2022/0383821), Zhang (U.S. Pub. 2025/0124857), Kim (U.S. Pub. 2023/0075599), Lee (U.S. Pub. 2020/0133327), Noh et al. (U.S. Pub. 2023/0009494), and Liberti et al. (U.S. Pub. 2022/0103170).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN A LUBIT whose telephone number is (571)270-3389. The examiner can normally be reached M - F, ~6am - 3pm.
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/RYAN A LUBIT/Primary Examiner, Art Unit 2626