DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 8-10 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20240177677) in view of Lee et al. (US 20200175912).
As to claim 1, Kim discloses a sub-pixel (Fig. 2(SP), [0043]: sub-pixel SP) comprising:
a first transistor (Fig. 2(DT): driving transistor) that is connected between a first node (Fig. 2(N2): second node) that receives a first driving power and a second node (Fig. 2(N3): third node) to generate a driving current and includes a control electrode connected to a third node (Fig. 2(N1): first node, [0052]: third pixel transistor PT3 transmits the high potential power voltage VDD to the second node N2. Note: second node N2 is interpreted as the “first node” and driving transistor DT interpreted as the “first transistor”. Therefore, driving transistor DT (first transistor) receives driving power VDD (interpreted as first driving power) from second node N2 (first node) through third pixel transistor PT3 (interpreted as fifth transistor), [0058]: when the driving transistor DT (first transistor) is turned on, a driving current is supplied to the light-emitting element EL);
a second transistor (Fig. 2(PT2): second pixel transistor) connected between a data line (Fig. 2(DL): data line) and the first node (Fig. 2(N2): second node, [0051]);
a third transistor (Fig. 2(PT1): first pixel transistor) connected between the second node (Fig. 2(N3): third node) and the third node (Fig. 2(N1): first node) and turned on in response to a first scan signal ([0050]: first pixel transistor PT1 (third transistor) can connect the first node N1 (third node) with the third node N3 (second node) based on the first scan signal SCAN1(n)); and
a light emitting element (Fig. 2(EL)) that receives the driving current to emit light ([0058]: driving current is supplied to the light-emitting element EL, [0060]: light-emitting element EL can emit light in proportion to the driving current from the driving transistor DT (first transistor)).
Kim does not explicitly teach the second transistor turned on in response to the first scan signal.
Lee teaches the second transistor (Fig. 2 (M2)) turned on in response to the first scan signal ([0060]: second transistor M2 is connected between the data line DLi and the first node N1 and turned on in response to the gate signal SCAN[j]. Note that the first transistor M1 and third transistor M3 are also connected as required by the claim).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s subpixel by incorporating Lee’s idea of turning the second transistor in response to the first scan signal in order to minimize noise on the gate signal and improve display quality (see Lee: [0027]).
As to claim 2, Kim (as modified by Lee) teach the sub-pixel of claim 1, wherein each of the second transistor (Kim: Fig. 2(PT2): second pixel transistor) and the third transistor (Kim: Fig. 2(PT1): first pixel transistor) is an NMOS transistor (Kim: Fig. 2, [0049]: first pixel transistor PT1 (third transistor) and the second pixel transistor PT2 (second transistor) are n-type (NMOS)) transistors).
As to claim 8, Kim discloses a display device (Fig. 1(110), [0035], [0039]) comprising:
a sub-pixel (Fig. 2(SP), [0043]: sub-pixel SP) that includes a first transistor (Fig. 2(DT): driving transistor) and a light emitting element (Fig. 2(EL)),
the first transistor (Fig. 2(DT): driving transistor) is connected between a first node (Fig. 2(N2): second node) that receives a first driving power and a second node (Fig. 2(N3): third node) to generate a driving current, the first transistor includes a control electrode connected to a third node (Fig. 2(N1): first node, [0052]: third pixel transistor PT3 transmits the high potential power voltage VDD to the second node N2. Note: second node N2 is interpreted as the “first node” and driving transistor DT interpreted as the “first transistor”. Therefore, driving transistor DT (first transistor) receives driving power VDD (interpreted as first driving power) from second node N2 (first node) through third pixel transistor PT3 (interpreted as fifth transistor), [0058]: when the driving transistor DT (first transistor) is turned on, a driving current is supplied to the light-emitting element EL),
the sub-pixel (Fig. 2(SP)) is connected to a first scan line, an emission control line, and a data line ([0043]: sub-pixel SP is connected to a data line DL, the plurality of scan lines SL, an emission control signal line);
an emission control signal to the emission control line (Fig. 2(EM(n)), [0043]: an emission control signal line);
a first scan driver (Fig. 1(120): gate driver) supplying a first scan signal to the first scan line (Fig. 1(SL), [0043]); and
a data driver (Fig. 1(130)) supplying a data signal to the data line (Fig. 1(DL), [0043]),
wherein the first scan signal (Fig. 2(SCAN1(n)): first scan signal) controls a timing at which the data signal is supplied to the first node (Fig. 2(N2): second node) and a timing at which the second node (Fig. 2(N3): third node) and the third node (Fig. 2(N1): first node) are connected ([0050] – [0051]).
Kim does not expressly teach an emission driver.
Lee teaches an emission driver (Fig. 1(400): EM driver, [0043]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s subpixel by incorporating Lee’s idea of including an emission driver in order to improve device functionality.
As to claim 9, Kim teaches the display device of claim 8, wherein the sub-pixel (Fig. 2(SP)) further includes
a second transistor (Fig. 2(PT2): second pixel transistor) connected between a data line (Fig. 2(DL): data line) and the first node (Fig. 2(N2): second node, [0051]);
a third transistor (Fig. 2(PT1): first pixel transistor) connected between the second node (Fig. 2(N3): third node) and the third node (Fig. 2(N1): first node) and turned on in response to a first scan signal ([0050]: first pixel transistor PT1 (third transistor) can connect the first node N1 (third node) with the third node N3 (second node) based on the first scan signal SCAN1(n)); and
the light emitting element (Fig. 2(EL)) that receives the driving current to emit light ([0058]: driving current is supplied to the light-emitting element EL, [0060]: light-emitting element EL can emit light in proportion to the driving current from the driving transistor DT (first transistor)).
Kim does not explicitly teach the second transistor turned on in response to the first scan signal.
Lee teaches the second transistor (Fig. 2 (M2)) turned on in response to the first scan signal ([0060]: second transistor M2 is connected between the data line DLi and the first node N1 and turned on in response to the gate signal SCAN[j]. Note that the first transistor M1 and third transistor M3 are also connected as required by the claim).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s subpixel by adapting Lee’s idea of turning the second transistor in response to the first scan signal in order to minimize noise on the gate signal and improve display quality (see Lee: [0027]).
As to claim 10, Kim (as modified by Lee) teach the display device of claim 9, wherein each of the second transistor (Kim: Fig. 2(PT2): second pixel transistor) and the third transistor (Kim: Fig. 2(PT1): first pixel transistor) is an NMOS transistor (Kim: Fig. 2, [0049]: first pixel transistor PT1 (third transistor) and the second pixel transistor PT2 (second transistor) are n-type (NMOS)) transistors).
As to claim 15, Kim discloses an electronic device (Fig. 1(110), [0035]) comprising:
a processor (Fig. 1(140): timing controller) to provide input image data ([0038]: timing controller 140 aligns the image data RGB input from an external source and supplies it to the data driver 130. It is well known in the art that a timing controller incorporates a processor); and
a display device (Fig. 1(110)) to display an image based on the input image data ([0038] – [0039]), wherein the display device comprising:
a sub-pixel (Fig. 2(SP), [0043]: sub-pixel SP) that includes a first transistor (Fig. 2(DT): driving transistor) and a light emitting element (Fig. 2(EL)),
the first transistor (Fig. 2(DT): driving transistor) is connected between a first node (Fig. 2(N2): second node) that receives a first driving power and a second node (Fig. 2(N3): third node) to generate a driving current, the first transistor includes a control electrode connected to a third node (Fig. 2(N1): first node, [0052]: third pixel transistor PT3 transmits the high potential power voltage VDD to the second node N2. Note: second node N2 is interpreted as the “first node” and driving transistor DT interpreted as the “first transistor”. Therefore, driving transistor DT (first transistor) receives driving power VDD (interpreted as first driving power) from second node N2 (first node) through third pixel transistor PT3 (interpreted as fifth transistor), [0058]: when the driving transistor DT (first transistor) is turned on, a driving current is supplied to the light-emitting element EL),
the sub-pixel (Fig. 2(SP)) is connected to an i-th first scan line, an (i-1)-th first scan line, an i-th emission control line, and a j-th data line ([0043]: sub-pixel SP is connected to a data line DL, the plurality of scan lines SL, an emission control signal line);
an i-th emission control signal to the i-th emission control line (Fig. 2(EM(n)), [0043]: an emission control signal line);
a first scan driver (Fig. 1(120): gate driver) that supplies an i-th first scan signal to the i-th first scan line and an (i- 1)-th first scan signal to the (i-1)-th first scan line (Fig. 1(SL), [0043]); and
a data driver (Fig. 1(130)) that supplies a data signal to the j-th data line (Fig. 1(DL), [0043]),
wherein the i-th first scan signal (Fig. 2(SCAN1(n)): first scan signal) controls a timing at which the data signal is supplied to the first node (Fig. 2(N2): second node) and a timing at which the second node (Fig. 2(N3): third node) and the third node (Fig. 2(N1): first node) are connected, and i and j are natural numbers ([0050] – [0051]).
Kim does not expressly teach an emission driver.
Lee teaches an emission driver (Fig. 1(400): EM driver, [0043]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s subpixel by incorporating Lee’s idea of including an emission driver in order to improve device functionality.
As to claim 16, Kim teaches the electronic device of claim 15, wherein the sub-pixel (Fig. 2(SP)) further includes
a second transistor (Fig. 2(PT2): second pixel transistor) connected between the j-th data line (Fig. 2(DL): data line) and the first node (Fig. 2(N2): second node, [0051]);
a third transistor (Fig. 2(PT1): first pixel transistor) connected between the second node (Fig. 2(N3): third node) and the third node (Fig. 2(N1): first node) and turned on in response to the i-th first scan signal ([0050]: first pixel transistor PT1 (third transistor) can connect the first node N1 (third node) with the third node N3 (second node) based on the first scan signal SCAN1(n)); and
the light emitting element (Fig. 2(EL)) that receives the driving current to emit light ([0058]: driving current is supplied to the light-emitting element EL, [0060]: light-emitting element EL can emit light in proportion to the driving current from the driving transistor DT (first transistor)).
Kim does not explicitly teach the second transistor turned on in response to the i-th first scan signal.
Lee teaches the second transistor (Fig. 2 (M2)) turned on in response to the i-th first scan signal ([0060]: second transistor M2 is connected between the data line DLi and the first node N1 and turned on in response to the gate signal SCAN[j]. Note that the first transistor M1 and third transistor M3 are also connected as required by the claim).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s subpixel by adapting Lee’s idea of turning the second transistor in response to the first scan signal in order to minimize noise on the gate signal and improve display quality (see Lee: [0027]).
Claims 3-4, 11-12 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20240177677) in view of Lee et al. (US 20200175912) and in further view of Kang et al. (US 202000113338).
As to claim 3, Kim (as modified by Lee) teach the sub-pixel of claim 1, further comprising a fourth transistor (Kim: Fig. 2(PT5): fifth pixel transistor) connected between the third node (Kim: Fig. 2(N1): first node) and a first power line (Kim: Fig. 2(Vint1)) providing a first initialization power (Kim: [0054]: fifth pixel transistor PT5 (fourth transistor) can transmit a first initialization voltage Vini1 of the first initialization line to the storage capacitor Cst and the first node N1 (third node)).
Kim (as modified by Lee) do not specifically teach the fourth transistor turned on in response to a second scan signal.
Kang teaches the fourth transistor (Fig, 2(TS4)) turned on in response to a second scan signal (Fig. 2(GI), [0041]: second gate signal GI, [0042]: fourth transistor TS4 may turn on, an initialization voltage VINIT may be applied to a first node N1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the subpixel of Kim (as modified by Lee) by incorporating Kang’s idea of turning on the fourth transistor in response to a second scan signal in order to further improve display quality.
As to claim 4, Kim (as modified by Lee and Kang) teach the sub-pixel of claim 3, further comprising a fifth transistor (Kim: Fig. 2(PT3): third pixel transistor) connected between the first node (Kim: Fig. 2(N2): second node) and a second power line (Kim: Fig. 2(VDD)) that provides a voltage of the first driving power and turned on in response to an emission control signal (Kim: [0052]: third pixel transistor PT3 transmits the high potential power voltage VDD to the second node N2 (first node) based on the emission control signal EM(n) from the emission control signal line); and
a sixth transistor (Kim: Fig. 2(PT4): fourth pixel transistor) connected between the second node (Kim: Fig. 2(N3): third node) and a fourth node (Kim: Fig. 2(N4): fourth node) and turned on in response to the emission control signal (Kim: [0053]: fourth pixel transistor PT4 is connected to the emission control signal line and transmit a driving current from the driving transistor DT to the light-emitting element EL based on the emission control signal EM(n) from the emission control signal line),
wherein the light emitting element (Kim: Fig. 2(EL)) is connected between the fourth node (Kim: Fig. 2(N4): fourth node) and a third power line (Kim: Fig. 2(VSS)) that provides a second driving power (Kim: [0060]: the anode of the light-emitting element EL is connected to the fourth node N4, and the cathode thereof is connected to a low potential power voltage line from which a low potential power voltage VSS is applied).
As to claim 11, Kim (as modified by Lee) teach the display device of claim 9, further comprising a second scan driver that supplies a second scan signal to the second scan line (Kim: [0063]: the second gate driver GD2 is added to the gate driver 120, so that the second scan signal SCAN2 at the high level can be generated without changing the existing driving timing of the first gate driver GD1 that generates the second scan signal SCAN2 at the low level),
wherein the sub-pixel (Kim: Fig. 2(SP)) further includes
a fourth transistor (Kim: Fig. 2(PT5): fifth pixel transistor) connected between the third node (Kim: Fig. 2(N1): first node) and a first power line (Kim: Fig. 2(Vint1)) providing a first initialization power (Kim: [0054]: fifth pixel transistor PT5 (fourth transistor) can transmit a first initialization voltage Vini1 of the first initialization line to the storage capacitor Cst and the first node N1 (third node)).
Kim (as modified by Lee) do not specifically teach the fourth transistor turned on in response to a second scan signal.
Kang teaches the fourth transistor (Fig, 2(TS4)) turned on in response to a second scan signal (Fig. 2(GI), [0041]: second gate signal GI, [0042]: fourth transistor TS4 may turn on, an initialization voltage VINIT may be applied to a first node N1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the subpixel of Kim (as modified by Lee) by incorporating Kang’s idea of turning on the fourth transistor in response to a second scan signal in order to further improve display quality.
As to claim 12, Kim (as modified by Lee and Kang) teach the display device of claim 11, wherein the sub-pixel (Kim: Fig. 2(SP)) further includes
a fifth transistor (Kim: Fig. 2(PT3): third pixel transistor) connected between the first node (Kim: Fig. 2(N2): second node) and a second power line (Kim: Fig. 2(VDD)) that provides a voltage of the first driving power and turned on in response to an emission control signal (Kim: [0052]: third pixel transistor PT3 transmits the high potential power voltage VDD to the second node N2 (first node) based on the emission control signal EM(n) from the emission control signal line); and
a sixth transistor (Kim: Fig. 2(PT4): fourth pixel transistor) connected between the second node (Kim: Fig. 2(N3): third node) and a fourth node (Kim: Fig. 2(N4): fourth node) and turned on in response to the emission control signal (Kim: [0053]: fourth pixel transistor PT4 is connected to the emission control signal line and transmit a driving current from the driving transistor DT to the light-emitting element EL based on the emission control signal EM(n) from the emission control signal line),
wherein the light emitting element (Kim: Fig. 2(EL)) is connected between the fourth node (Kim: Fig. 2(N4): fourth node) and a third power line (Kim: Fig. 2(VSS)) that provides a second driving power (Kim: [0060]: the anode of the light-emitting element EL is connected to the fourth node N4, and the cathode thereof is connected to a low potential power voltage line from which a low potential power voltage VSS is applied).
As to claim 17, Kim (as modified by Lee) teach the electronic device of claim 16, wherein the sub-pixel (Kim: Fig. 2(SP)) further includes
a fourth transistor (Kim: Fig. 2(PT5): fifth pixel transistor) connected between the third node (Kim: Fig. 2(N1): first node) and a first power line (Kim: Fig. 2(Vint1)) providing a first initialization power (Kim: [0054]: fifth pixel transistor PT5 (fourth transistor) can transmit a first initialization voltage Vini1 of the first initialization line to the storage capacitor Cst and the first node N1 (third node)).
Kim (as modified by Lee) do not specifically teach the fourth transistor turned on in response to the (i-1)th first scan signal.
Kang teaches the fourth transistor (Fig, 2(TS4)) turned on in response the (i-1)th first scan signal (Fig. 2(GI), [0041]: second gate signal GI, [0042]: fourth transistor TS4 may turn on, an initialization voltage VINIT may be applied to a first node N1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the subpixel of Kim (as modified by Lee) by incorporating Kang’s idea of turning on the fourth transistor in response to a second scan signal in order to further improve display quality.
As to claim 18, Kim (as modified by Lee and Kang) teach the electronic device of claim 17, wherein the sub-pixel (Kim: Fig. 2(SP)) further includes
a fifth transistor (Kim: Fig. 2(PT3): third pixel transistor) connected between the first node (Kim: Fig. 2(N2): second node) and a second power line (Kim: Fig. 2(VDD)) that provides a voltage of the first driving power and turned on in response to the i-th emission control signal (Kim: [0052]: third pixel transistor PT3 transmits the high potential power voltage VDD to the second node N2 (first node) based on the emission control signal EM(n) from the emission control signal line); and
a sixth transistor (Kim: Fig. 2(PT4): fourth pixel transistor) connected between the second node (Kim: Fig. 2(N3): third node) and a fourth node (Kim: Fig. 2(N4): fourth node) and turned on in response to the i-th emission control signal (Kim: [0053]: fourth pixel transistor PT4 is connected to the emission control signal line and transmit a driving current from the driving transistor DT to the light-emitting element EL based on the emission control signal EM(n) from the emission control signal line),
wherein the light emitting element (Kim: Fig. 2(EL)) is connected between the fourth node (Kim: Fig. 2(N4): fourth node) and a third power line (Kim: Fig. 2(VSS)) that provides a second driving power (Kim: [0060]: the anode of the light-emitting element EL is connected to the fourth node N4, and the cathode thereof is connected to a low potential power voltage line from which a low potential power voltage VSS is applied).
Allowable Subject Matter
Claims 5-7, 13-14 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/AFROZA CHOWDHURY/Primary Examiner, Art Unit 2628