DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/20/2025. The submission is following the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 6, 14, 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Arai et al., (US 2023/0044912 A1).
Regarding claim 1, Arai et al., disclose an imaging apparatus comprising:
a substrate (341, Fig.11);
a photoelectric converter (261) provided in the substrate (341, see Figs. 11-16, and [0187]);
a first transfer transistor (252A, Fig. 16) connected to the photoelectric converter (261) and including a first control terminal (“The TG 252A”, see [0168], “The TG 252A is a gate portion of the transfer transistor 252A”); and
a second transfer transistor (252B, Fig.16) connected to the photoelectric converter (261) and including a second control terminal (“the TG 252B”, see [0168], “the TG 252B is a gate portion of the transfer transistor 252B”), wherein the photoelectric converter (261) includes a first semiconductor region (352) of a first conductivity type (“P-type”, [0187]) provided in the substrate (341, see Fig. 11 and [0187], “an N-type (second conductive type) semiconductor region 352 is formed in unis of pixels in a P-type (first conductive type) semiconductor region 351”), and in a plan view of the substrate, each of the first control terminal (“The TG 252A”) and the second control terminal (“the TG 252B”)
overlaps the first semiconductor region (352) (see Fig.16, both gates (The TG 252A and the TG 252B) of the transfer transistors overlap vertically with the photodiode 261, and [0187], the photodiode 261 is formed in the first semiconductor region 352)
, and a total of an overlapping area of the first control terminal (TG 252A) and the first semiconductor region and an overlapping area of the second control terminal (TG 252B) and the first semiconductor region is at least 20% of an area of the photoelectric converter (see Fig.16, the total overlapping of both gates with the active region is at least at 20% of the photodiode region 261).
Regarding claim 2, Arai et al., disclose an imaging apparatus comprising:
a substrate (341, Fig.11, [0186]); a photoelectric converter (261) provided in the substrate (341, see Figs. 11-12, and [0187]); a first transfer transistor (252A, Fig. 16) connected to the photoelectric converter (261) and including a first control terminal (“The TG 252A”, see [0168], “The TG 252A is a gate portion of the transfer transistor 252A”); and a second transfer transistor (252B, Fig.16) connected to the photoelectric converter (261) and including a second control terminal (“the TG 252B”, see [0168], “the TG 252B is a gate portion of the transfer transistor 252B”), wherein the photoelectric converter (261) includes a first semiconductor region (352) of a first conductivity type provided in the substrate, and in a plan view of the substrate (341)(see Fig. 11 and [0187], “an N-type (second conductive type) semiconductor region 352 is formed in unis of pixels in a P-type (first conductive type) semiconductor region 351”), the first control terminal (“The TG 252A”, see [0168]) and the second control terminal (“the TG 252B”, see [0168]) overlap the first semiconductor region (see Fig.16, both gates (The TG 252A and the TG 252B) of the transfer transistors overlap vertically with the photodiode 261, and [0187], the photodiode 261 is formed in the first semiconductor region 352) and are aligned in a first direction (both transistor gates are lined up side by side along a straight line from left to right), and in the first direction, a total of a length of an overlapping portion of the first control terminal (“The TG 252A”) and the first semiconductor region (352) and a length of an overlapping portion of the second control terminal (the TG 252B) and the first semiconductor region (352) is at least 20% of a length of the photoelectric converter (see Fig.16 at least, the length of overlap between the gate 252A and the PD261 plus the length of overlap between the gate 252B and the PD 261 is at least 20% of the total length of the PD261 along the straight line from the left to right).
Regarding claim 6, Arai et al., as discussed in claim 1, disclose in the plan view of the substrate, the overlapping area of the first control terminal (TG252A) and the first semiconductor region is equivalent to the overlapping area of the second control terminal (TG252B) and the first semiconductor region (see Fig.16, the area where the TG252A overlaps the photoelectric region 261 is the same as the area where the TG252B overlaps the photoelectric region 261).
Regarding claim 14, Arai et al., disclose a fabrication method for fabricating an imaging apparatus, the fabrication method comprising: forming a photoelectric converter (261, Figs.11-12) including a first semiconductor region (352) of a first conductivity type (P-type) provided in a substrate (341, Fig.11)([0187], “ semiconductor region 352 is formed in unis of pixels in a P-type (first conductive type) semiconductor region 351”)
; and forming a first transfer transistor (252A, Fig. 16) and a second transfer transistor (252B, Fig.16) that are connected to the photoelectric converter (261, see Fig.16), wherein in the forming of the first transfer transistor (252A) and the second transfer transistor (252B), each of a first control terminal (TG 252A ) of the first transfer transistor (252A, see [0168], “The TG 252A is a gate portion of the transfer transistor 252A”) and a second control terminal (the TG252B) of the second transfer transistor (252B, see [0168], “the TG 252B is a gate portion of the transfer transistor 252B”) is formed to overlap the first semiconductor region in a plan view of the substrate (see Fig. 16, both the TG 252B and the TG 252A are side by side on the top of the PD261).
Regarding claim 15, Arai et al., as discussed in claim 14, disclose wherein in the forming of the first transfer transistor (252A, Fig. 16) and the second transfer transistor (252B, Fig.16), in the plan view of the substrate (341), each of the first control terminal (TG 252A ) and the second control terminal (TG 252B ) is formed to overlap the first semiconductor region to satisfy the following:(i) a total of an overlapping area of the first control terminal and the first semiconductor region and an overlapping area of the second control terminal and the first semiconductor region is at least 20% of an area of the photoelectric converter (see Fig.16, the length of overlap between the gate 252A and the PD261 plus the length of overlap between the gate 252B and the PD 261 is at least 20% of the total length of the PD261 along the straight line from the left to right)
or (ii) in an alignment direction of the first control terminal and the second control terminal, a total of a length of an overlapping portion of the first control terminal and the first semiconductor region and a length of an overlapping portion of the second control terminal and the first semiconductor region is at least 20% of a length of the photoelectric converter.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Arai et al., in view of Mheen et al., (US 2007/0158710 A1).
Regarding claim 4, Arai et al., as discussed in claim 1, disclose a driving circuit (411A, 411B, see [0206], “Referring to FIG. 13 , the via 411A is connected to the pixel driving line 246A … the pixel driving line 246A is connected to the TG 251A”, and [0217], “the via 411B is connected to the pixel driving line 246B …the pixel driving line 246B is connected to the TG 251B”). Arai et al., do not disclose that the driving circuit supplies a voltage lower than or equal to an electric potential of the substrate to the first control terminal and the second control terminal as claimed. Mheen et al., disclose a driving circuit supplies a voltage lower than or equal to an electric potential of the substrate to the first control terminal and the second control terminal (Fig. 3 and [0045], “The transfer transistor Tx comprises a gate 310, a gate oxide layer 320 and a p-type substrate 360”, and [0047], “a predetermined negative offset potential is applied to the gate 310”). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Arai et al., by utilizing the teaching of Mheen et al., to raise the potential capacity, thereby better reducing the dark current (Mheen et al., [0047]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Arai et al., in view of Mao et al., (US 2018/0098008 A1).
Regarding claim 7, Arai et al., as discussed in claim 1, do not disclose a unit cell that is provided in the substrate and includes n pixels, where n is a natural number, and a charge accumulator in which charge generated in the n pixels accumulates as claimed. Mao et al., disclose a unit cell (102, Fig.1) that is provided in a substrate and includes n pixels, where n is a natural number (P1, P2, P3, see Fig.1), and a charge accumulator (224, Fig.2 or 324, Fig.3) in which charge generated in the n pixels accumulates wherein each of the n pixels includes the photoelectric converter (214/314), the first transfer transistor (316A), and the second transfer transistor (318A), and in each of the n pixels, the first transfer transistor includes a first input and output terminal connected to the photoelectric converter (314A) within the pixel (see Fig.3) and a second input and output terminal connected to the charge accumulator (FD), and the second transfer transistor includes a third input and output terminal connected to the photoelectric converter (314A) within the pixel (see Fig.3) and a fourth input and output terminal connected to a power supply line (VDD, Fig.3). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Arai et al., by utilizing the teaching of Mao et al., to provide a higher dynamic range (Mao et al., [0031]).
Claims 8-10, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Arai et al., in view of Mao et al., and further in view of Ito et al., (US 2016/0161611 A1).
Regarding claims 8, 9 and 13, Arai et al., in view of Mao et al., as discussed in claim 7, do not disclose a driving circuit that drives the first control terminal and the second control terminal according to an operation mode selected from among a plurality of operation modes as claimed. Ito et al., disclose a driving circuit that drives the first control terminal and the second control terminal according to an operation mode selected from among a plurality of operation modes ([0076], “an illumination mode” and “a first distance measurement mode (sensing mode)”), wherein the plurality of operation modes include: a first operation mode in which to expose at least one of the n pixels to light with a first wavelength ([0085], “a white LED with a shorter wavelength “); and a second operation mode in which to expose at least one of the n pixels to blinking light (“light emission pulse signals”, [0076]) with a second wavelength (“near-infrared light”). Ito et al., disclose the first operation mode being an imaging mode for generating a visible light image ([0080], “an illumination light source used for lighting up a dark place without the purpose of distance measurement”), and the second operation mode is a distance measuring mode for generating a range image ([0080]a distance measurement light source used for detecting a physical quantity such as a distance ([0087]-[0088], “outputs distance information indicating the distance to the subject”). Ito et al., also disclose a light source (20, Fig. 1); the imaging apparatus according to claim 8; and an arithmetic circuit that calculates a distance to a target object in accordance with a signal output from the imaging apparatus ([0088], “The calculator 40 performs an operation based on the raw data 53 received from the imaging device 10, and outputs distance information (detected information) indicating the distance to the subject”), wherein the blinking light ([0076], “light emission signals (light emission pulse signals)”) with the second wavelength ([0082], “long-wavelength light source (e.g., red LED)”) is reflected light that has reflected off the target object among blinking light rays emitted from the light source ([0085], “ exposure of light reflected by a subject”).Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Arai et al., and Mao et al., by utilizing the teaching of Ito et al., to provide multi-wavelength sensing capability and reduce interference of signals.
Regarding claim 10, Arai et al., in view of Mao et al., and Ito et al., as discussed in claim 8, Ito et al., also disclose that in the second operation mode, the n pixels are exposed to the blinking light at a different timing for each frame period ([0087]), and within the frame period, a start timing of exposure of each of the n pixels is same [0101], “With an operation of collectively resetting the plurality of photodiodes (PDs) 101 known as global reset, it is possible to eliminate the time difference in the light detected by each PD”), and an end timing of exposure of each of the n pixels is same ([0102], “collectively reading the signal charge of the light receiver from the plurality of pixels into the accumulator”).
Claims 3, 5 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Arai et al.
Regarding claims 3 and 16, Arai et al., disclose the fabrication method for fabricating the imaging apparatus according to claim 14, wherein in the forming of the photoelectric converter (261, Fig.16), the photoelectric converter (261) that further includes, above the first semiconductor region (352), a second semiconductor region of a second conductivity type ([0187], “a P-type semiconductor region 351”, and see Fig. 11, the P-type coats the surfaces of the N-types 352) having a reverse polarity of the first conductivity type is formed ([0187], P-type has a reverse polarity of the first conductivity type (N-type)), and in the forming of the first transfer transistor (252A) and the second transfer transistor (252B, Fig. 16), in the plan view of the substrate, each of the first control terminal (TG252A) and the second control terminal (TG252B) is disposed above the second semiconductor region with an insulator film interposed therebetween ((351)(see Figs. 11-16, the gates TG252A/B located at the front side of the substrate. Because the P-type region 351 coats the front surface of the substrate, the gates TG252A/B sit directly above the P-type surface layer) with an insulator film interposed therebetween (inherently included because without an insulator film, the system would not operate). However, if not, selecting an element such as an insulator film for providing better control of electric field between gate and the semiconductor would have been obvious. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Arai et al., accordingly to provide better control of electric field between gate and the semiconductor.
Regarding claim 5, Arai et al., as discussed in claim 1, disclose the first transfer transistor and the second transfer transistor; however, Arai et al., do not disclose the arrangement such as the first transfer transistor being disposed opposite the second transfer transistor as claimed. Selecting an arrangement for transistors to minimize cross talk and signal interconnect interface for the apparatus would have been obvious to one of ordinary skill in the art. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Arai et al., accordingly to minimize cross talk and signal interconnect interface for the apparatus.
Allowable Subject Matter
5. Claims 11, 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 11, the prior art fails to disclose in the second operation mode, within a frame period, a start timing of exposure of each of the n pixels is different, and an end timing of exposure of each of the n pixels is different.
Regarding claim 12, the prior art fails to disclose the unit cell includes: a capacitor; and a switching device connected in series between the capacitor and the charge accumulator, and the switching device maintains conduction between the capacitor and the charge accumulator in the second operation mode, and interrupts conduction between the capacitor and the charge accumulator in the first operation mode.
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MAI THI NGOC TRAN whose telephone number is (571)272- 3456. The examiner can normally be reached Monday-Friday: 9:00-5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, GEORGIA EPPS can be reached on (571)272-2328. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visithttps://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/M.T.T./Examiner, Art Unit 2878
/GEORGIA Y EPPS/Supervisory Patent Examiner, Art Unit 2878
Prosecution Insights