DETAILED ACTION
General Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
5. Applicants seeking an interview with the examiner, including Microsoft Team Meeting, are encouraged to fill out the online Automated Interview Request (AIR) form
(https://www.uspto.gov/sites/default/files/documents/PTOL413A.pdf). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
6. Status of claim(s) to be treated in this office action:
a. Independent: 1 and 11.
b. Pending: 1-20.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 11 are rejected under 35 U.S.C. 103 as being unpatentable over Li PG PUB 20080084751 (hereinafter Li), in view of Kwak PG PUB 20160240257 (hereinafter Kwak).
Regarding independent claim 1, Li teaches an operating method of a storage device, the operating method comprising:
performing plural program loops on target memory cells for an n-th program state (B state in figure 7, figures 13 and 14 of Li teaches programming multi-state nonvolatile memory cells, step 512, 514 and 522 in figure 14 of Li applies a program pulse, verifies the cells, increases the pulse voltage, and repeats the loop), according to a double verify program scheme (Figures 17-18 of Li teaches a lower and final verify level for a state, [0099] of Li, “…programming of memory cells to state A using two verify levels, indicated in the Figures as V.sub.vA1 and V.sub.vA… two verify operations are required for each state. One verify operation at the corresponding final verify level (e.g., V.sub.vA) for each state to which the coarse/fine programming methodology is applied, and one verify operation at the corresponding second verify level (e.g., V.sub.vA1) for each state…”, [0103] of Li, “…coarse and fine verify levels are only used for a select state or states. For example, coarse and fine levels could be used just for state B and state C or just state C…”), n being a natural number greater than 1 and less than N corresponding to a number of program states, wherein:
the plural program loops include applying, to the target memory cells, program pulses having a step size for the n-th program state according to an incremental step pulse program scheme (figure 6 of Li teaches an ISPP programming method, figure 14 of Li teaches Vpgm increase by a step size before returning to step 512 for the next pulse); and
the plural program loops include varying the step size according to the n-th program state (Li teaches in figure 14 switching between DVpgm1 and DVpgm2, including during full sequence programming, and teaches combining changed increments with coarse/fine verification).
Li does not clearly establish that its illustrated increment switch occurs while the selected B cells are still being programmed.
Kwak supplies the loop-level adjustment. In figure 9 and [0124], “an increment of a program pulse may be reduced from ISPP1 to ISPP2”, with the switching loop selectable using “information indicating whether a particular state is passed” ([0124] of Kwak, “…the increment of the program pulse ISPP1 may be reduced after the predetermined program loop. Here, the predetermined program loop may be based on the number of program loops, information indicating whether the number of off cells detected is over a predetermined value, information indicating whether a particular state is passed…”). Applying Kwak’s adjustment during Li’s ongoing program loops for B would produce the claimed varying step size for the n-th state.
Li teaches using two verify levels to tighten a state’s threshold -voltage distribution and using that technique with changed pulse increments. Kwak teaches adjusting the increment during program loop to narrow threshold-voltage distribution toward higher program states. A person of ordinary skill would have had reason to apply Kwak’s loop level increment control to Li’s double verify programming of intermediate state B to improve control of B distribution.
Regarding independent claim 11, the combination of Li and Kwak teaches an operating method of a storage device, the operating method comprising performing plural program loops on target memory cells for an n-th program state within a j-th program state group (P16’ in third group of figure 7 of Kwak, Kwak in figure 7 teaches three groups, the third group containing P15’, P16’ and P17’), according to a double verify program scheme (Figures 17-18 of Li teaches a lower and final verify level for a state, [0099] of Li, “…programming of memory cells to state A using two verify levels, indicated in the Figures as V.sub.vA1 and V.sub.vA… two verify operations are required for each state. One verify operation at the corresponding final verify level (e.g., V.sub.vA) for each state to which the coarse/fine programming methodology is applied, and one verify operation at the corresponding second verify level (e.g., V.sub.vA1) for each state…”[0103] of Li, “…coarse and fine verify levels are only used for a select state or states. For example, coarse and fine levels could be used just for state B and state C or just state C…”), n being a natural number greater than 1 and less than Nj corresponding to a number of program states included in each program state group, and j being a natural number greater than 1 to J corresponding to a number of program state groups, wherein:
the plural program loops include applying, to the target memory cells, program pulses having a step size for an n-th program state within the j-th program state group (Kwak in figure 7 teaches three groups, the third group containing P15’, P16’ and P17’. In the proposed combination, select J=3, j=3, Nj=3, and n=2, so P16’ is the n-th state within the j-group) according to an incremental step pulse program scheme (figure 6 of Li teaches an ISPP programming method, figure 14 of Li teaches Vpgm increase by a step size before returning to step 512 for the next pulse); and
the plural program loops include varying the step size according to each of the n-th program state and the j-th program state group (Li teaches in figure 14 switching between DVpgm1 and DVpgm2, including during full sequence programming, and teaches combining changed increments with coarse/fine verification, Kwak in figure 7 teaches the distribution widths of its groups to the program-pulse increment, Kwak in figure 9-10 and [0124] teaches varying that increment over program loops, including based on whether a particular state is passed. Applying Kwak’s increment selection of Li’s double-verified programming of P16’ in Kwak third group provides the proposed state-and group -dependent variation).
Li teaches using two verify levels to tighten a state’s threshold -voltage distribution and using that technique with changed pulse increments. Kwak teaches controlling distribution width through increment, including for group states. A person of ordinary skill would have had reason to apply Kwak’s group and loop-dependent increment control to Li’s double verify method to improve distribution of the selected intermediate states.
Allowable Subject Matter
Claims 2-10, 12-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The closest prior art to the present invention is Li PG PUB 20080084751 (hereinafter Li).
Li discloses lowest programmed state in multi-state non-volatile flash memory devices can suffer from an increased level of bit line to bit line capacitive charge coupling when compared with other states. Program voltages applied to memory cells as increasing voltage pulses can be incremented using smaller values when programming memory cells to the lowest programmable state. Smaller increments in the applied voltage allow for greater precision and a narrower threshold voltage distribution to compensate for the disproportionate charge coupling experienced by cells programmed to this state. Smaller increment values can be used when switching from lower page to upper page programming in some implementations. In a pipelined programming architecture where cells forming a physical page store two logical pages of data and programming for one logical page begins before receiving data for the other logical page, the increment value can be increased when switching from programming the first logical page to programming both pages concurrently.
Regarding claim 2 (and the respective dependent claims), the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: adjusting the step size from the initial value to a pre-updated value when, for the first time, one of the target memory cells has a higher threshold voltage than a pre-verification level for the n-th program state, and wherein the pre-updated value is a sum of the base value and a pre- offset value.
Regarding claim 12 (and the respective dependent claims), the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: adjusting the step size from the group initial value to a pre-updated value when, for the first time, one of the target memory cells has a higher threshold voltage than a pre-verification level for the n-th program state within the j-th program state group, and wherein the pre-updated value is a sum of the base value and a group pre-offset value.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOCHUN L CHEN whose telephone number is (571)272-0941. The examiner can normally be reached on M-F: 9AM-5:00PM.
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824
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