Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
In response to a restriction requirement dated December10, 2025 the Applicants elected Invention I of claims 1-7 without traverse in a reply filed on February 9, 2026. The non-elected claims 8-20 are withdrawn.
Pending elected claims 2-7 of which claim 1 is an independent claim, are examined on their merits, infra.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119(a)-(d), and based on application # 10-2024-0087950 filed in Korea on July 4, 2024 which papers have been placed of record in the file.
Oath/Declaration
The Office acknowledges receipt of a properly signed Oath/Declaration submitted March 21, 2025.
Drawings
The drawings filed March 21, 2025 are accepted by the examiner.
Abstract
The abstract filed March 21, 2025 is accepted by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US 20230215316 Al) in view of Ono (US 20240312421 A1) in further view of Lee (US 20220077263 A1)
As to Claim 1:
Baek et al. discloses an electronic apparatus (Baek, see Abstract, where Baek discloses that a emitting display device can include a display panel including a plurality of pixels; a plurality of gate lines configured to supply gate signals to the pixels; and a plurality of stages connected to the plurality of gate lines, and configured to output gate pulses to a group of pixels connected to at least two gate lines among the plurality of gate lines for sensing a characteristic of each pixel among the group of pixels during a sensing period) comprising a processor (Baek, see processors 200, 300, 400 and 500 in figure 1) configured to generate image data (Baek, see paragraph [0004], where Baek discloses compensation methods being used in a display period where an image is displayed), and a display device configured to display an image based on the image data (Baek, see paragraph [0056], where Baek discloses that the light emitting display apparatus according to the present disclosure, as illustrated in FIG. 1, can include a light emitting display panel 100 which includes a display area 120 displaying an image and a non-display area 130 provided outside the display area 120, a gate driver 200 which supplies a gate signal to a plurality of gate lines GLl to GLg provided in the display area 120 of the light emitting display panel 100, a data driver 300 which supplies data voltages to a plurality of data lines DLl to DLd provided in the light emitting display panel 100, a controller 400 which controls driving of the gate driver 200 and the data driver 300, and a power supply 500 which supplies power to the controller, the gate driver, the data driver, and the light emitting display panel. Here, g, d and n can be positive integers greater than zero), the display device comprising: a display panel comprising pixels (Baek, see 110 in figure 1 and paragraph [0058], where Baek discloses that each pixel 110 included in the light emitting display panel 100, as illustrated in FIG. 2, can include an emission area which includes a pixel driving circuit PDC, including a switching transistor Tswl, a storage capacitor Cst, a driving transistor Tdr, and a sensing transistor Tsw2, and a light emitting device ED); and a gate driver (Baek, see gate driver 200 in figure 4 and paragraph [0056], where Baek discloses controller 400 which controls driving of the gate driver 200 and the data driver 300, and a power supply 500 which supplies power to the controller, the gate driver, the data driver, and the light emitting display panel. Here, g, d and n can be positive integers greater than zero) comprising stages configured to provide gate signals to the pixels (Baek, see 201 in figure 4 and paragraphs [0085] and [0086], where Baek discloses that the gate driver 200 can include a plurality of stages 201 ( e.g., stages 1 through g, where g is a positive integer greater than zero). Each of the stages 201 can be connected to at least one gate line GL. Each of the stages 201 can be driven based on a start signal transferred from the controller 400, or can be driven based on a carry signal transferred from a previous stage or a next stage), the stages comprising: a control circuit configured to control a signal of a control node (Baek, see paragraph [0018], where Baek discloses that each of the plurality of stages includes a signal output unit configured to sequentially output the gate pulses to the at least two gate lines; and a sensing selector configured to store a selection signal in a sensing selection period of the sensing period, and control the signal output unit to output the gate pulses during a sensing performance period of the sensing period based on the selection signal, the sensing performance period being subsequent to the sensing selection period), and a signal of an inverting control node (Baek, see paragraph [0102], where Baek discloses that the signal controller 210 can control a signal supplied to a Q node and a signal supplied to a Qb node, and thus, the signal output unit 220 can output the gate pulse or the gate off signal (e.g., see FIGS. 5 and 6)), based on an input signal; and first to Mth output circuits (Baek, see paragraph [0106], where Baek discloses that the signal output unit 220 can output the gate off signal to the gate lines based on the Qb node control signal. According to an embodiment of the present invention, the Qb node can be effectively be pre-charged or can be ready faster, and sensing of the pixels connected to each of the gate lines can be carried out faster during the OFF sensing, thus, improving) M being a natural number greater than or equal to 3 (Baek, see SCCLK1 through SCCLK4 in figure 6) , configured to respectively output first to Mth output signals based on the signal of the control node and the signal of the inverting control node (Baek, see 220 in figure 6), and comprising: a pull-up transistor configured to transmit a high gate voltage to an output terminal in response to the signal of the inverting control node (Baek, see Tc1 in figure 6); a buffer transistor configured to transmit a corresponding clock signal among first to Mth clock signals to the output terminal in response to the signal of the control node (Baek, see Tc2 in figure 6); and a boost capacitor connected between the output terminal and the gate of the buffer transistor (Baek, see capacitor between Tc1 and Tc2 in figure 6 and paragraph [0126], where Baek discloses that a gate of the first carry output transistor Tcl can be connected to a Q node Q, a first terminal of the first carry output transistor Tcl can be connected to a line through which a 4n-3th carry clock SRCLK(4n-3) is input, and a second terminal of the first carry output transistor Tcl can be connected to a carry output line), and wherein a sensed value of the boost capacitor of the first output circuit is different from at least one of capacitances of the boost capacitors of the second to Mth output circuits (Baek, see CS(4n-3), CS(4n-4) and CS(4n-5) in figure 8).
Baek differs from the claimed subject matter in that Baek does not explicitly disclose an always-on transistor connected between the control node and a gate of the buffer transistor, and configured to be maintained in a turned-on state; and a boost capacitor connected between the output terminal and the gate of the buffer transistor, and wherein a capacitance of the boost capacitor of the first output circuit is different from at least one of capacitances of the boost capacitors of the second to Mth output circuits.
However in an analogous art, Ono discloses an always-on transistor (Ono, see T3 in figure 5A) connected between the control node (Ono, see Q0 in figure 5A) and a gate of the buffer transistor (Ono, see gate of T8 in figure 5A), and configured to be maintained in a turned-on state (Ono, see paragraph [0214], where Ono discloses that the timing waveforms shown in FIG. 30 are illustrative. In the example of FIG. 30, signal CLK_BUF may be pulsed high (with pulse width PW _SC) during the low phase of CLK_B. Operating gate driver 40-o in this way can, if care is not taken, result in transient signals to be coupled onto signal CR_OUT via always-on transistor T3, as indicated by signal perturbations 110. Such signal perturbations 110 can be propagated down the chain of gate driver circuits, showing up as transient signals 112 in signal CR_IN. Such type of transient signals can cause instability in the state of inverter 100, which may inadvertently drive node QBl to an incorrect voltage level); and a boost capacitor (Ono, see CBST in figure 33) connected between the output terminal (Ono, see GOUT in figure 33) and the gate of the buffer transistor (Ono, see gate of transistor T2 and paragraph [0220], where Ono discloses that as shown in FIG. 33, output buffer subcircuit 44-r may include output buffer transistors Tl and T2, additional transistors T3 and Tl3, and capacitors CQ2 and CBSTt .Transistor Tl may be a p-type silicon transistor having a first source-drain terminal configured to receive output buffer clock signal CLK_ BUF, a gate terminal coupled to node Q2, and a second source-drain terminal coupled to a gate driver output port on which gate output signal GOUT is generated).
PNG
media_image1.png
856
1104
media_image1.png
Greyscale
PNG
media_image2.png
896
1058
media_image2.png
Greyscale
It would have been obvious to one of ordinary skill in the art to modify the invention of Baek with Ono. One would be motivated to modify Baek by disclosing an always-on transistor connected between the control node and a gate of the buffer transistor, and configured to be maintained in a turned-on state; and a boost capacitor connected between the output terminal and the gate of the buffer transistor as taught by Ono, and thereby prolonging the lifetime of gate driver circuitry where a lot of switching activity takes place and where leakage is not as big of a concern relative to pixels (Ono, see paragraph [0075]). Baek in view of Ono differ from the claimed subject matter in that Baek in view of Ono does not explicitly disclose wherein a capacitance of the boost capacitor of the first output circuit is different from at least one of capacitances of the boost capacitors of the second to Mth output circuits.
However in an analogous art, Lee discloses wherein a capacitance of the boost capacitor of the first output circuit is different from at least one of capacitances of the boost capacitors of the second to Mth output circuits (Lee, see paragraph [0024], where Lee discloses that the first lower boost electrode and the first upper boost electrode may form a first boost capacitor, the second lower boost electrode and the second upper boost electrode may form a second boost capacitor, and a capacitance of the first boost capacitor may be different from a capacitance of the second boost capacitor).
It would have been obvious to one of ordinary skill in the art to modify the invention of Baek in view of Ono with Lee. One would be motivated to modify Baek in view of Ono by disclosing a capacitance of the boost capacitor of the first output circuit is different from at least one of capacitances of the boost capacitors of the second to Mth output circuits as taught by Lee, and thereby reducing a distance between conductors forming a capacitor, it is possible to reduce an area occupied by the capacitor and realize high resolution while maintaining a capacitance of the capacitor (Lee, see paragraph [0028]).
As to Claim 2:
Baek in view of Ono in further view of Lee discloses that the electronic apparatus of claim 1, wherein the capacitances of the boost capacitors of the first to Mth output circuits are different from each other (Lee, see paragraph [0024], where Lee discloses that the first lower boost electrode and the first upper boost electrode may form a first boost capacitor, the second lower boost electrode and the second upper boost electrode may form a second boost capacitor, and a capacitance of the first boost capacitor may be different from a capacitance of the second boost capacitor).
As to Claim 3:
Baek in view of Ono in further view of Lee discloses that the electronic apparatus of claim 1, wherein the first to Mth output circuits are configured to sequentially output pulses of the first to Mth clock signals as the first to Mth output signals (Baek, see CS(4n-3), CS(4n-4) and CS(4n-5) in figure 8).
Allowable Subject Matter
Claims 4, 5, 6 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Referring to claim 4 and dependent claims 5, 6 and 7, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein the control circuit comprises: a first transistor configured to transmit the input signal to the control node in response to an M+1th clock signal; a second transistor comprising a gate connected to the inverting control node, a first terminal configured to receive the high gate voltage, and a second terminal; and a third transistor comprising a gate configured to receive one of the first to Mth clock signals, a first terminal connected to the second terminal of the second transistor, and a second terminal connected to the control node”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure. Ono (US 20240127758 A1) discloses that the pixels can be formed using semiconducting oxide transistors, whereas the gate drivers can be formed using silicon transistor. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed. Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NELSON ROSARIO whose telephone number is (571)270-1866. The examiner can normally be reached on Monday through Friday, 7:30am- 5:00pm EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached on (571) 270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NELSON M ROSARIO/Primary Examiner, Art Unit 2624