StDETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Claims 16-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on March 6, 2026.
Allowable Subject Matter
Claims 2-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest related art is Han et al. (US 20220101783 A1).
Han does not teach each and every limitation of claim 2 including:
Wherein the pixel circuit block comprises:
a first transistor comprising a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node;
a second transistor comprising a control electrode for receiving the write signal, a first electrode for receiving the pixel data voltage, and a second electrode connected to the second node; and
a fifth transistor comprising a control electrode for receiving the emission signal, a first electrode for receiving a first power voltage, and a second electrode connected to the second node, and
wherein the pulse width modulation block comprises:an eighth transistor comprising a control electrode connected to a fifth node, a first electrode for receiving the first power voltage, and a second electrode connected to the control electrode of the first transistor; and
a ninth transistor comprising a control electrode for receiving the pulse width modulation write signal, a first electrode for receiving the pulse width modulation data voltage, and a second electrode connected to the fifth node.
Claims 3-13 are objected to as dependent upon claim 2.
Regarding claim 12, Han is the closest prior art. Han does not teach each and every limitation including:
wherein the pixel circuit block comprises:
a first transistor comprising a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node;
a second transistor comprising a control electrode for receiving the write signal, a first electrode for receiving the pixel data voltage, and a second electrode connected to the second node;
a third transistor comprising a control electrode for receiving the write signal, a first electrode connected to the third node, and a second electrode connected to the first node;
a fourth transistor comprising a control electrode for receiving the initialization signal, a first electrode for receiving a first initialization voltage, and a second electrode connected to the first node;
a fifth transistor comprising a control electrode for receiving the emission signal, a first electrode for receiving a first power voltage, and a second electrode connected to the second node;
a sixth transistor comprising a control electrode for receiving the emission signal, a first electrode connected to the third node, and a second electrode connected to a fourth node;
a seventh transistor comprising a control electrode for receiving the light- emitting element initialization signal, a first electrode for receiving a second initialization voltage, and a second electrode connected to the fourth node; and
a first storage capacitor comprising a first electrode for receiving the first power voltage, and a second electrode connected to the first node,
wherein the pulse width modulation block comprises:
an eighth transistor comprising a control electrode connected to a fifth node, a first electrode for receiving the first power voltage, and a second electrode connected to the first node;
a ninth transistor comprising a control electrode for receiving the pulse width modulation write signal, a first electrode for receiving the pulse width modulation data voltage, and a second electrode connected to the fifth node; and
a sweep capacitor comprising a first electrode connected to the sweep signal generator, and a second electrode connected to the fifth node, and wherein the sweep signal generator comprises:
a tenth transistor comprising a control electrode connected to a sixth node, a first electrode connected to a seventh node, and a second electrode connected to an eighth node;
an eleventh transistor comprises a control electrode for receiving the write signal, a first electrode for receiving the sweep data voltage, and a second electrode connected to the seventh node;
a twelfth transistor comprising a control electrode for receiving the write signal, a first electrode connected to the eighth node, and a second electrode connected to the sixth node;
a thirteenth transistor comprising a control electrode for receiving the initialization signal, a first electrode for receiving the first initialization voltage, and a second electrode connected to the sixth node;
a fourteenth transistor comprising a control electrode for receiving the emission signal, a first electrode for receiving the first power voltage, and a second electrode connected to the seventh node;
a fifteenth transistor comprising a control electrode for receiving the emission signal, a first electrode connected to the eighth node, and a second electrode connected to a ninth node;
a sixteenth transistor comprising a control electrode for receiving the light-emitting element initialization signal, a first electrode for receiving the second initialization voltage, and a second electrode connected to the ninth node; and
a second storage capacitor comprising a first electrode for receiving the first power voltage, and a second electrode connected to the sixth node.
Claims 13-14 are rejected as dependent upon claim 12.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Han et al. (US 20220101783 A1).
Regarding claims 1 and 20, Han teaches an electronic device or display device (Title, “Display Panel”) comprising:
a display panel comprising a pixel (Title, Fig. 3, [0054], Display panel 101 comprising pixels 10), and a sweep signal generator configured to generate a sweep signal (Fig. 1, [0063], see a sweep frequency signal Vsweep);
a data driver configured to apply a pixel data voltage (Fig. 1, see data voltage Data_A), a sweep data voltage (Fig. 1, Vsweep), and a pulse width modulation data voltage to the display panel ([0077], pulse width modulation data voltage Data_W);
a gate driver configured to output a write signal (Fig. 1, See write signal Gate_A), a pulse width modulation write signal (Fig. 1, width modulation scan signal Gate_W), an initialization signal (Fig. 1, [0073], See an initialization signal Vinit connected to transistor M8), and a light-emitting element initialization signal (Fig. 1, se Vinit connected to transistor M2 and emitting device E. Note applicant specification [0094] teaches, “the first initialization voltage VINT may be same with the second initialization voltage VAINT”); and
an emission driver configured to apply an emission signal to the display panel (Fig. 1, [0066], see light emitting control sub-circuit 024 which receives a light emitting control signal EM),
wherein the pixel comprises:
a light-emitting element (Fig. 1, light emitting device E);
a pixel circuit block (pixel driving structure of Fig. 1) configured to apply a driving current to the light- emitting element in response to the pixel data voltage and the pulse width modulation write signal, and having a structure that is consistent with a structure of the sweep signal generator (Fig. 1, [0055-0056], See the PAM driving circuit 002 which is configured to control the amplitude of the driving current supplied to the light emitting device E…the pulse width of the driving current finally used by the PAM driving circuit 002 to drive the light emitting device E is identical to the pulse width of the pulse width modulation data voltage Data_W received by the PWM driving circuit 001.” Regarding the limitation “having a structure that is consistent with a structure of the sweep signal generator,” see fig. 1 wherein the pixel driving circuit is able to receive and act on Vsweep so it must be therefore consistent with a structure of the sweep signal generator in a sense that the two structures are compatible in terms of their signal interactions. Examiner advises amending this limitation to define how the structures are “consistent”); and
a pulse width modulation block configured to apply the pulse width modulation write signal to the pixel circuit block based on the pulse width modulation write signal, the sweep signal from the sweep signal generator, and the pulse width modulation data voltage (Fig. 1, See the PWM driving circuit 001 which receives input from Vsweep, Data_W, and width modulation scan signal Gate_W. [0056], “The PWM driving circuit 001 is configured to control the pulse width of the driving current supplied to the light emitting device E to be driven according to the pulse width modulation data voltage Data_W”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 20220101783 A1), as applied to claim 1 above, and further in view of Hwang et al. (US 20230121681 A1).
Regarding claim 15, Han teaches the display device of claim 1, wherein the display panel further comprises first to N-th pixel-rows (Fig. 3 shows N pixel rows).
Han does not teach first to N-th sweep signal generators, N being a positive integer,
wherein the first pixel-row and the first sweep signal generator are at a same row, and
wherein the N-th pixel-row and the N-th sweep signal generator are at a same row.
Hwang teaches a display device wherein a display panel (Title, Fig. 1, [0071], display device 10 includes a display panel 100) further comprises first to N-th pixel-rows (Fig. 1 shows first to N-th pixel rows) and first to N-th sweep signal generator lines (Fig. 1, sweep signal lines SWPL);
wherein the first pixel-row and the first sweep signal generator line are at a same row (Fig. 1, see first row of pixels and SWPL), and
wherein the N-th pixel-row and the N-th sweep signal generator lines are at a same row (Fig. 1, see Nth or final row of pixels and SWPL).
It would have been obvious to one skilled in the art, before the effective filing date of the invention, to modify Han with Hwang as this amounts to combining prior art elements according to known methods to yield predictable results. Han and Hwang include each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable as all elements are known the display art evidenced by the teachings of Han and Hwang.
Regarding the limitation stating N-th sweep signal generators, Hwang figure 1 and [0080] teach a single sweep signal driver 113 driving a plurality of sweep signal lines SWPL. N-th sweep signal generators however is a mere duplication of parts, In reHarza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See MPEP 2144.04, section VI. It would have been obvious to one skilled in the art, before the effective filing date of the invention, to modify Han and Hwang such that there are a plurality or N sweep signal generators as having a plurality of sweep signal generators for each signal line has no patentable significance unless a new and unexpected result is produced.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20230107775 A1, Kim et al. figures 1-2 is related to the limitations of claims 1 and 2.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN P BRITTINGHAM whose telephone number is (571)270-7865. The examiner can normally be reached Monday-Thursday, 10 AM - 6 PM, EST.
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/NATHAN P BRITTINGHAM/Examiner, Art Unit 2629