DETAILED ACTION
The action is responsive to the following communications: the Application filed March 21, 2025 and the information disclosure statement (IDS) filed March 21, 2025. This application is a CON of 17/512,597.
Claims 1-20 are pending. Claims 1, 10 and 19 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 21, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Independent claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over independent claims 1-20 of US Patent No. 10,872,666. Although the claims at issue are not identical, they are not patentably distinct from each other.
Instant Application
US Patent 10,872,666
Comment
Claim 1. An apparatus, comprising: an array of memory cells, each memory cell of the array of memory cells comprising a first transistor comprising a control gate and a floating gate and a second transistor coupled with the floating gate of the first transistor, wherein each memory cell is configured to store a logic state using the first transistor and the second transistor;
a row of clamp memory cells coupled with the array of memory cells, wherein each clamp memory cell of the row of clamp memory cells is coupled with a corresponding source line of a plurality of source lines included in the apparatus, and wherein the row of clamp memory cells is coupled with a clamp line configured to bias the row of clamp memory cells; and
a row of ground memory cells coupled with the array of memory cells and the row of clamp memory cells, wherein each ground memory cell of the row of ground memory cells is coupled with the corresponding source line of the plurality of source lines, wherein the row of ground memory cells is coupled with a ground line configured to bias the row of ground memory cells, and wherein each source line is configured to be biased according to an operation being performed on one or more respective memory cells of the array of memory cells.
Claim 1. An apparatus, comprising:
an array of memory cells, each memory cell of the array of memory cells comprising a first transistor that
includes a control gate and a floating gate and a second transistor connected with the floating gate of the first transistor, wherein each memory cell is configured to store a logic state using the first transistor and second
transistor;
Claim 2. The apparatus of claim 1, further comprising:
a clamp row of memory cells coupled with the array of memory cells, each memory cell of the clamp row of
memory cells comprising a third transistor that includes a floating gate and a fourth transistor connected with
the floating gate of the third transistor, wherein a first node of each of the third transistors is connected with
a corresponding source line of the plurality of source
lines; and
a clamp line connected with a control gate of each of the third transistors and configured to bias the corresponding source line to a voltage of the one digit line based on the operation being a write operation.
6. The apparatus of claim 1, further comprising:
a ground row of memory cells coupled with the array of memory cells, each memory cell of the ground row of
memory cells comprising a fifth transistor that includes a floating gate and a sixth transistor coupled with the
floating gate of the fifth transistor, wherein a first node of each of the fifth transistors is connected with a
corresponding source line of the plurality of source lines; and
a ground line connected with a control gate of each of the fifth transistors and configured to bias the corresponding source line to a ground voltage based on the operation being a read operation.
Note footnote1
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 9-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Inoue et al. (US 8,582,348).
Regarding independent claim 1, Inoue et al. disclose an apparatus, comprising:
an array of memory cells (see e.g., FIG. 3), each memory cell of the array of memory cells comprising a first transistor (FIG. 2: 160) comprising a control gate (C) and a floating gate (FG) and a second transistor (162) coupled with the floating gate (FG) of the first transistor (160), wherein each memory cell is configured to store a logic state using the first transistor and the second transistor (see FIGS. 2-3 and accompanying disclosure);
a row of clamp memory cells (FIG. 3, 1st row, which has 1st cell in FIG. 2 (i.e., this claim is open ended)) coupled with the array of memory cells, wherein each clamp memory cell of the row of clamp memory cells is coupled with a corresponding source line (FIGS. 2-4: SL) of a plurality of source lines included in the apparatus, and wherein the row of clamp memory cells is coupled with a clamp line configured to bias the row of clamp memory cells (see FIGS. 2-4 and accompanying disclosure); and
a row of ground memory cells (FIG. 3, 2nd row, which has 2nd cell in FIG. 2 (i.e., this claim is open ended)) coupled with the array of memory cells and the row of clamp memory cells, wherein each ground memory cell of the row of ground memory cells is coupled with the corresponding source line (FIGS. 2-4: SL) of the plurality of source lines, wherein the row of ground memory cells is coupled with a ground line (FIGS. 2-4: GND) configured to bias the row of ground memory cells, and wherein each source line is configured to be biased according to an operation being performed on one or more respective memory cells of the array of memory cells (see FIGS. 2-4 and accompanying disclosure).
Regarding claim 2, Inoue et al. disclose each clamp memory cell of the row of clamp memory cells comprises a third transistor that includes a floating gate; each ground memory cell of the row of ground memory cells comprises a fourth transistor that includes a floating gate; and each source line of the plurality of source lines is coupled with a respective first transistor of one or more memory cells of the array of memory cells, is coupled with a respective third transistor of a clamp memory cell of the row of clamp memory cells, and is coupled with a respective fourth transistor of a ground memory cell of the row of ground memory cells (see FIG 3, second column with FIG. 2).
Regarding claim 9, Inoue et al. disclose each clamp memory cell of the row of clamp memory cells and each memory cell of the array of memory cells is coupled with a respective digit line of a plurality of digit lines of the apparatus; and each ground memory cell of the row of ground memory cells is electrically isolated from the plurality of digit lines (see FIGS 3-4, second column with FIG. 2).
Regarding method independent claim 10 and its device claim 19, Inoue et al. disclose a method, comprising:
receiving a command (e.g., col. 4, line 2: … writing, storing, and reading data …) to perform an access operation at a memory cell (e.g., FIGS. 1-3) that comprises a first transistor (e.g., FIG. 2: 160) comprising a floating gate (FG) for storing a logic state of the memory cell and a second transistor (162) coupled with the floating gate (FG) of the first transistor, wherein the floating gate is coupled with a source line (SL) that is configured to be biased according to a type of the access operation (see FIGS. 1-3 and accompanying disclosure); and
accessing (e.g., col. 4, line 2: … writing, storing, and reading data …, along with FIG. 4: writing / reading period), based at least in part on receiving the command, the memory cell, wherein accessing the memory cell comprises:
biasing, based at least in part on receiving the command (e.g., FIG. 4: writing), a clamp line (FIG. 4: OSG1) coupled with the source line (SL) to a first voltage (VDD), wherein biasing the clamp line (BL1) applies the first voltage (VDD) to a clamp memory cell (1st CELL in FIG. 2), of a row of clamp memory cells (FIG. 3, 1st row, which has 1st cell in FIG. 2) coupled with the clamp line (OSG1), that is coupled with the source line (SL); and
biasing, based at least in part on receiving the command (e.g., FIG. 4: reading), a ground line (GND) coupled with the source line (SL) to a second voltage (GND), wherein biasing the ground line applies the second voltage (GND) to a ground memory cell (2nd CELL in FIG. 2 for BL2), of a row of ground memory cells (FIG. 3, 2nd row, which has 2nd cell in FIG. 2 (i.e., this claim is open ended)) coupled with the ground line (GND), that is coupled with the source line (SL=GND at reading).
Regarding claim 11, Inoue et al. disclose the first voltage comprises a voltage of a digit line (FIGS. 2-3: BL) associated with the memory cell and the second voltage comprises a ground voltage based at least in part on the type of the access operation being a write operation (e.g., FIG. 4 and accompanying disclosure).
Regarding claim 12, Inoue et al. disclose the first voltage is a zero voltage and the second voltage comprises a ground voltage based at least in part on the type of the access operation being a read operation (FIG. 4).
Regarding claims 13-15, Inoue et al. disclose the clamp memory cell comprises a third transistor comprising a floating gate and a fourth transistor coupled with the floating gate of the third transistor, and wherein a first node of the third transistor is coupled with the source line; biasing the clamp line to the first voltage comprises: activating, based at least in part on the type of the access operation being a write operation, the third transistor to couple the source line with a digit line associated with the first voltage; and a second node of the fourth transistor is coupled with a digit line and a gate of the fourth transistor is coupled with the clamp line (see FIG 3, second column with FIG. 2, and FIG. 4 and accompanying disclosure).
Regarding claims 16-18, Inoue et al. disclose the ground memory cell comprises a fifth transistor comprising a floating gate and a sixth transistor coupled with the floating gate of the fifth transistor, and wherein a first node of the fifth transistor is coupled with the source line; biasing the ground line to the second voltage comprises: activating, based at least in part on the type of the access operation being a read operation, the fifth transistor to couple the source line with a ground voltage, the second voltage comprising the ground voltage; and a second node of the fifth transistor is coupled with a ground voltage (see FIG 3, second column with FIG. 2, and FIG. 4 and accompanying disclosure).
Regarding claim 20, Inoue et al. disclose the first voltage comprises a voltage of a digit line (FIG. 4: BL) associated with the memory cell and the second voltage comprises a ground voltage based at least in part on the type of the access operation being a write operation (see FIG. 4, writing period).
Allowable Subject Matter
Claims 3-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if overcoming nonstatutory double patenting as indicated above rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
1 Re independent claims 1, 10 and 19, claims of US Patent recites all the claimed limitations. The various dependent claims are anticipated by/obvious in view of the conflicting patent.
Prosecution Insights