DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application filed 03/24/2025. Claims 1-20 are pending in the Application, of which Claims 1, 9 and 17 are independent.
Continuity Priority information
The present Application 19088010 filed 03/24/2025 Claims Priority from Provisional Application 63573569, filed 04/03/2024.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. (PgPub. US 20210036716) Pub. Date: 2021-02-04.
Regarding independent Claims 1, 9 and 17, Zhang discloses systems and methods for improving fast fail support for error correction in non-volatile memory, comprising:
a processing device coupled to a memory device to perform operations,
[0028] As shown in FIG. 1, the memory system 100 includes a controller module 120 that includes a memory interface 121 to communicate with the memory module 110, a host interface 126 to communicate with a host (not shown), and a processor 124 to execute firmware-level code.
responsive to determining that an encoded host data read from a memory device contains one or more errors, performing a first set of error correcting code operations, using a plurality of first bit flip threshold values; FIG. 9 illustrates a method for improving error correction in a non-volatile memory.
at operation 910, receiving a codeword from a read operation in a fast fail mode.
at operations 920 -930, initially configuring a maximum number of iterations and a set of values for a plurality of bit flipping thresholds for performing a decoding operation on the codeword, and performing a plurality of decoding iterations, each iteration using a subset of bit flipping thresholds,
performing a second set of error correcting code operations, using a plurality of second bit flip threshold values;
at operations 940-950, calculating a remaining number of iterations and reconfiguring the set of values for the plurality of bit flipping thresholds to restart the decoding operation.
performing a third set of error correcting code operations, using a plurality of third bit flip threshold values,
at operation 960, repeating operations 930 through 950 until the codeword is successfully decoded or the remaining number of iterations is less than or equal to zero. In some embodiments, a convergence rate and a correction capability of the decoding operation is based on the set of values for the plurality of bit-flipping thresholds.
Regarding Claims 2, 3, 10, 11, 18, 19, Zhang discloses returning a respective bit of the encoded host data back to an original value of the respective bit. [0053] As illustrated in FIG. 7, the operation of the bit-flipping decoder includes a syndrome calculation, which updates the number of unsatisfied check nodes (nUCN).
[0055] In some embodiments, the decoder initialization is followed by setting the bit-flipping thresholds of the FSM based on the number of unsatisfied check nodes (nUCN) and a reliability calculation based on nUCN and the current estimate of the hard decision (denoted hardDec in FIG. 7).
Regarding Claims 4, 12, 20, Zhang discloses successfully corrected the one or more errors in the encoded host data, returning host data. at operation 960, repeating operations 930 through 950 until the codeword is successfully decoded or the remaining number of iterations is less than or equal to zero. [0045] In a RAID-1 or similar scenario, the host system will usually prefer to get an error quickly so it can try reading the same data from the other side of the mirror rather than wait for the drive to re-try a read and fall back to slower levels of ECC.
Regarding Claims 5, 13, Zhang discloses wherein the plurality of third bit flip threshold values is optimized; [0020] In previous ECC decoders, the maximum latency is fixed and the decoder is typically optimized to achieve the best error correction performance given that maximum latency. However, with FF mode enabled, embodiments of the disclosed technology take into account the variable maximum latency, thereby optimizing operations when FF is enabled.
Regarding Claims 6-8, 14-16, Zhang discloses determining whether a number of unsatisfied check nodes connected to a respective bit satisfies the second bit flip threshold value; and responsive to determining, flipping the respective bit. [0053] As illustrated in FIG. 7, the operation of the bit-flipping decoder includes a syndrome calculation, which updates the number of unsatisfied check nodes (nUCN). In an example, nUCN is representative of the number of errors in the syndrome. That is, if nUCN=0, then the received codeword has been decoded correctly. On the other hand, if nUCN≠0, then there are errors in the decoded codeword, and processing must continue.
[0055] In some embodiments, the decoder initialization is followed by setting the bit-flipping thresholds of the FSM based on the number of unsatisfied check nodes (nUCN) and a reliability calculation based on nUCN and the current estimate of the hard decision (denoted hardDec in FIG. 7). The thresholds and reliability are used to perform the bit-flipping process for the current iteration, which is followed by a syndrome calculation.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: September 22, 2026
Non-Final Rejection 20260922
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
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