Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed March 24, 2025.
Status of claims to be treated in this office action:
a. Independent: 1, 14
b. Pending: 1-20
Claim Objections
Claim 13 is objected to because of the following informalities:
Regarding claim 13, in lines 4-5, make the following change:
“the search driver is further configured to compare, simultaneously, the data in each set and the data query based on word line search signals in the first and second word lines in each row.”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7-8, 14, and 17 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Wong (US Pat. 6317349 B1).
Regarding independent claim 1, Wong discloses a system (Fig. 8: non-volatile CAM 800; col. 14, line 46) comprising:
a content addressable memory (CAM) array (array 850; col. 14, line 46) comprising:
n rows (Fig 8 depicts two rows of dual CAM cells 810) and m columns (Fig 8 depicts three columns) of CAM elements (810; col. 14, line 47), wherein each column of the m columns comprises a set with n CAM elements (there are two dual CAM cells 810 in each column);
a first word line (word line 820; col. 14, line 51) and a second word line (word line 825; col. 14, line 51) in each row of the n rows; and
a first bit line (bit line 241; col. 14, line 50) and a second bit line (bit line 242; col. 14, lines 50-51) in each column of the m columns; and
a write data driver (Fig. 8: driver 371 or 372; col. 15, lines 13-15: A driver 371 or 372 applies programming voltage Vw (e.g., 5 to 6 volts) to the bit line 241 or 242 coupled to the selected transistor) configured to simultaneously write data to multiple static random-access memory (SRAM) cells of a CAM element (claim 10; col. 21, line 14: the volatile CAM cells comprise SRAM-based CAM cells) in each set in the CAM array (col. 15, lines 18-20: When writing a word to a row of CAM array 850, each CAM cell 810 in the row can be simultaneously programmed) in multiple write steps (col. 15, lines 20-26: In one programming operation, transistors 811 and 813 are initially programmed to one threshold voltage state, and transistors 812 and 814 are initially programmed to the other threshold voltage state. Subsequently, a transistor 813 or 814 in specific CAM cell 810 are programmed to the high threshold voltage state for masking of specific bits in the CAM word; col. 7, lines 17-19: programming of 256 CAM cells can be performed in four steps with 64 CAM cells being programmed in parallel during each step).
Regarding claim 7, Wong discloses the limitations of claim 1, and further:
wherein the CAM array (Fig. 8: 850) is configured to receive a data query, the CAM array further comprising a search driver (row control block 860; col. 15, lines 37-52 describe how row control block controls search in CAM 800) configured to simultaneously compare data in each set of the CAM array to the data query (col. 1, lines 16-24: The match line carries a signal that during a search, indicates whether the word stored in the row matches an input value…A search applies to each pair of bit lines, a pair of complementary binary signals that represent a bit of an input value. Examiner concludes that searching is performed on each pair of bit lines simultaneously) in multiple search steps (col. 4, lines 23-28: A search operation in an array of dual CAM cells uses either the first elements or the second elements. Searching only the first elements compares an input value to all bits of the word without masking. The second elements are for searches that mask one or more bits. Examiner concludes that searching is performed on all the first elements in one search step and all the second elements in another search step).
Regarding claim 8, Wong discloses the limitations of claim 7, and further:
wherein the search driver (Fig. 8: 860) is further configured to simultaneously compare the data in each set to the data query (col. 1, lines 16-24) based on a difference in signals applied to the first bit line and the second bit line for the set (col. 2, lines 28-46: A search biases match lines 120 with a low-current, voltage source and applies complementary binary signals bit lines 141 and 142 to represent the bits of an input value. For the example storage convention described above, if a bit has value 1, an associated bit line 141 is at supply voltage Vcc, and an associated bit line 142 is grounded. If CAM cells 100 stores 1…neither transistor 111 nor 112 conducts, CAM cell 100 does not pull down the voltage on the match line. If CAM cells 100 stores 0…causes transistor 111 to conduct and pull down the voltage on match line 120. A sense amplifier connected to match line 120 senses whether any CAM cells on match line 120 conduct and thereby determines whether the input value matches the stored word. Examiner concludes that the complementary nature, or difference, in the signals on the bit lines is critical to the comparison between the data in the set and the data query).
Independent claim 14 contains limitations that are mostly the same as the
limitations of claim 1, but drafted in method format and those limitations are thus rejected for the same reasons. Specifically, the first limitation of claim 14 is substantially the same as the fifth (last) limitation of claim 1, and the second through fourth limitations of claim 14 are substantially the same as the first through fourth limitations of claim 1.
Regarding claim 17, Wong discloses the limitations of claim 14. The limitations of claim 17 are substantially the same as the limitations of claim 7, and are thus rejected for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Wong (US Pat. 6317349 B1) as applied to claim 1 above, and further in view of Lien et al.
(US Pub. 20020159320 A1; “Lien”) and Yu et al. (US Pub. 20180315473 A1; “Yu”).
Regarding claim 2, Wong discloses the limitations of claim 1. Wong does not disclose:
wherein each CAM element of the CAM elements comprises:
a first static random-access memory (SRAM) cell configured to be written during a first write step; and
a second SRAM cell configured to be written during a second write step.
However, Lien teaches:
wherein each CAM element (Fig. 10: SRAM CAM cell 125F; [0067]) of the CAM elements (ternary CAM array 120F; [0067]) comprises:
a first static random-access memory (SRAM) cell (first SRAM cell 125F1; [0067])
a second SRAM cell (second SRAM cell 125F2; [0067])
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Lien to Wong wherein each CAM element of the CAM elements comprises a first static random-access memory (SRAM) cell and a second SRAM cell in order to reduce soft errors in CAM arrays by refreshing with data from a RAM array (Lien, [0012]).
Also, through Yu:
a first static random-access memory (SRAM) cell (Fig. 3: first 6T SRAM bit cell 46; [0039]) configured to be written during a first write step ([0039]: the SRAM write operation for pre-storing the second input value +1 in the SRAM cell 10B is a two-step operation. The first step is to write the second input value into the first 6T SRAM bit cell 46); and
a second SRAM cell (second 6T SRAM bit cell 48; [0040]) configured to be written during a second write step ([0040]: The second step is to write the second input value into the second 6T SRAM bit cell 48).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Yu to modified Wong wherein the system comprises a first static random-access memory (SRAM) cell configured to be written during a first write step; and a second SRAM cell configured to be written during a second write step in order to improve parallelism of compute-in-memory by activating multiple rows at a time (Yu, [0005]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Wong (US Pat. 6317349 B1) as applied to claim 1 above, and further in view of Yu (US Pub. 20180315473 A1).
Regarding claim 3, Wong discloses the limitations of claim 1. Wong does not disclose:
wherein each SRAM cell of the multiple SRAM cells comprises six transistor (6T) SRAM cells.
However, Yu teaches:
wherein each SRAM cell of the multiple SRAM cells comprises six transistor (6T) SRAM cells (per Fig. 3, the first 6T SRAM bit cell 46 and the second 6T SRAM bit cell 48 each include six transistors) .
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Yu to Wong wherein each SRAM cell of the multiple SRAM cells comprises six transistor (6T) SRAM cells in order to improve parallelism of compute-in-memory by activating multiple rows at a time (Yu, [0005]).
Claims 4-6 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Wong (US Pat. 6317349 B1) as applied to claims 1 and 14 above, respectively, and further in view of Ma et al. (US Pub. 20030016580 A1; “Ma”).
Regarding claim 4, Wong discloses the limitations of claim 1. Wong does not disclose:
wherein the write data driver is further configured to write all '0' states for the CAM array during a first write step.
However, Ma teaches:
wherein the write data driver ([0043]: Although not shown, overwrite circuitry including global write drivers can be configured to write the preset data onto the databuses, or additional drivers can be directly connected to the databuses) is further configured to write all '0' states for the CAM array during a first write step ([0043]: To allow equalization of the bitlines under all four cases according to the present invention, the first and second bitlines of both sub-arrays are overturned, or overwritten with preset complementary logic potential levels from the databuses DBn and DBn+1 prior to equalization…a low logic potential level can be written onto databus DBn+1 after the read operation. Therefore, BLn and BLn* are driven to the low logic potential level via tri-state inverters 113, 114, 115 and 116. Examiner asserts that the writing of all low logic potential levels to the CAM array is analogous to a first write step. Examiner also notes that Fig. 5 depicts one row 110 of the array of ternary CAM cells 100 shown in Fig. 1. See para. [0037]: One row 110 of ternary CAM cells and associated equalization circuits is shown in FIG. 5, where an array can contain a plurality of rows 110 arranged in column, and a plurality of columns arranged side by side)).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Ma to Wong wherein the write data driver is further configured to write all '0' states for the CAM array during a first write step in order to implement a method for high-speed precharging of bitlines in a CAM device (Ma, [0001]).
Regarding claim 5, Wong discloses the limitations of claim 1. Wong does not disclose:
wherein the write data driver is further configured to write all '1' states for the CAM array during a second write step.
However, Ma teaches:
wherein the write data driver ([0043]) is further configured to write all '1' states for the CAM array during a second write step ([0043]: a high logic potential level can be written onto databus DBn…BLn+1 and BLn+1* are driven to the high logic potential level via tri-state inverters 117, 118, 119 and 120).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Ma to Wong wherein the write data driver is further configured to write all '1' states for the CAM array during a second write step in order to implement a method for high-speed precharging of bitlines in a CAM device (Ma, [0001]).
Regarding claim 6, Wong discloses the limitations of claim 1. Wong does not disclose:
wherein the write data driver is further configured to, for each set, apply a high signal to the first bit line in the set and a low signal to the second bit line in the set during a first write step.
However, Ma teaches:
wherein the write data driver ([0043]) is further configured to, for each set (Examiner asserts that, referring to the row depicted in Fig. 5 and the array 100 of Fig. 1, a set is all CAM cells 140 within a column of the array), apply a high signal ([0043]: a high logic potential level) to the first bit line in the set (BLn+1) and a low signal ([0043]: a low logic potential level) to the second bit line in the set (BLn) during a first write step (although Examiner used para. [0043] to describe a first write step including driving bit lines to a low logic level in claim 4 and to describe a second write step including driving bit lines to a high logic level in claim 5, claim 6 only depends on claim 1, so Examiner will define both operations together as a first write step. Further, per para. [0043]: there are several methods for writing preset data to the databuses, which should be apparent to those skilled in the art).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Ma to Wong wherein the write data driver is further configured to, for each set, apply a high signal to the first bit line in the set and a low signal to the second bit line in the set during a first write step in order to implement a method for high-speed precharging of bitlines in a CAM device (Ma, [0001]).
Regarding claim 15, Wong discloses the limitations of claim 14. The limitations of claim 15 are substantially the same as limitations of claim 4, but drafted in method format, and are thus rejected for the same reasons.
Regarding claim 16, Wong discloses the limitations of claim 14. The limitations of claim 16 are substantially the same as limitations of claim 5, but drafted in method format and are thus rejected for the same reasons.
Claims 9, 11, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wong (US Pat. 6317349 B1) as applied to claim 7 above, and further in view of Sywyk et al. (US Pat. 6697275 B1; “Sywyk”).
Regarding claim 9, Wong discloses the limitations of claim 7. Wong discloses a search driver, but does not disclose:
detect matches between the data in each set and the data query during a first search step.
However, Sywyk teaches:
detect matches between the data in each set and the data query during a first search step (col. 8, lines 21-26: in a find match mode, a match circuit/priority encoder 314 can set a match flag (MATCH_FLAG) if a match exists, set a multiple match flag (MULT) if more than one match exists, and activate a priority encoder output (ROM0 to ROMy) corresponding to a highest priority entry having an active match indication output).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Sywyk to Wong wherein there is circuitry to detect matches between the data in each set and the data query during a first search step in order to identify mismatches and efficiently verify matches (Sywyk, col. 3, lines 32-35).
Regarding claim 11, Wong discloses the limitations of claim 7. Wong discloses a search driver, but does not disclose:
detect mismatches between the data in each set and the data query during a second search step.
However, Sywyk teaches:
detect mismatches between the data in each set and the data query during a second search step (col. 8, lines 27-34: in a find mismatch mode, a match circuit/priority encoder 314 can set a match flag (MATCH_FLAG) if a mismatch exists, set a multiple match flag (MULT) if more than one mismatch exists, and activate a priority encoder output (ROM0 to ROMy) corresponding to a highest priority entry having an active mismatch indication. Thus, a first mismatch may be determined. This mismatch may indicate an error).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Sywyk to Wong wherein there is circuitry to detect mismatches between the data in each set and the data query during a second search step in order to identify mismatches and efficiently verify matches (Sywyk, col. 3, lines 32-35).
Regarding claim 18, Wong discloses the limitations of claim 17. The limitations of claim 18 are substantially the same as the limitations of claim 9, but drafted in method format and are thus rejected for the same reasons.
Regarding claim 20, Wong discloses the limitations of claim 17. The limitations of claim 20 are substantially the same as the limitations of claim 11, but drafted in method format and are thus rejected for the same reasons.
Claims 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Wong (US Pat. 6317349 B1) and Sywyk (US Pat. 6697275 B1) as applied to claims 9 and 18 above, respectively, and further in view of Chen et al. (CN 113539327 A; “Chen”).
Regarding claim 10, Wong and Sywyk together disclose the limitations of claim 9. Further, through Sywyk:
wherein the CAM array (col. 1, lines 25-26: A typical CAM can store the data values of a look-up table in one or more CAM cell arrays)
a number of detected matches (col. 8, lines 21-26).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Sywyk to modified Wong wherein there is a CAM array and a number of detected matches is determined in order to identify mismatches and efficiently verify matches (Sywyk, col. 3, lines 32-35).
Neither Wong nor Sywyk discloses:
wherein the array is configured to set a value of a bit line voltage based on a number of detected matches.
However, Chen teaches:
wherein the array (Fig. 7: phase change memory array; [n0025], p.16) is configured to set a value of a bit line voltage based on a number of detected matches ([n0036], p. 26, lines 3-6: Based on the word line voltage set by the input image, a read current Ir is applied to the bit line. The bit line output voltage is compared. If all matching models have no conducting low impedance cells, the corresponding bit line voltage is higher. The lower the matching degree, the more conducting low-impedance cells there are, and the lower the output bit line voltage).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Chen to modified Wong wherein the array is configured to set a value of a bit line voltage based on a number of detected matches in order to make the data matching calculations and data retrieval more efficient (Chen, [n0004], p.5).
Regarding claim 19, Wong and Sywyk together disclose the limitations of claim 18. The limitations of claim 19 are substantially the same as the limitations of claim 10, but drafted in method format and are thus rejected for the same reasons.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Wong (US Pat. 6317349 B1) as applied to claim 7 above, and further in view of Bettman et al. (US Pat. 7173837 B1; “Bettman”).
Regarding claim 12, Wong discloses the limitations of claim 7. Wong does not disclose:
wherein the CAM array is configured to apply word line write signals to the first word line and the second word line during a first write step and a second write step.
However, Bettman teaches:
wherein the CAM array (col. 6, lines 60-61: CAM array containing a CAM cell 300) is configured to apply word line write signals to the first word line (Fig. 1: word line WL1 116; col. 5, line 19) and the second word line (word line WL2 114; col. 5, lines 9-10) during a first write step (col. 5, lines 61-66: In a write operation, data can be written into storage sections (102-0 and 102-1) according to a two-step process involving a pre-write step and a write data step. In a pre-write step, word line WL1 116 can enable pre-write devices 112-0 and 112-1 while word line WL2 114 disables access devices (110-0 and 110-1)) and a second write step (col. 6, lines 4-6: In a write data step, word line WL1 116 can disable pre-write devices (112-0 and 112-1) while word line WL2 114 enables access devices (110-0 and 110-1)).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Bettman to Wong wherein the CAM array is configured to apply word line write signals to the first word line and the second word line during a first write step and a second write step in order to implement a device with wider compare data lines for faster compare operations (Bettman, col. 4, lines 19-21).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Wong (US Pat. 6317349 B1) and Bettman (US Pat. 7173837 B1) as applied to claim 12 above, and further in view of Chiang (US Pub. 20230377651 A1) and Shinohara (JP 2004348845 A).
Regarding claim 13, Wong and Bettman together disclose the limitations of claim 12. Neither Wong nor Bettman discloses:
wherein the CAM array is configured to apply word line search signals to the first word line and the second word line during at least a portion of two search steps, wherein the word line search signals are lower than the word line write signals, and wherein the search driver is further configured to compare, simultaneously, the data based to the data query based on word line search signals in the first and second word lines in each row.
However, Chiang teaches:
wherein the CAM array ([0012]: CAM arrays) is configured to apply word line search signals to the first word line and the second word line during at least a portion of two search steps ([0021]: Programming the predetermined search results is a two-step process. For the first step of the two-step process, the word line driver 104 applies a first voltage to the gates of both the corresponding first ferroelectric memory element 102a and the corresponding second ferroelectric memory element 102b via a corresponding first word line (e.g., WL.sub.1,1) and a corresponding second word line (e.g., WL.sub.1,1′) of the plurality of word lines, respectively; [0022]: As for the second step of the two-step process, to set the data state to the first state, a second voltage having an opposite polarity and approximately half the magnitude of the first voltage is applied to the gate of the second ferroelectric memory element 102b via the second word line. Examiner concludes that word line search signals are applied to both word lines during the first step and a word line search signal is applied to only the second word line during the second step. Para. [0021] therefore teaches the language of the claim since [0021] teaches one step, which is a portion of the two steps),
and wherein the search driver (Fig. 1: word line driver 104; [0024]: To search for the first data state in the CAM unit, the word line driver 104 applies a first search voltage…to the gate of the corresponding first ferroelectric memory element 102a via a corresponding first word line, and a second search voltage…to the gate of the corresponding second ferroelectric memory element 102b) is further configured to compare, simultaneously, the data based to the data query based on word line search signals in the first and second word lines in each row ([0051]: A CAM unit of the plurality of CAM units includes a first ferroelectric memory element, a plurality of word lines extending along the rows and configured to provide a search query to the plurality of CAM units for bitwise comparison between the search query and the data states of the plurality of CAM units).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Chiang to modified Wong wherein the CAM array is configured to apply word line search signals to the first word line and the second word line during at least a portion of two search steps, and wherein the search driver is further configured to compare, simultaneously, the data based to the data query based on word line search signals in the first and second word lines in each row in order to provide a CAM device with a smaller footprint and lower power consumption (Chiang, [0013]).
Also, Shinohara teaches:
wherein the word line search signals are lower than the word line write signals ([0017]: During the search operation, the word line WL is set to an L level; [0028]-[0029]: when the word line WL is selected…the output voltage Vbout (boost voltage) from the boost voltage generation circuit 4 is output to the word line WL. This voltage Vbout is a voltage generated by a boost circuit (not shown) in the boost voltage generation circuit 4, and since it is at a higher potential than the power supply voltage Vcc, the word line WL is boosted above the power supply voltage Vcc. Examiner concludes that the word line search signal is a low “L level” and the word line write signal is boosted above a power supply voltage Vcc and is therefore high),
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Shinohara to modified Wong wherein the word line search signals are lower than the word line write signals in order to provide a CAM on a low-voltage SOI substrate (Shinohara, [0001]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIZABETH ROSE AGGER whose telephone number is (571)270-0250. The examiner can normally be reached Mon-Fri, 8am-5pm.
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/E.R.A./Examiner, Art Unit 2824
/SULTANA BEGUM/Primary Examiner, Art Unit 2824
9/30/2026
