DETAILED ACTION
This action is in response to the application filed on 3/24/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1 is rejected on the ground of non-statutory double patenting as being unpatentable over Claim 1 of U.S. Patent No. 11632048. Although the claims at issue are not identical, they are not patentably distinct from each other because: Claim 1 of the instant application states: a voltage regulator comprising: a power supply voltage node; a power supply reference node; an output node; a plurality of phase circuits, wherein each phase circuit of the plurality of phase circuits comprises: at least one p-type transistor coupled to the power supply voltage node; at least one n-type transistor coupled to the power supply reference node; and an inductor comprising a first terminal coupled exclusively to the at least one p-type transistor and the at least one n-type transistor, and a second terminal coupled to the output node; and a control circuit configured to, responsive to a power state signal, enable a predetermined number of phase circuits of the plurality of phase circuits, wherein the inductors of the plurality of phase circuits are an entirety of the inductors of the voltage regulator coupled to the output node and comprise a same inductor type. Claim 1 of US Patent 11632048 states: voltage regulator comprising: an output node; a control circuit configured to receive a power state signal from a load circuit coupled to the output node and output a control signal based on the power state signal; and a power stage comprising a plurality of phase circuits, each phase circuit of the plurality of phase circuits comprising: one or more p-type transistors coupled to a power supply voltage node; one or more n-type transistors coupled to a power supply reference node; and an inductor comprising a first terminal coupled exclusively to the one or more p-type transistors and the one or more n-type transistors, and a second terminal coupled to the output node, wherein the power stage is configured to enable a phase circuit of the plurality of phase circuits responsive to the control signal, the plurality of phase circuits is an entirety of phase circuits coupled to the control circuit, the inductors of the plurality of phase circuits are an entirety of the inductors coupled to the output node, and the inductor of each phase circuit of the plurality of phase circuits is a same inductor type.
Allowable Subject Matter
Claims 2-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 9-20 are allowed.
The following is an examiner’s statement of reasons for allowance: Regarding claim 9, the prior art fails to teach or disclose a voltage regulator comprising: wherein each phase circuit of the plurality of phase circuits comprises: a plurality of p-type transistors coupled to the power supply voltage node; a plurality of n-type transistors coupled to the power supply reference node; and an inductor comprising a first terminal coupled exclusively to the plurality of p-type transistors and the plurality of n-type transistors, and a second terminal coupled to the output node; and a control circuit configured to, responsive to a power state signal, enable a predetermined number of phase circuits of the plurality of phase circuits and predetermined p-type transistors of the plurality of p-type transistors and n-type transistors of the plurality of n-type transistors of each enabled phase circuit of the plurality of phase circuits, wherein the inductors of the plurality of phase circuits are an entirety of the inductors of the voltage regulator coupled to the output node and comprise a same inductor type, in combination with all the limitations set forth in claim 9. Regarding claim 16, the prior art fails to teach or disclose a method of regulating a voltage, the method comprising: receiving a power state signal at a control circuit of a voltage regulator comprising a plurality of phase circuits coupled to a power supply voltage node, a power supply reference node, and an output node; and in response to the power state signal, using the control circuit to enable each phase circuit of a predetermined number of phase circuits of the plurality of phase circuits by at least one of: coupling the output node to the power supply voltage node through at least one p-type transistor of the phase circuit and an inductor of the phase circuit, or coupling the output node to the power supply reference node through at least one n-type transistor of the phase circuit and the inductor, wherein a first terminal of the inductor of each phase circuit is coupled exclusively to the at least one p-type transistor and the at least one n-type transistor, and the inductors of the phase circuits of the plurality of phase circuits are an entirety of the inductors of the voltage regulator coupled to the output node and comprise a same inductor type. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEFFREY A GBLENDE whose telephone number is (571)270-5472. The examiner can normally be reached M-F 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JEFFREY A GBLENDE/Primary Examiner, Art Unit 2838
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