DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 8 is objected to because of the following informalities: lines 4-5 and 8-9 of claim 8 contains the phrase “the gate end cap structure” which appears to be a copy and paste typo from claim 1 where Applicant replaced the ‘gate end cap structure’ with the ‘second isolation structure’ but for the two instances cited above. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0134797 A1 to Lin et al. (hereinafter “Lin”).
Regarding claim 1, Lin discloses an integrated circuit structure, comprising:
a fin having a portion protruding above a trench isolation structure (integrated circuit structure having nanostructure stacks 1302 in fin structure disposed above isolation structures 402; Fig. 20B; paragraphs [0012], [0037], [0098]);
a gate end cap structure on the trench isolation structure, the gate end cap structure laterally spaced apart from the fin (dielectric fins 502 on isolation structures 402 and laterally spaced apart from stacks 1302; Fig. 20B; paragraph [0043]);
a gate dielectric material layer over a top of the fin and along sides of the fin, the gate dielectric material layer on the trench isolation structure, and the gate dielectric material layer along a side of the gate end cap structure (gate dielectric structures 1808 disposed over top and sides of stacks 1302, over isolation structures 402, and along sides of dielectric fins 502; Fig. 20B; paragraph [0137]);
a conductive gate layer over the gate dielectric material layer (bottom portion of gate electrode structures 1502 within stacks 1302 is disposed over gate dielectric structures 1808; Fig. 20B);
a conductive gate fill material layer over the conductive gate layer (top portion of gate electrode structures 1502 disposed over bottom portion thereof; Fig. 20B);
a dielectric gate cap over the gate fill material layer (fourth dielectric layer 1506 disposed over top portion of gate electrodes 1502; Fig. 20B); and
a dielectric gate plug on the gate end cap structure, the dielectric gate plug laterally adjacent to the conductive gate fill material, the dielectric gate plug laterally adjacent to and in contact with the dielectric gate cap, and the dielectric gate plug having an uppermost surface at a same level as an uppermost surface of the dielectric gate cap (fifth dielectric layer 1902 disposed over isolation structures 402, laterally adjacent top portion of gate electrode structures 1502, and laterally adjacent and in contact with fourth dielectric layer 1506, where top surface of layer 1902 is disposed at same level as top surface of layer 1506; Fig. 20B), wherein the gate dielectric material layer extends along a side of the dielectric gate plug from a top of the gate end cap structure to a bottom of the dielectric gate cap (gate dielectric structures 1808 extending along side of layer 1902 from top of fins 502 to bottom of layer 1506; Fig. 20B).
Regarding claim 2, Lin discloses the integrated circuit structure of claim 1, wherein the conductive gate layer is on the gate dielectric material layer along the side of the gate end cap structure (bottom portion of gate electrode structures 1502 disposed over gate dielectric structures 1808 adjacent a side of fins 502; Fig. 20B).
Regarding claim 3, Lin discloses the integrated circuit structure of claim 2, wherein the conductive gate layer is on the gate dielectric material layer along the side of the dielectric gate plug (bottom portion of gate electrode structures 1502 disposed over gate dielectric structures 1808 adjacent a side of layer 1902; Fig. 20B).
Regarding claim 4, Lin discloses the integrated circuit structure of claim 1, further comprising: one or more nanowires over the fin (nanostructure stacks 1302 may include nanowires disposed over portions of the fin structure; Fig. 20; paragraph [0100]).
Regarding claim 5, Lin discloses the integrated circuit structure of claim 1, wherein the dielectric gate plug has a lateral width less than a lateral width of the gate end cap structure where the dielectric gate plug meets the gate end cap structure (layer 1902 has lateral width smaller than that of the fins 502 at the place where they vertically overlap; Fig. 20B).
Regarding claim 6, Lin discloses the integrated circuit structure of claim 1, wherein the gate end cap structure has an uppermost surface above an uppermost surface of the fin (fins 502 have top surface above that of nanostructure stacks 1302; Fig. 20B).
Regarding claim 7, Lin discloses the integrated circuit structure of claim 1, wherein the gate end cap structure has a bottommost surface above an uppermost surface of the trench isolation structure (fins 502 have bottom surface above upper surface of isolation structures 402; Fig. 20B).
Regarding claim 8, Lin discloses an integrated circuit structure, comprising:
a three-dimensional body having a portion protruding above a first isolation structure (integrated circuit structure having nanostructure stacks 1302 in fin structure disposed above isolation structures 402; Fig. 20B; paragraphs [0012], [0037], [0098]);
a second isolation structure on the first isolation structure, the gate end cap structure laterally spaced apart from the three-dimensional body (dielectric fins 502 on isolation structures 402 and laterally spaced apart from stacks 1302; Fig. 20B; paragraph [0043]);
a gate dielectric material layer over a top of the three-dimensional body and along sides of the three-dimensional body, the gate dielectric material layer on the first isolation structure, and the gate dielectric material layer along a side of the gate end cap structure (gate dielectric structures 1808 disposed over top and sides of stacks 1302, over isolation structures 402, and along sides of dielectric fins 502; Fig. 20B; paragraph [0137]);
a conductive gate layer over the gate dielectric material layer (bottom portion of gate electrode structures 1502 within stacks 1302 is disposed over gate dielectric structures 1808; Fig. 20B);
a conductive gate fill material layer over the conductive gate layer (top portion of gate electrode structures 1502 disposed over bottom portion thereof; Fig. 20B);
a dielectric gate cap over the gate fill material layer (fourth dielectric layer 1506 disposed over top portion of gate electrodes 1502; Fig. 20B); and
a dielectric gate plug on the second isolation structure, the dielectric gate plug laterally adjacent to the conductive gate fill material, the dielectric gate plug laterally adjacent to and in contact with the dielectric gate cap, and the dielectric gate plug having an uppermost surface at a same level as an uppermost surface of the dielectric gate cap (fifth dielectric layer 1902 disposed over isolation structures 402, laterally adjacent top portion of gate electrode structures 1502, and laterally adjacent and in contact with fourth dielectric layer 1506, where top surface of layer 1902 is disposed at same level as top surface of layer 1506; Fig. 20B), wherein the gate dielectric material layer extends along a side of the dielectric gate plug from a top of the second isolation structure to a bottom of the dielectric gate cap (gate dielectric structures 1808 extending along side of layer 1902 from top of fins 502 to bottom of layer 1506; Fig. 20B).
Regarding claim 9, Lin discloses the integrated circuit structure of claim 8, wherein the conductive gate layer is on the gate dielectric material layer along the side of the second isolation structure (bottom portion of gate electrode structures 1502 disposed over gate dielectric structures 1808 adjacent a side of fins 502; Fig. 20B).
Regarding claim 10, Lin discloses the integrated circuit structure of claim 9, wherein the conductive gate layer is on the gate dielectric material layer along the side of the dielectric gate plug (bottom portion of gate electrode structures 1502 disposed over gate dielectric structures 1808 adjacent a side of layer 1902; Fig. 20B).
Regarding claim 11, Lin discloses the integrated circuit structure of claim 8, further comprising: one or more nanowires over the three-dimensional body (nanostructure stacks 1302 may include nanowires disposed over portions of the fin structure; Fig. 20; paragraph [0100]).
Regarding claim 12, Lin discloses the integrated circuit structure of claim 8, wherein the dielectric gate plug has a lateral width less than a lateral width of the second isolation structure where the dielectric gate plug meets the second isolation structure (layer 1902 has lateral width smaller than that of the fins 502 at the place where they vertically overlap; Fig. 20B).
Regarding claim 13, Lin discloses the integrated circuit structure of claim 8, wherein the second isolation structure has an uppermost surface above an uppermost surface of the three-dimensional body (fins 502 have top surface above that of nanostructure stacks 1302; Fig. 20B).
Regarding claim 14, Lin discloses the integrated circuit structure of claim 8, wherein the second isolation structure has a bottommost surface above an uppermost surface of the first isolation structure (fins 502 have bottom surface above upper surface of isolation structures 402; Fig. 20B).
Regarding claim 15, Lin discloses a method of fabricating an integrated circuit structure, the method comprising:
forming a fin having a portion protruding above a trench isolation structure (forming integrated circuit structure having nanostructure stacks 1302 in fin structure disposed above isolation structures 402; Fig. 20B; paragraphs [0012], [0037], [0098]);
forming a gate end cap structure on the trench isolation structure, the gate end cap structure laterally spaced apart from the fin (forming dielectric fins 502 on isolation structures 402 and laterally spaced apart from stacks 1302; Fig. 20B; paragraph [0043]);
forming a gate dielectric material layer over a top of the fin and along sides of the fin, the gate dielectric material layer on the trench isolation structure, and the gate dielectric material layer along a side of the gate end cap structure (forming gate dielectric structures 1808 disposed over top and sides of stacks 1302, over isolation structures 402, and along sides of dielectric fins 502; Fig. 20B; paragraph [0137]);
forming a conductive gate layer over the gate dielectric material layer (forming bottom portion of gate electrode structures 1502 within stacks 1302 is disposed over gate dielectric structures 1808; Fig. 20B);
forming a conductive gate fill material layer over the conductive gate layer (forming top portion of gate electrode structures 1502 disposed over bottom portion thereof; Fig. 20B);
forming a dielectric gate cap over the gate fill material layer (fourth dielectric layer 1506 disposed over top portion of gate electrodes 1502; Fig. 20B); and
forming a dielectric gate plug on the gate end cap structure, the dielectric gate plug laterally adjacent to the conductive gate fill material, the dielectric gate plug laterally adjacent to and in contact with the dielectric gate cap, and the dielectric gate plug having an uppermost surface at a same level as an uppermost surface of the dielectric gate cap (forming fifth dielectric layer 1902 disposed over isolation structures 402, laterally adjacent top portion of gate electrode structures 1502, and laterally adjacent and in contact with fourth dielectric layer 1506, where top surface of layer 1902 is disposed at same level as top surface of layer 1506; Fig. 20B), wherein the gate dielectric material layer extends along a side of the dielectric gate plug from a top of the gate end cap structure to a bottom of the dielectric gate cap (forming gate dielectric structures 1808 extending along side of layer 1902 from top of fins 502 to bottom of layer 1506; Fig. 20B).
Regarding claim 16, Lin discloses the method of claim 15, wherein the conductive gate layer is on the gate dielectric material layer along the side of the gate end cap structure (bottom portion of gate electrode structures 1502 disposed over gate dielectric structures 1808 adjacent a side of fins 502; Fig. 20B).
Regarding claim 17, Lin discloses the method of claim 16, wherein the conductive gate layer is on the gate dielectric material layer along the side of the dielectric gate plug (bottom portion of gate electrode structures 1502 disposed over gate dielectric structures 1808 adjacent a side of layer 1902; Fig. 20B).
Regarding claim 18, Lin discloses the method of claim 15, further comprising: forming one or more nanowires over the fin (nanostructure stacks 1302 may include nanowires disposed over portions of the fin structure; Fig. 20; paragraph [0100]).
Regarding claim 19, Lin discloses the method of claim 15, wherein the dielectric gate plug has a lateral width less than a lateral width of the gate end cap structure where the dielectric gate plug meets the gate end cap structure (layer 1902 has lateral width smaller than that of the fins 502 at the place where they vertically overlap; Fig. 20B).
Regarding claim 20, Lin discloses the method of claim 15, wherein the gate end cap structure has an uppermost surface above an uppermost surface of the fin (fins 502 have top surface above that of nanostructure stacks 1302; Fig. 20B).
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2022/0123115 A1 to Chou et al. and US 2016/0071846 A1 to Wen et al. each discloses integrated circuits having related fin and dielectric structures arranged similar to the presently claimed invention.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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