DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-10 and 20 are currently pending and prosecuted.
Election/Restrictions
Claims 11-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species B, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 12 march 2026.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 18/661,597, filed on 4 June 2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 24 March 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 9-10 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al., US PG-Pub 2021/0201759, hereinafter Cho.
Regarding Claim 1, Cho teaches a pixel (pixel PXL) comprising:
a light-emitting element (light emitting element EL);
a first transistor (driving transistor DT) including a first electrode, a second electrode, and a gate electrode (Fig. 3, and corresponding descriptions; [0051]);
a third transistor (fourth switching transistor T3) connected between the second electrode of the first transistor and the gate electrode of the first transistor (Fig. 3, and corresponding descriptions; [0059]) and including a gate electrode connected with a first scan line (first scan line A; Fig. 3, and corresponding descriptions; [0059]);
a fifth transistor (second switching transistor T2) connected between the first electrode of the first transistor (Fig. 3, and corresponding descriptions; [0057]) and a second node (second node N2) and including a gate electrode connected with the first scan line (Fig. 3, and corresponding descriptions; [0057]); and
a capacitor (first storage capacitor Cst1) connected between the gate electrode of the first transistor and the second node (Fig. 3, and corresponding descriptions; [0062]),
wherein, during a compensation period, a driving voltage is transferred to the gate electrode of the first transistor through the third transistor and the driving voltage is transferred through the fifth transistor to the second node (Figs. 3-4, 6A-6B and 8A-8B, and corresponding descriptions; [0064]-[0065], [0074], [0076]).
Regarding Claim 2, Cho teaches the pixel of claim 1, wherein, during the compensation period, the third transistor and the fifth transistor are turned on in response to a first scan signal transferred from the first scan line (Figs. 3-4, 6A-6B and 8A-8B, and corresponding descriptions; [0064]-[0065], [0074], [0076]).
Regarding Claim 3, Cho teaches the pixel of claim 1, wherein, during an initialization period, an initialization voltage is transferred to the gate electrode of the first transistor through the third transistor (Figs. 3-4, 6A-6B and 8A-8B, and corresponding descriptions; [0064]-[0065], [0074], [0076]).
Regarding Claim 4, Cho teaches the pixel of claim 1, further comprising:
an eighth transistor (fifth switching transistor T5) connected between a driving voltage line and the first electrode of the first transistor (Fig. 3, and corresponding descriptions; [0060]) and including a gate electrode connected with a first emission line (Fig. 3, and corresponding descriptions; [0060], emission line E),
wherein, during the compensation period, a first scan signal provided to the first scan line and a first emission signal provided to the first emission line are at an active level (Figs. 3-4 and 10A-10B, and corresponding descriptions; [0064]-[0065], [0082]-[0084]).
Regarding Claim 9, Cho teaches the pixel of claim 1, further comprising:
a second transistor (third switching transistor T3) connected between a data line and the second node (Fig. 3, and corresponding descriptions; [0058]) and including a gate electrode connected with a third scan line (Fig. 3, and corresponding descriptions; [0058], third scan line C).
Regarding Claim 10, Cho teaches the pixel of claim 1, further comprising:
a ninth transistor connected between the first electrode of the first transistor and a bias voltage line and including a gate electrode connected with a fourth scan line.
Regarding Claim 20, Cho teaches an electronic device (electroluminescent display device) comprising:
a display panel (display panel 10) including a pixel (pixel PXL) connected with a plurality of scan lines (plurality of gate lines 15), a plurality of emission lines (plurality of data lines 14), and a data line (emission line; [0033], “a data voltage supplied to each data line 14 and an initialization voltage supplied to an initialization voltage line, respectively, an emission line for supplying an emission signal adapted to enable light emission of the corresponding pixels PXL”);
a scan driving circuit (gate driving circuit 13) configured to drive the plurality of scan lines in response to a scan control signal ([0042]-[0043]);
a driving controller (data driving circuit 12) configured to output the scan control signal ([0040]-[0041]); and
a voltage generator (power circuit 16) configured to generate a driving voltage and an initialization voltage ([0044]),
wherein the pixel includes:
a light-emitting element (light emitting element EL);
a first transistor (driving transistor DT) including a first electrode, a second electrode, and a gate electrode (Fig. 3, and corresponding descriptions; [0051]);
a third transistor (fourth switching transistor T3) connected between the second electrode of the first transistor and the gate electrode of the first transistor (Fig. 3, and corresponding descriptions; [0059]) and including a gate electrode connected with a first scan line among the plurality of scan lines (first scan line A; Fig. 3, and corresponding descriptions; [0059]);
a fifth transistor (second switching transistor T2) connected between the first electrode of the first transistor (Fig. 3, and corresponding descriptions; [0057]) and a second node (second node N2) and including a gate electrode connected with the first scan line (Fig. 3, and corresponding descriptions; [0057]); and
a capacitor (first storage capacitor Cst1) connected between the first node and the second node (Fig. 3, and corresponding descriptions; [0062]),
wherein, during a compensation period, the driving voltage is transferred to the gate electrode of the first transistor through the third transistor and the driving voltage is transferred through the fifth transistor to the second node (Figs. 3-4 and 6A-6B, and corresponding descriptions; [0064]-[0065], [0074]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Cho as applied to claim 1 above, and further in view of Park et al., US PG-Pub 2021/0256908, hereinafter Park.
Regarding Claim 5, Cho teaches the pixel of claim 1, further comprising:
a sixth transistor (sixth switching transistor T6) connected between the second electrode of the first transistor and the light-emitting element (Fig. 3, and corresponding descriptions; [0060]) and including a gate electrode connected with an emission line (Fig. 3, and corresponding descriptions; [0060]; emission line E); and
a seventh transistor (seventh switching transistor T7) connected between the light-emitting element and an initialization voltage line (Fig. 3, and corresponding descriptions; [0061], initialization voltage line Vint) and including a gate electrode connected with a second scan line (Fig. 3, and corresponding descriptions; [0061], second scan line B).
However, Cho does not explicitly teach the sixth transistor including a gate electrode connected with a second emission line.
Park teaches the sixth transistor (Park: sixth transistor T6) including a gate electrode connected with a second emission line (Park: Fig. 2, and corresponding descriptions; [0092]-[0094], previous emission control line EL[i-k], which is different from emission control line EL[i]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the invention to incorporate the second emission line taught by Park into the device taught by Cho in order to shift the control signal by k horizontal periods (Park: [0093]), thereby providing a higher quality display device for the user.
Regarding Claim 6, Cho, as modified by Park, teaches the pixel of claim 5, wherein, during an initialization period, the third transistor the sixth transistor and the seventh transistor are turned on such that an initialization voltage from the initialization voltage line is transferred to the gate electrode of the first transistor (Cho: Figs. 3-4, 6A-6B, 8A-8B and 10A-10B, and corresponding descriptions; [0064]-[0065], [0074], [0076]-[0077], [0082]-[0084]).
Regarding Claim 7, Cho, as modified by Park, teaches the pixel of claim 6, wherein, during the initialization period, a first scan signal (Cho: first scan signal SN(n-2)) provided to the first scan line (Cho: [0059]), a second scan signal (Cho: second scan signal SP(n-2)) provided to the second scan line (Cho: [0061]), and a second emission signal (Park: previous emission control signal) provided to the second emission line (Park: [0092]-[0094]) are at an active level (Cho: Figs. 3-4, 6A-6B, 8A-8B and 10A-10B, and corresponding descriptions; Park: [0092]-[0094]).
Regarding Claim 8, Cho, as modified by Park, teaches the pixel of claim 7, wherein the initialization period and the compensation period are repeated in turn plural times (Cho: Figs. 3-4, and corresponding descriptions; [0069]-[0071]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHEN T REED whose telephone number is (571)272-7234. The examiner can normally be reached M-F: 0800-1800.
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STEPHEN T. REED
Primary Examiner
Art Unit 2627
/Stephen T. Reed/Primary Examiner, Art Unit 2627