Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/25/25 has been considered by the examiner.
Drawings
The drawings were received on 3/24/25. These drawings are acceptable.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 21-29, 34, 35 and 40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5, 11, 15-22 and 24 of U.S. Patent No. 12,259,777. Although the claims at issue are not identical, they are not patentably distinct from each other because in claims 21-27 the limitations are fully contained within the claims 15-21 however the claims are directed to “non-transitory computer-readable medium to include instructions, which when executed by a system, causes the system to” to implement the method of the patented claims 15-21. In claims 28 and 35, the only limitation not fully contained within the patented claims is “receive an indication of correctable errors (CEs)” however both the pending and patented claims recite “(CEs) detected by an on-die error checking and correction (ECC) circuit of a memory device from among the multiple memory devices, wherein the indication of CEs detected by the on-die ECC circuit of the memory device were provided to a memory controller by the memory device” (pending claim emphasis added) and “(CEs) detected by an on-die error checking and correction (ECC) circuit of the memory devices and provided to the controller by the memory devices” (patented claims). Therefore, since the correctable errors have been provided, it would have been obvious to a person having ordinary skill in the art at the time of filing of the present application to have understood that something internal provided would be received, given the patented claims this would have been obvious.
See table below:
19088887
US 12259777
21. At least one non-transitory computer-readable medium to include instructions, which when executed by a system, causes the system to:
receive an indication of correctable errors (CEs) detected by an on-die error checking and correction (ECC) circuit of a memory device and provided to a controller by the memory device;
correlate a hardware configuration of the memory device with the detected CEs; and
predict an uncorrectable error (UE) based on correlation of the hardware configuration with the detected CEs.
15. A method for predicting memory device failure, comprising:
receiving an indication of correctable errors (CEs) detected by an on-die error checking and correction (ECC) circuit of a memory device and provided to a controller by the memory device; correlating a hardware configuration of the memory device with the detected CEs; and predicting an uncorrectable error (UE) based on correlation of the hardware configuration with the detected CEs.
22. The at least one non-transitory computer-readable medium of claim 21, wherein the memory device comprises a dual inline memory module (DIMM).
16. The method of claim 15,
wherein the memory device comprises a dual inline memory module (DIMM).
23. The at least one non-transitory computer-readable medium of claim 21, wherein to correlate a fault corresponding to the hardware configuration of the memory device with the detected CEs comprises to correlate a hardware structure of the memory device with the detected CEs, to include correlating structure-specific fault indicators for the memory device.
17. The method of claim 15,
wherein correlating a fault corresponding to the hardware configuration of the memory device with the detected CEs comprises correlating a hardware
structure of the memory device with the detected CEs, including correlating structure-specific fault indicators for the memory device.
24. The at least one non-transitory computer-readable medium of claim 23, wherein to predict the UE comprises to generate a row fault predictor based on a pattern of CEs detected in a row of the memory device.
18. The method of claim 17,
wherein predicting the UE comprises generating a row fault predictor based on a pattern of CEs detected in a row of the memory device.
25. The at least one non-transitory computer-readable medium of claim 23, wherein to predict the UE comprises the instructions to further cause the system to generate a column fault predictor based
on a pattern of CEs detected in a column of the memory device.
19. The method of claim 17,
wherein predicting the UE comprises
generating a column fault predictor based on a pattern of CEs detected in a column of the memory device.
26. The at least one non-transitory computer-readable medium of claim 23, wherein to predict the UE comprises to generate a bank fault predictor based on
a pattern of CEs detected in a bank of the memory device.
20. The method of claim 17,
wherein predicting the UE comprises generating a bank fault predictor based on a pattern of CEs detected in a bank of the memory device.
27. The at least one non-transitory computer-readable medium of claim 21, wherein to predicting the UE comprises identifying a failure threshold based on a failure prediction model built for the memory device.
21. The method of claim 15,
wherein predicting the UE comprises identifying a failure threshold based on a failure prediction model built for the memory device.
28. An apparatus comprising:
a substrate; and
circuitry disposed on the substrate,
the circuitry to:
receive an indication of correctable errors (CEs) detected by an on-die error checking and correction (ECC) circuit of a memory device and provided to a controller by the memory device;
correlate a hardware configuration of the memory device with the detected CEs;
and
predict an uncorrectable error (UE) based on correlation of the hardware configuration with the detected CEs.
1. An apparatus to predict memory device failure, comprising:
a substrate; and
a controller disposed on the substrate,
the controller to
execute a memory failure prediction engine, the memory failure prediction engine to
correlate a hardware configuration of a memory device with correctable errors (CEs) detected by an on-die error checking and correction (ECC) circuit of the memory device and provided to the controller by the memory device, and
predict an uncorrectable error (UE) based on correlation of the hardware configuration with the detected CEs.
29. The apparatus of claim 28, wherein the memory device comprises a dual inline memory module (DIMM).
5. The apparatus of claim 1,
wherein the memory device comprises a dual inline memory module (DIMM), and wherein the controller comprises a controller of the DIMM.
34. The apparatus of claim 28, wherein the circuitry to predicting the UE comprises the circuitry to identify a failure threshold based on a failure prediction model built for the memory device.
11. The apparatus of claim 1, wherein the memory failure prediction engine is to identify a failure threshold based on a memory failure prediction model built for the memory device.
35. A host hardware platform comprising:
a dual inline memory module (DIMM) that includes multiple memory devices; and
circuitry coupled to the multiple memory devices,
the circuitry to:
receive an indication of correctable errors (CEs) detected by an on-die error checking and correction (ECC) circuit of a memory device from among the multiple memory devices, wherein the indication of CEs detected by the on-die ECC circuit of the memory device were provided to a memory controller by the memory device;
correlate a hardware configuration of the memory device with the detected CEs; and
predict an uncorrectable error (UE) based on correlation of the hardware configuration with the detected CEs.
22. A system comprising: a host hardware platform including a central processing unit (CPU) and
a dual inline memory module (DIMM) having multiple memory devices; and a controller coupled to the memory devices of the DIMM,
the controller to
execute a memory failure prediction engine, the memory failure prediction engine to
correlate a hardware configuration of the host hardware platform with correctable errors (CEs) detected by an on-die error checking and correction (ECC) circuit of the memory devices and provided to the controller by the memory devices, and
predict an uncorrectable error (UE) based on correlation of the hardware configuration with the detected CEs.
40. (New) The host hardware platform of claim 35, wherein the circuitry to predicting the UE comprises the circuitry
to identify a failure threshold based on a failure prediction model built for the memory device.
24. The system of claim 22, wherein the memory failure prediction engine is
to identify a failure threshold based on a failure prediction model built for the memory devices.
Allowable Subject Matter
Claims 30-33 and 36-39 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2023/0161655 to Schlichting et al. teach a computerized method for training and using an uncorrectable error (UE) state prediction model based on telemetry error data is described. Sets of UE state labels and non-UE state labels are generated from a first set of collected telemetry data. Statistical features are extracted from telemetry data of the sets of UE state labels and non-UE state labels.
US 2021/0064462 to Eun et al. teach a memory device with an on-die ECC to help indicate/detect uncorrectable errors. The failure of the semiconductor memory device indicates that an uncorrectable error by the ECC function has occurred in the volatile memory device. The runtime repair operation indicates an operation to replace addresses in which the errors have occurred with repair addresses for preventing correctable errors from being changed to uncorrectable errors while a device or a system including the semiconductor memory device (volatile memory device) is operating.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CYNTHIA H BRITT whose telephone number is (571)272-3815. The examiner can normally be reached Monday - Thursday 8-5.
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CYNTHIA H. BRITT
Primary Examiner
Art Unit 2111
/CYNTHIA BRITT/Primary Examiner, Art Unit 2111
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