DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-8, 10-12 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Fujioka et al. (US 2013/0286302 A1) in view of Chaki et al. (USPN 5,646,966 A).
As to claim 1, Fujioka teaches a driving circuit comprising:
a display driver configured to generate a vertical synchronization signal according to a first clock signal of a first oscillator (see at least figs. 1-2, 9: timing generator 5, oscillation circuit 7a; and [0040] “The liquid crystal driving controller (timing generator) 5 generates, in accordance with a reference clock signal CLK from the oscillation circuit 7a (internal oscillation circuit), … a vertical synchronization signal Vsync”);
a sensor driver configured to generate a touch signal according to a second clock signal of a second oscillator (see at least figs. 1-2, 9: touch panel controller 4, oscillation circuit 7b and [0042] “While the above operation is being carried out, the touch panel controller 4 carries out sensing of the touch panel 2 at a timing based on a signal generated in accordance with a reference clock signal CLK supplied from the oscillation circuit 7b (generating circuit).”); and
a determination circuit configured to:
store threshold values of a range (see at least figs. 1-2: correcting circuit 10 and frequency counter 11; and [0063] “(i) a frequency reference value .., and (ii) an amount of correction … are stored in advance in the correcting circuit 10.”; [0070] “(i) a frequency reference value .., and (ii) an amount of correction .. are stored in advance in the correcting circuit 10”; [0082] “since a variation caused in a general oscillation circuit due to a temperature difference or an individual difference is .+-.8 to 10%, it is sufficient to set the amount of change so that the frequency of the reference clock signal CLK can be changed at a rate of 1% and up to .+-.16%.” – note Fujioka stores reference frequency values, acceptable deviations (±%)).
Fujioka does not expressly teach a determination circuit configured to: store threshold values of a third range or threshold values of a fourth range; detect a single cycle of the vertical synchronization signal according to a third count value of the second clock signal included in a high level section of the vertical synchronization signal, or a fourth count value of the second clock signal included in a low level section of the vertical synchronization signal; and output a detection signal based on the single cycle of the vertical synchronization signal when the third count value is out of the third range or the fourth count value is out of the fourth range.
Chaki teaches
a determination circuit configured to:
store threshold values of a third range or threshold values of a fourth range (see at least Fig. 1: N-number of latch circuits 51 to 5N for holding the count values of clocks between the edge portions; Col. 6 lines 38-48 “an (N+1) number of inequality coincidence circuits 10.sub.0 to 10.sub.N as comparator means, for comparing the numbers of clocks generated between transitions of the synchronization pattern and the clock count values held by the latch circuits 5.sub.1 to 5.sub.N and the counter 6, and for outputting a signal indicating the coincidence between the number of clocks between the edge portions and the clock count values of the distances between transitions of the synchronization pattern in case the difference between the two numbers of clocks is within a certain range” – therefore Chaki teaches comparison of measured clock counts against stored clock count values and determining whether the difference is within a predetermined allowable range);
detect a single cycle of the vertical synchronization signal according to a third count value of the second clock signal included in a high level section of the vertical synchronization signal, or a fourth count value of the second clock signal included in a low level section of the vertical synchronization signal (see at least fig. 1: counter 6 for counting the clocks generated between the extracted edge portions and col. 5 lines 1-3 “The number of clocks counted is therefore the distance between transitions produced in the synchronization signal.”; col. 5 lines 7-9 “the latch circuits 5.sub.1 to 5.sub.N hold the hysteresis of the clock count values between transitions” – note each interval measured by Chaki represents an individual synchronization interval bounded by successive transitions and is independently represented by a corresponding clock count value. Evaluation of an individual measured interval against a stored acceptable range constitutes evaluation of a single synchronization cycle or cycle portion. Also note the intervals measured by Chaki include intervals extending from a rising edge to a subsequent falling edge and intervals extending from a falling edge to a subsequent rising edge. Such intervals inherently correspond respectively to high-level portions and low-level portions of the synchronization signal.);
output a detection signal based on the single cycle of the vertical synchronization signal when the third count value is out of the third range or the fourth count value is out of the fourth range (see at least col. 4 lines 13-17 “AND gate 8 as decision means .. to give a decision as to whether or not the signal transition patterns are coincident”, and col. 6, lines 38-48 “an (N+1) number of inequality coincidence circuits 10.sub.0 to 10.sub.N as comparator means, for comparing the numbers of clocks generated between transitions of the synchronization pattern and the clock count values held by the latch circuits 5.sub.1 to 5.sub.N and the counter 6, and for outputting a signal indicating the coincidence between the number of clocks between the edge portions and the clock count values of the distances between transitions of the synchronization pattern in case the difference between the two numbers of clocks is within a certain range”- note each interval measured by Chaki represents an individual synchronization interval bounded by successive transitions and is independently represented by a corresponding clock count value. Evaluation of an individual measured interval against a stored acceptable range constitutes evaluation of a single synchronization cycle or cycle portion. Further, because Chaki already measures synchronization intervals bounded by successive transitions and compares the measured intervals against stored acceptable values, it would have been an obvious design choice to classify the measured intervals according to edge polarity and separately evaluate intervals corresponding to high-level sections and intervals corresponding to low-level sections of the synchronization signal. One of ordinary skill in the art would have recognized that intervals bounded by opposite edge polarities may have different expected durations and therefore may appropriately be evaluated against different acceptable ranges. Accordingly, it would have been obvious to maintain a first acceptable range for intervals corresponding to high-level sections of the synchronization signal and a second acceptable range for intervals corresponding to low-level sections of the synchronization signal. Such modification merely applies known interval-counting and threshold-comparison techniques to known categories of synchronization intervals and would have yielded predictable results.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Fujioka to employ Chaki’s synchronization interval counting and threshold comparison techniques for monitoring the vertical synchronization signal using the clock signal generated by Fujioka’s touch-controller oscillator (7b) and generating a detection signal when measured synchronization intervals fall outside predetermined acceptable ranges. Because a periodic synchronization signal inherently includes alternating high-level and low-level sections bounded by successive signal transitions, and because Chaki already measures clock counts between such transitions and compares the measured counts against stored reference values, it would have been obvious to separately evaluate clock counts corresponding to the high-level and low-level portions of the synchronization signal using respective threshold ranges. Such modification would have predictably improved detection of timing deviations, pulse-width variations, duty-cycle distortion, jitter, and other synchronization abnormalities between the display and touch subsystems while applying known interval-counting and threshold-comparison techniques to known portions of a synchronization signal.
As to claim 15, Fujioka teaches a display device comprising:
a display component comprising pixels connected to scan lines and data lines (see at least fig. 2: liquid crystal panel 3, scan line G, data lines S, note pixels are inherent in liquid crystal panel 3);
a sensor component comprising first sensors and second sensors configured to sense an external input (see at least figs. 4, 6-7);
a display driver configured to divide a first clock signal of a first oscillator, generate a vertical synchronization signal, and supply a data signal to the data lines (see at least figs. 1-2, 9: timing generator 5, oscillation circuit 7a, source driver 51, data lines S; and [0040] “The liquid crystal driving controller (timing generator) 5 generates, in accordance with a reference clock signal CLK from the oscillation circuit 7a (internal oscillation circuit), … a vertical synchronization signal Vsync”);
a sensor driver configured to divide a second clock signal of a second oscillator, and generate a touch signal to be supplied to the first sensors and/or the second sensors (see at least figs. 1-2, 9: touch panel controller 4, oscillation circuit 7b and [0042] “While the above operation is being carried out, the touch panel controller 4 carries out sensing of the touch panel 2 at a timing based on a signal generated in accordance with a reference clock signal CLK supplied from the oscillation circuit 7b (generating circuit).”); and
a determination circuit configured to:
store threshold values of a range (see at least figs. 1-2: correcting circuit 10 and frequency counter 11; and [0063] “(i) a frequency reference value .., and (ii) an amount of correction … are stored in advance in the correcting circuit 10.”; [0070] “(i) a frequency reference value .., and (ii) an amount of correction .. are stored in advance in the correcting circuit 10”; [0082] “since a variation caused in a general oscillation circuit due to a temperature difference or an individual difference is .+-.8 to 10%, it is sufficient to set the amount of change so that the frequency of the reference clock signal CLK can be changed at a rate of 1% and up to .+-.16%.” – note Fujioka stores reference frequency values, acceptable deviations (±%)).
Fujioka does not directly teach a determination circuit configured to: store threshold values of a third range or threshold values of a fourth range; detect a single cycle of the vertical synchronization signal according to a third count value of the second clock signal included in a high level section of the vertical synchronization signal, or a fourth count value of the second clock signal included in a low level section of the vertical synchronization signal; and output a detection signal based on the single cycle of the vertical synchronization signal when the third count value is out of the third range or the fourth count value is out of the fourth range.
Chaki teaches
a determination circuit configured to:
store threshold values of a third range or threshold values of a fourth range (see at least Fig. 1: N-number of latch circuits 51 to 5N for holding the count values of clocks between the edge portions; Col. 6 lines 38-48 “an (N+1) number of inequality coincidence circuits 10.sub.0 to 10.sub.N as comparator means, for comparing the numbers of clocks generated between transitions of the synchronization pattern and the clock count values held by the latch circuits 5.sub.1 to 5.sub.N and the counter 6, and for outputting a signal indicating the coincidence between the number of clocks between the edge portions and the clock count values of the distances between transitions of the synchronization pattern in case the difference between the two numbers of clocks is within a certain range” – therefore Chaki teaches comparison of measured clock counts against stored clock count values and determining whether the difference is within a predetermined allowable range);
detect a single cycle of the vertical synchronization signal according to a third count value of the second clock signal included in a high level section of the vertical synchronization signal, or a fourth count value of the second clock signal included in a low level section of the vertical synchronization signal (see at least fig. 1: counter 6 for counting the clocks generated between the extracted edge portions and col. 5 lines 1-3 “The number of clocks counted is therefore the distance between transitions produced in the synchronization signal.”; col. 5 lines 7-9 “the latch circuits 5.sub.1 to 5.sub.N hold the hysteresis of the clock count values between transitions” – note each interval measured by Chaki represents an individual synchronization interval bounded by successive transitions and is independently represented by a corresponding clock count value. Evaluation of an individual measured interval against a stored acceptable range constitutes evaluation of a single synchronization cycle or cycle portion. Also note the intervals measured by Chaki include intervals extending from a rising edge to a subsequent falling edge and intervals extending from a falling edge to a subsequent rising edge. Such intervals inherently correspond respectively to high-level portions and low-level portions of the synchronization signal.);
output a detection signal based on the single cycle of the vertical synchronization signal when the third count value is out of the third range or the fourth count value is out of the fourth range (see at least col. 4 lines 13-17 “AND gate 8 as decision means .. to give a decision as to whether or not the signal transition patterns are coincident”, and col. 6, lines 38-48 “an (N+1) number of inequality coincidence circuits 10.sub.0 to 10.sub.N as comparator means, for comparing the numbers of clocks generated between transitions of the synchronization pattern and the clock count values held by the latch circuits 5.sub.1 to 5.sub.N and the counter 6, and for outputting a signal indicating the coincidence between the number of clocks between the edge portions and the clock count values of the distances between transitions of the synchronization pattern in case the difference between the two numbers of clocks is within a certain range”- note each interval measured by Chaki represents an individual synchronization interval bounded by successive transitions and is independently represented by a corresponding clock count value. Evaluation of an individual measured interval against a stored acceptable range constitutes evaluation of a single synchronization cycle or cycle portion. Further, because Chaki already measures synchronization intervals bounded by successive transitions and compares the measured intervals against stored acceptable values, it would have been an obvious design choice to classify the measured intervals according to edge polarity and separately evaluate intervals corresponding to high-level sections and intervals corresponding to low-level sections of the synchronization signal. One of ordinary skill in the art would have recognized that intervals bounded by opposite edge polarities may have different expected durations and therefore may appropriately be evaluated against different acceptable ranges. Accordingly, it would have been obvious to maintain a first acceptable range for intervals corresponding to high-level sections of the synchronization signal and a second acceptable range for intervals corresponding to low-level sections of the synchronization signal. Such modification merely applies known interval-counting and threshold-comparison techniques to known categories of synchronization intervals and would have yielded predictable results.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Fujioka to employ Chaki’s synchronization interval counting and threshold comparison techniques for monitoring the vertical synchronization signal using the clock signal generated by Fujioka’s touch-controller oscillator (7b) and generating a detection signal when measured synchronization intervals fall outside predetermined acceptable ranges. Because a periodic synchronization signal inherently includes alternating high-level and low-level sections bounded by successive signal transitions, and because Chaki already measures clock counts between such transitions and compares the measured counts against stored reference values, it would have been obvious to separately evaluate clock counts corresponding to the high-level and low-level portions of the synchronization signal using respective threshold ranges. Such modification would have predictably improved detection of timing deviations, pulse-width variations, duty-cycle distortion, jitter, and other synchronization abnormalities between the display and touch subsystems while applying known interval-counting and threshold-comparison techniques to known portions of a synchronization signal.
As to claim 2, the combination of Fujioka and Chaki teach the driving circuit according to claim 1 (see above rejection), wherein to detect the cycle of the vertical synchronization signal according to the second clock signal, the determination circuit is configured to count a number of times that the second clock signal overlaps with at least one of the high level section or the low level section of the vertical synchronization signal (see Chaki at least fig. 1: counter 6 for counting the clocks generated between the extracted edge portions and col. 5 lines 1-3 “The number of clocks counted is therefore the distance between transitions produced in the synchronization signal.”; col. 5 lines 7-9 “the latch circuits 5.sub.1 to 5.sub.N hold the hysteresis of the clock count values between transitions” – note Chaki measures intervals bounded by successive transitions. Intervals bounded by a rising edge and a subsequent falling edge inherently correspond to high-level portions of the synchronization signal, while intervals bounded by a falling edge and a subsequent rising edge inherently correspond to low-level portions of the synchronization signal.).
As to claim 3, the combination of Fujioka and Chaki teach the driving circuit according to claim 1 (see above rejection), wherein the determination circuit comprises:
a counter configured to: count, according to the second clock signal (see Fujioka at least fig. 1(a) frequency counter 11, oscillation circuit 7b),
at least one section from the high level section of the vertical synchronization signal; and generate the third count value according to the count (see Chaki at least fig. 1: counter 6 for counting the clocks generated between the extracted edge portions and col. 5 lines 1-3 “The number of clocks counted is therefore the distance between transitions produced in the synchronization signal.”; col. 5 lines 7-9 “the latch circuits 5.sub.1 to 5.sub.N hold the hysteresis of the clock count values between transitions” – note Chaki measures intervals bounded by successive transitions. Intervals bounded by a rising edge and a subsequent falling edge inherently correspond to high-level portions of the synchronization signal, while intervals bounded by a falling edge and a subsequent rising edge inherently correspond to low-level portions of the synchronization signal.);
storage configured to store the threshold values of the third range (see Chaki at least Fig. 1: N-number of latch circuits 51 to 5N for holding the count values of clocks between the edge portions; Col. 6 lines 38-48 “an (N+1) number of inequality coincidence circuits 10.sub.0 to 10.sub.N as comparator means, for comparing the numbers of clocks generated between transitions of the synchronization pattern and the clock count values held by the latch circuits 5.sub.1 to 5.sub.N and the counter 6, and for outputting a signal indicating the coincidence between the number of clocks between the edge portions and the clock count values of the distances between transitions of the synchronization pattern in case the difference between the two numbers of clocks is within a certain range” – therefore Chaki teaches storage of count values and range-based thresholds); and
a controller configured to receive the third count value and the threshold values of the third range, and output the detection signal when the third count value is out of the third range (see Chaki at least col. 4 lines 13-17 “AND gate 8 as decision means .. to give a decision as to whether or not the signal transition patterns are coincident” – note by logical inversion, a detection signal is produced when the measured values fall outside the acceptable range).
As to claim 4, the combination of Fujioka and Chaki teach the driving circuit according to claim 3 (see above rejection), further comprising a frequency controller connected to the second oscillator, and configured to change a frequency of the second clock signal in response to the detection signal (see Fujioka at least fig. 1 and [0057] “correction of one of the liquid crystal driving frequency and the scanning frequency makes it possible to prevent the touch panel-sensed noise frequency and the liquid crystal driving noise frequency from overlapping each other.”).
As to claim 6, the combination of Fujioka and Chaki teach the driving circuit according to claim 4 (see above rejection), wherein the sensor driver comprises a touch controller configured to supply the touch signal to sensors (see Fujioka at least figs. 1: touch panel controller 4).
As to claim 7, the combination of Fujioka and Chaki teach the driving circuit according to claim 6 (see above rejection), wherein the sensor driver comprises the determination circuit and the frequency controller (see Fujioka at least fig. 1: correcting circuit 10 and frequency counter 11).
As to claim 8, the combination of Fujioka and Chaki teach the driving circuit according to claim 3 (see above rejection), further comprising a first frequency controller connected to the first oscillator, and configured to change a frequency of the first clock signal in response to the detection signal (see Fujioka at least fig. 1(b): frequency controller 11 connected to oscillation circuit 7a).
As to claim 10, the combination of Fujioka and Chaki teach the driving circuit according to claim 8 (see above rejection), wherein the display driver comprises: a data driver configured to supply a data signal to data lines; and a timing controller configured to control the data driver (see Fujioka at least fig. 2: source driver 51, data lines S, timing generator 5).
As to claim 11, the combination of Fujioka and Chaki teach the driving circuit according to claim 10 (see above rejection), wherein the display driver comprises the determination circuit and the first frequency controller (see Fujioka at least fig. 1: correcting circuit 10 and frequency counter 11).
As to claim 12, the combination of Fujioka and Chaki teach the driving circuit according to claim 10 (see above rejection), wherein the first frequency controller is configured to supply a control signal to the timing controller in response to the detection signal, and wherein the timing controller is configured to supply an oscillation change signal to the sensor driver in response to the control signal (see Fujioka at least figs. 1-2 and [0057] “correction of one of the liquid crystal driving frequency and the scanning frequency makes it possible to prevent the touch panel-sensed noise frequency and the liquid crystal driving noise frequency from overlapping each other.”).
As to claim 14, the combination of Fujioka and Chaki teach the driving circuit according to claim 1 (see above rejection), wherein the determination circuit comprises:
a counter configured to: count, according to the second clock signal (see Fujioka at least fig. 1(a) frequency counter 11, oscillation circuit 7b),
at least one section from the low level section of the vertical synchronization signal; and generate the fourth count value according to the count (see Chaki at least fig. 1: counter 6 for counting the clocks generated between the extracted edge portions and col. 5 lines 1-3 “The number of clocks counted is therefore the distance between transitions produced in the synchronization signal.” – note a high-level section of a synchronization signal is bounded by edges; thus, counting clocks between those edges inherently measures the duration of the high-level section; col. 5 lines 7-9 “the latch circuits 5.sub.1 to 5.sub.N hold the hysteresis of the clock count values between transitions” – note Chaki measures intervals bounded by successive transitions. Intervals bounded by a rising edge and a subsequent falling edge inherently correspond to high-level portions of the synchronization signal, while intervals bounded by a falling edge and a subsequent rising edge inherently correspond to low-level portions of the synchronization signal);
storage configured to store the threshold values of the fourth range (see Chaki at least Fig. 1: N-number of latch circuits 51 to 5N for holding the count values of clocks between the edge portions; Col. 6 lines 38-48 “an (N+1) number of inequality coincidence circuits 10.sub.0 to 10.sub.N as comparator means, for comparing the numbers of clocks generated between transitions of the synchronization pattern and the clock count values held by the latch circuits 5.sub.1 to 5.sub.N and the counter 6, and for outputting a signal indicating the coincidence between the number of clocks between the edge portions and the clock count values of the distances between transitions of the synchronization pattern in case the difference between the two numbers of clocks is within a certain range” – therefore Chaki teaches storage of count values and range-based thresholds); and
a controller configured to receive the fourth count value and the threshold values of the fourth range, and output the detection signal when the fourth count value is out of the fourth range (see Chaki at least col. 4 lines 13-17 “AND gate 8 as decision means .. to give a decision as to whether or not the signal transition patterns are coincident” – note by logical inversion, a detection signal is produced when the measured values fall outside the acceptable range).
As to claim 16, the combination of Fujioka and Chaki teach the display device according to claim 15 (see above rejection),
wherein to detect the cycle of the vertical synchronization signal according to the second clock signal, the determination circuit is configured to count a number of times that the second clock signal overlaps with at least one of the high level section or the low level section of the vertical synchronization signal (see Chaki at least fig. 1: counter 6 for counting the clocks generated between the extracted edge portions and col. 5 lines 1-3 “The number of clocks counted is therefore the distance between transitions produced in the synchronization signal.”; col. 5 lines 7-9 “the latch circuits 5.sub.1 to 5.sub.N hold the hysteresis of the clock count values between transitions” – note Chaki measures intervals bounded by successive transitions. Intervals bounded by a rising edge and a subsequent falling edge inherently correspond to high-level portions of the synchronization signal, while intervals bounded by a falling edge and a subsequent rising edge inherently correspond to low-level portions of the synchronization signal),
wherein the determination circuit comprises:
a counter configured to count the cycle of the vertical synchronization signal according to the second clock signal, and generate the third count value or the fourth count value (see Fujioka at least fig. 1(a) frequency counter 11, oscillation circuit 7b; Chaki at least fig. 1: counter 6 for counting the clocks generated between the extracted edge portions);
storage configured to store the threshold values of the third range or the fourth range (see Chaki at least Fig. 1: N-number of latch circuits 51 to 5N for holding the count values of clocks between the edge portions; Col. 6 lines 38-48 “an (N+1) number of inequality coincidence circuits 10.sub.0 to 10.sub.N as comparator means, for comparing the numbers of clocks generated between transitions of the synchronization pattern and the clock count values held by the latch circuits 5.sub.1 to 5.sub.N and the counter 6, and for outputting a signal indicating the coincidence between the number of clocks between the edge portions and the clock count values of the distances between transitions of the synchronization pattern in case the difference between the two numbers of clocks is within a certain range” – therefore Chaki teaches storage of count values and range-based thresholds); and
a controller configured to receive the third count value or the fourth count value, and the threshold values of the third range or the fourth range, and output the detection signal when the third count value is out of the third range or the fourth count value is out of the fourth range (see Chaki at least col. 4 lines 13-17 “AND gate 8 as decision means .. to give a decision as to whether or not the signal transition patterns are coincident” – note by logical inversion, a detection signal is produced when the measured values fall outside the acceptable range).
Response to Arguments
Applicant's arguments filed 3/30/2026 have been fully considered but they are not persuasive.
Applicant argues that Chaki counts clocks between transitions of a synchronization signal for purposes of signal reproduction and therefore there would have been no reason for one of ordinary skill in the art to modify Chaki to detect a third count value in a high-level section of the synchronization signal or a fourth count value in a low-level section of the synchronization signal.
Examiner disagrees - The rejection does not rely on Chaki’s signal reproduction functionality. Rather, Chaki is relied upon for teaching measurement of synchronization timing intervals according to clock counts occurring between successive transitions of a synchronization signal and comparison of measured count values against stored acceptable values. The intended use of the measured intervals in Chaki does not negate or limit these teachings.
Applicant further argues that Chaki seeks to reduce circuit scale and that modifying Chaki to separately evaluate high-level and low-level portions of a synchronization signal would be contrary to the teachings of Chaki.
Examiner disagrees - The rejection does not require increasing the number of latch circuits in the manner alleged by Applicant. Rather, the rejection relies on classifying synchronization intervals that are already measured by Chaki according to edge polarity and evaluating those intervals against corresponding acceptable ranges. Applicant has not identified any disclosure in Chaki criticizing, discrediting, or otherwise discouraging classification of measured synchronization intervals according to edge polarity or use of separate acceptable ranges for different interval types. A preference for reduced circuit scale does not teach away from the modification proposed by the rejection.
Applicant additionally argues that the cited portions of Chaki do not describe different noise characteristics associated with different signal levels.
Examiner notes that Applicant is correct that Chaki does not expressly discuss different noise characteristics associated with different signal levels. However, the rejection is maintained because the rationale for the modification does not depend on any particular noise characteristic. Rather, once synchronization intervals are measured between successive transitions and compared against stored acceptable values, it would have been obvious to classify the measured intervals according to edge polarity and evaluate the resulting interval types against corresponding acceptable ranges. Such modification represents a predictable variation of Chaki’s disclosed synchronization interval monitoring technique.
Applicant further argues that detecting a third count value in a high-level section of the synchronization signal or a fourth count value in a low-level section of the synchronization signal would defeat the purpose of Chaki.
Examiner disagrees - The rejection does not alter Chaki’s disclosed interval-counting technique. Rather, the rejection relies upon the fact that Chaki already measures intervals bounded by successive transitions. Intervals bounded by a rising edge and a subsequent falling edge inherently correspond to high-level portions of the synchronization signal, while intervals bounded by a falling edge and a subsequent rising edge inherently correspond to low-level portions of the synchronization signal. Classifying already measured intervals according to edge polarity does not defeat the purpose of Chaki and instead represents a predictable refinement of the disclosed timing-monitoring technique.
Applicant additionally argues that Chaki requires a plurality of latch circuits for storing successive clock count values and that detecting a single cycle of the vertical synchronization signal and outputting a detection signal based on the single cycle would not enable the signal reproduction functionality of Chaki.
Examiner disagrees - Claim 1/15 does not exclude storage of multiple count values, use of multiple latch circuits, maintenance of historical synchronization information, or additional processing based on multiple synchronization intervals. The claim merely requires detecting a single cycle of the vertical synchronization signal according to the recited count values and outputting a detection signal based on the single cycle. Chaki measures synchronization timing on an interval-by-interval basis, wherein each measured interval between successive transitions corresponds to an individual synchronization interval represented by a clock count value. Evaluation of an individual measured interval against a stored acceptable range constitutes evaluation of a single synchronization interval. The fact that Chaki additionally stores multiple interval measurements for subsequent synchronization processing does not preclude generation of a determination result based on an individual measured interval.
Examiner notes that Applicant’s arguments attack Chaki individually rather than the teachings and suggestions of the combined references.
Allowable Subject Matter
Claims 5, 9, 13 and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
None of the prior art of record teach:
“A driving circuit comprising: a display driver configured to generate a vertical synchronization signal according to a first clock signal of a first oscillator; a sensor driver configured to generate a touch signal according to a second clock signal of a second oscillator; and a determination circuit configured to: store threshold values of a third range or threshold values of a fourth range; detect a single cycle of the vertical synchronization signal according to a third count value of the second clock signal included in a high level section of the vertical synchronization signal, or a fourth count value of the second clock signal included in a low level section of the vertical synchronization signal; and output a detection signal based on the single cycle of the vertical synchronization signal when the third count value is out of the third range or the fourth count value is out of the fourth range;
wherein the determination circuit comprises: a counter configured to: count, according to the second clock signal, at least one section from the high level section of the vertical synchronization signal; and generate the third count value according to the count; storage configured to store the threshold values of the third range; and a controller configured to receive the third count value and the threshold values of the third range, and output the detection signal when the third count value is out of the third range;
further comprising a frequency controller connected to the second oscillator, and configured to change a frequency of the second clock signal in response to the detection signal;
wherein, when the frequency of the second clock signal is changed by the frequency controller, the count value is changed to be included in the range.”;
“A driving circuit comprising: a display driver configured to generate a vertical synchronization signal according to a first clock signal of a first oscillator; a sensor driver configured to generate a touch signal according to a second clock signal of a second oscillator; and a determination circuit configured to: store threshold values of a third range or threshold values of a fourth range; detect a single cycle of the vertical synchronization signal according to a third count value of the second clock signal included in a high level section of the vertical synchronization signal, or a fourth count value of the second clock signal included in a low level section of the vertical synchronization signal; and output a detection signal based on the single cycle of the vertical synchronization signal when the third count value is out of the third range or the fourth count value is out of the fourth range;
wherein the determination circuit comprises: a counter configured to: count, according to the second clock signal, at least one section from the high level section of the vertical synchronization signal; and generate the third count value according to the count; storage configured to store the threshold values of the third range; and a controller configured to receive the third count value and the threshold values of the third range, and output the detection signal when the third count value is out of the third range;
further comprising a first frequency controller connected to the first oscillator, and configured to change a frequency of the first clock signal in response to the detection signal;
wherein, when the frequency of the first clock signal is changed by the first frequency controller, the count value is changed to be included in the range.”;
“A driving circuit comprising: a display driver configured to generate a vertical synchronization signal according to a first clock signal of a first oscillator; a sensor driver configured to generate a touch signal according to a second clock signal of a second oscillator; and a determination circuit configured to: store threshold values of a third range or threshold values of a fourth range; detect a single cycle of the vertical synchronization signal according to a third count value of the second clock signal included in a high level section of the vertical synchronization signal, or a fourth count value of the second clock signal included in a low level section of the vertical synchronization signal; and output a detection signal based on the single cycle of the vertical synchronization signal when the third count value is out of the third range or the fourth count value is out of the fourth range;
wherein the determination circuit comprises: a counter configured to: count, according to the second clock signal, at least one section from the high level section of the vertical synchronization signal; and generate the third count value according to the count; storage configured to store the threshold values of the third range; and a controller configured to receive the third count value and the threshold values of the third range, and output the detection signal when the third count value is out of the third range;
further comprising a first frequency controller connected to the first oscillator, and configured to change a frequency of the first clock signal in response to the detection signal;
wherein the display driver comprises: a data driver configured to supply a data signal to data lines; and a timing controller configured to control the data driver;
wherein the first frequency controller is configured to supply a control signal to the timing controller in response to the detection signal, and wherein the timing controller is configured to supply an oscillation change signal to the sensor driver in response to the control signal;
wherein the sensor driver comprises a second frequency controller connected to the second oscillator, and configured to change a frequency of the second clock signal in response to the oscillation change signal, and wherein, when the frequency of the second clock signal is changed by the second frequency controller, the third count value is changed to be included in the third range.”;
“A display device comprising: a display component comprising pixels connected to scan lines and data lines; a sensor component comprising first sensors and second sensors configured to sense an external input; a display driver configured to divide a first clock signal of a first oscillator, generate a vertical synchronization signal, and supply a data signal to the data lines; a sensor driver configured to divide a second clock signal of a second oscillator, and generate a touch signal to be supplied to the first sensors and/or the second sensors; and a determination circuit configured to: store threshold values of a third range or threshold values of a fourth range; detect a single cycle of the vertical synchronization signal according to a third count value of the second clock signal included in a high level section of the vertical synchronization signal, or a fourth count value of the second clock signal included in a low level section of the vertical synchronization signal; and output a detection signal based on the single cycle of the vertical synchronization signal when the third count value is out of the third range or the fourth count value is out of the fourth range;
wherein to detect the cycle of the vertical synchronization signal according to the second clock signal, the determination circuit is configured to count a number of times that the second clock signal overlaps with at least one of the high level section or the low level section of the vertical synchronization signal, wherein the determination circuit comprises: a counter configured to count the cycle of the vertical synchronization signal according to the second clock signal, and generate the third count value or the fourth count value; storage configured to store the threshold values of the third range or the fourth range; and a controller configured to receive the third count value or the fourth count value, and the threshold values of the third range or the fourth range, and output the detection signal when the third count value is out of the third range or the fourth count value is out of the fourth range;
further comprising a frequency controller connected to the second oscillator, and configured to change a frequency of the second clock signal in response to the detection signal, wherein, when the frequency of the second clock signal is changed by the frequency controller, the third count value or the fourth count value is changed to be included in the range.”; and
“A display device comprising: a display component comprising pixels connected to scan lines and data lines; a sensor component comprising first sensors and second sensors configured to sense an external input; a display driver configured to divide a first clock signal of a first oscillator, generate a vertical synchronization signal, and supply a data signal to the data lines; a sensor driver configured to divide a second clock signal of a second oscillator, and generate a touch signal to be supplied to the first sensors and/or the second sensors; and a determination circuit configured to: store threshold values of a third range or threshold values of a fourth range; detect a single cycle of the vertical synchronization signal according to a third count value of the second clock signal included in a high level section of the vertical synchronization signal, or a fourth count value of the second clock signal included in a low level section of the vertical synchronization signal; and output a detection signal based on the single cycle of the vertical synchronization signal when the third count value is out of the third range or the fourth count value is out of the fourth range;
wherein to detect the cycle of the vertical synchronization signal according to the second clock signal, the determination circuit is configured to count a number of times that the second clock signal overlaps with at least one of the high level section or the low level section of the vertical synchronization signal, wherein the determination circuit comprises: a counter configured to count the cycle of the vertical synchronization signal according to the second clock signal, and generate the third count value or the fourth count value; storage configured to store the threshold values of the third range or the fourth range; and a controller configured to receive the third count value or the fourth count value, and the threshold values of the third range or the fourth range, and output the detection signal when the third count value is out of the third range or the fourth count value is out of the fourth range;
further comprising a frequency controller connected to the first oscillator, and configured to change a frequency of the first clock signal in response to the detection signal, wherein, when the frequency of the first clock signal is changed by the frequency controller, the third count value or the fourth count value is changed to be included in the range.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JENNIFER L ZUBAJLO/Examiner, Art Unit 2627 6/7/2026
/KE XIAO/Supervisory Patent Examiner, Art Unit 2627
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