DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-23 of U.S. Patent No. 12,260,046 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the differences between the instant claim and the patent claim represent obvious variations, such as limiting detection to vertical synchronization and specifying threshold ranges, which would have been obvious to one of ordinary skill in the art.
USPN 12,260,046 B2
Instant Application 19/088935
1. A driving circuit comprising:
a display driver configured to generate a horizontal synchronization signal and a vertical synchronization signal according to a first clock signal of a first oscillator;
a sensor driver configured to generate a touch signal according to a second clock signal of a second oscillator; and
a determination circuit configured to
detect a cycle of at least one of the horizontal synchronization signal or the vertical synchronization signal according to the second clock signal, and output a detection signal when the cycle is out of a range, wherein the determination circuit is a part of the display driver or the sensor driver, and wherein to detect the cycle of the at least one of the horizontal synchronization signal or the vertical synchronization signal according to the second clock signal, the determination circuit is configured to count a number of times that the second clock signal overlaps with at least one of a high level section or a low level section of the horizontal synchronization signal or the vertical synchronization signal, wherein the determination circuit is configured to detect the cycle of the horizontal synchronization signal according to a first count value of the second clock signal included in the high level section of the horizontal synchronization signal, and a second count value of the second clock signal included in the low level section of the horizontal synchronization signal, wherein the determination circuit is configured to output the detection signal when the first count value or the second count value is out of the range.
1. A driving circuit comprising:
a display driver configured to generate a vertical synchronization signal according to a first clock signal of a first oscillator;
a sensor driver configured to generate a touch signal according to a second clock signal of a second oscillator; and
a determination circuit configured to:
store threshold values of a third range or threshold values of a fourth range;
detect a cycle of the vertical synchronization signal according to a third count value of the second clock signal included in a high level section of the vertical synchronization signal, or a fourth count value of the second clock signal included in a low level section of the vertical synchronization signal; and
output a detection signal when the third count value is out of the third range or the fourth count value is out of the fourth range.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-8, 10-12 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Fujioka et al. (US 2013/0286302 A1) in view of Chaki et al. (USPN 5,646,966 A).
As to claim 1, Fujioka teaches a driving circuit comprising:
a display driver configured to generate a vertical synchronization signal according to a first clock signal of a first oscillator (see at least figs. 1-2, 9: timing generator 5, oscillation circuit 7a; and [0040] “The liquid crystal driving controller (timing generator) 5 generates, in accordance with a reference clock signal CLK from the oscillation circuit 7a (internal oscillation circuit), … a vertical synchronization signal Vsync”);
a sensor driver configured to generate a touch signal according to a second clock signal of a second oscillator (see at least figs. 1-2, 9: touch panel controller 4, oscillation circuit 7b and [0042] “While the above operation is being carried out, the touch panel controller 4 carries out sensing of the touch panel 2 at a timing based on a signal generated in accordance with a reference clock signal CLK supplied from the oscillation circuit 7b (generating circuit).”); and
a determination circuit configured to:
store threshold values of a range (see at least figs. 1-2: correcting circuit 10 and frequency counter 11; and [0063] “(i) a frequency reference value .., and (ii) an amount of correction … are stored in advance in the correcting circuit 10.”; [0070] “(i) a frequency reference value .., and (ii) an amount of correction .. are stored in advance in the correcting circuit 10”; [0082] “since a variation caused in a general oscillation circuit due to a temperature difference or an individual difference is .+-.8 to 10%, it is sufficient to set the amount of change so that the frequency of the reference clock signal CLK can be changed at a rate of 1% and up to .+-.16%.” – note Fujioka stores reference frequency values, acceptable deviations (±%)).
Fujioka does not directly teach a determination circuit configured to: store threshold values of a third range or threshold values of a fourth range; detect a cycle of the vertical synchronization signal according to a third count value of the second clock signal included in a high level section of the vertical synchronization signal, or a fourth count value of the second clock signal included in a low level section of the vertical synchronization signal; and output a detection signal when the third count value is out of the third range or the fourth count value is out of the fourth range.
Chaki teaches
a determination circuit configured to:
store threshold values of a third range or threshold values of a fourth range (see at least Fig. 1: N-number of latch circuits 51 to 5N for holding the count values of clocks between the edge portions; Col. 6 lines 38-48 “an (N+1) number of inequality coincidence circuits 10.sub.0 to 10.sub.N as comparator means, for comparing the numbers of clocks generated between transitions of the synchronization pattern and the clock count values held by the latch circuits 5.sub.1 to 5.sub.N and the counter 6, and for outputting a signal indicating the coincidence between the number of clocks between the edge portions and the clock count values of the distances between transitions of the synchronization pattern in case the difference between the two numbers of clocks is within a certain range” – therefore Chaki teaches storage of count values and range-based thresholds);
detect a cycle of the vertical synchronization signal according to a third count value of the second clock signal included in a high level section of the vertical synchronization signal, or a fourth count value of the second clock signal included in a low level section of the vertical synchronization signal (see at least fig. 1: counter 6 for counting the clocks generated between the extracted edge portions and col. 5 lines 1-3 “The number of clocks counted is therefore the distance between transitions produced in the synchronization signal.” – note a high-level section of a synchronization signal is bounded by edges; thus, counting clocks between those edges inherently measures the duration of the high-level section; col. 5 lines 7-9 “the latch circuits 5.sub.1 to 5.sub.N hold the hysteresis of the clock count values between transitions” – note successive measurements of clock counts between transitions necessarily include both high-level and low-level durations of the synchronization signal. Separating these measurements into distinct high-level and low-level sections would have been an obvious design variation to improve timing resolution, especially where different noise characteristics may occur during different signal levels. This is an obvious extension of disclosed timing measurement); and
output a detection signal when the third count value is out of the third range or the fourth count value is out of the fourth range (see at least col. 4 lines 13-17 “AND gate 8 as decision means .. to give a decision as to whether or not the signal transition patterns are coincident” – note by logical inversion, a detection signal is produced when the measured values fall outside the acceptable range).
Fujioka and Chaki both relate to synchronization timing detection. Fujioka teaches a display system with a first oscillator for display timing and a second oscillator for touch sensing, including counters and stored reference values for monitoring timing deviations. Chaki teaches counting clock pulses during synchronization signal intervals and comparing the counts to stored threshold values to detect abnormal timing. Applying Chaki’s technique to Fujioka’s system would improve reliability in detecting timing abnormalities between display and touch domains. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Fujioka to count pulses of the second oscillator during high and low portions of the vertical synchronization signal and output a detection signal when the counts deviate from expected ranges, as a predictable use of known timing monitoring techniques. The claimed invention represents an obvious application of known synchronization-timing measurement techniques to a known dual-oscillator display/touch system. The rationale to support a conclusion that the claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods and the combination yields nothing more than predictable results to one of ordinary skill in the art.
As to claim 15, Fujioka teaches a display device comprising:
a display component comprising pixels connected to scan lines and data lines (see at least fig. 2: liquid crystal panel 3, scan line G, data lines S, note pixels are inherent in liquid crystal panel 3);
a sensor component comprising first sensors and second sensors configured to sense an external input (see at least figs. 4, 6-7);
a display driver configured to divide a first clock signal of a first oscillator, generate a vertical synchronization signal, and supply a data signal to the data lines (see at least figs. 1-2, 9: timing generator 5, oscillation circuit 7a, source driver 51, data lines S; and [0040] “The liquid crystal driving controller (timing generator) 5 generates, in accordance with a reference clock signal CLK from the oscillation circuit 7a (internal oscillation circuit), … a vertical synchronization signal Vsync”);
a sensor driver configured to divide a second clock signal of a second oscillator, and generate a touch signal to be supplied to the first sensors and/or the second sensors (see at least figs. 1-2, 9: touch panel controller 4, oscillation circuit 7b and [0042] “While the above operation is being carried out, the touch panel controller 4 carries out sensing of the touch panel 2 at a timing based on a signal generated in accordance with a reference clock signal CLK supplied from the oscillation circuit 7b (generating circuit).”); and
a determination circuit configured to:
store threshold values of a range (see at least figs. 1-2: correcting circuit 10 and frequency counter 11; and [0063] “(i) a frequency reference value .., and (ii) an amount of correction … are stored in advance in the correcting circuit 10.”; [0070] “(i) a frequency reference value .., and (ii) an amount of correction .. are stored in advance in the correcting circuit 10”; [0082] “since a variation caused in a general oscillation circuit due to a temperature difference or an individual difference is .+-.8 to 10%, it is sufficient to set the amount of change so that the frequency of the reference clock signal CLK can be changed at a rate of 1% and up to .+-.16%.” – note Fujioka stores reference frequency values, acceptable deviations (±%)).
Fujioka does not directly teach store threshold values of a third range or threshold values of a fourth range; detect a cycle of the vertical synchronization signal according to a third count value of the second clock signal included in a high level section of the vertical synchronization signal, or a fourth count value of the second clock signal included in a low level section of the vertical synchronization signal; and output a detection signal when the third count value is out of the third range or the fourth count value is out of the fourth range.
Chaki teaches a determination circuit configured to:
store threshold values of a third range or threshold values of a fourth range (see at least Fig. 1: N-number of latch circuits 51 to 5N for holding the count values of clocks between the edge portions; Col. 6 lines 38-48 “an (N+1) number of inequality coincidence circuits 10.sub.0 to 10.sub.N as comparator means, for comparing the numbers of clocks generated between transitions of the synchronization pattern and the clock count values held by the latch circuits 5.sub.1 to 5.sub.N and the counter 6, and for outputting a signal indicating the coincidence between the number of clocks between the edge portions and the clock count values of the distances between transitions of the synchronization pattern in case the difference between the two numbers of clocks is within a certain range” – therefore Chaki teaches storage of count values and range-based thresholds);
detect a cycle of the vertical synchronization signal according to a third count value of the second clock signal included in a high level section of the vertical synchronization signal, or a fourth count value of the second clock signal included in a low level section of the vertical synchronization signal (see at least fig. 1: counter 6 for counting the clocks generated between the extracted edge portions and col. 5 lines 1-3 “The number of clocks counted is therefore the distance between transitions produced in the synchronization signal.” – note a high-level section of a synchronization signal is bounded by edges; thus, counting clocks between those edges inherently measures the duration of the high-level section; col. 5 lines 7-9 “the latch circuits 5.sub.1 to 5.sub.N hold the hysteresis of the clock count values between transitions” – note successive measurements of clock counts between transitions necessarily include both high-level and low-level durations of the synchronization signal. Separating these measurements into distinct high-level and low-level sections would have been an obvious design variation to improve timing resolution, especially where different noise characteristics may occur during different signal levels. This is an obvious extension of disclosed timing measurement); and
output a detection signal when the third count value is out of the third range or the fourth count value is out of the fourth range (see at least col. 4 lines 13-17 “AND gate 8 as decision means .. to give a decision as to whether or not the signal transition patterns are coincident” – note by logical inversion, a detection signal is produced when the measured values fall outside the acceptable range).
Fujioka and Chaki both relate to synchronization timing detection. Fujioka teaches a display system with a first oscillator for display timing and a second oscillator for touch sensing, including counters and stored reference values for monitoring timing deviations. Chaki teaches counting clock pulses during synchronization signal intervals and comparing the counts to stored threshold values to detect abnormal timing. Applying Chaki’s technique to Fujioka’s system would improve reliability in detecting timing abnormalities between display and touch domains. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Fujioka to count pulses of the second oscillator during high and low portions of the vertical synchronization signal and output a detection signal when the counts deviate from expected ranges, as a predictable use of known timing monitoring techniques. The claimed invention represents an obvious application of known synchronization-timing measurement techniques to a known dual-oscillator display/touch system. The rationale to support a conclusion that the claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods and the combination yields nothing more than predictable results to one of ordinary skill in the art.
As to claim 2, the combination of Fujioka and Chaki teach the driving circuit according to claim 1 (see above rejection), wherein to detect the cycle of the vertical synchronization signal according to the second clock signal, the determination circuit is configured to count a number of times that the second clock signal overlaps with at least one of the high level section or the low level section of the vertical synchronization signal (see Chaki at least fig. 1: counter 6 for counting the clocks generated between the extracted edge portions and col. 5 lines 1-3 “The number of clocks counted is therefore the distance between transitions produced in the synchronization signal.” – note a high-level section of a synchronization signal is bounded by edges; thus, counting clocks between those edges inherently measures the duration of the high-level section; col. 5 lines 7-9 “the latch circuits 5.sub.1 to 5.sub.N hold the hysteresis of the clock count values between transitions” – note successive measurements of clock counts between transitions necessarily include both high-level and low-level durations of the synchronization signal. Separating these measurements into distinct high-level and low-level sections would have been an obvious design variation to improve timing resolution, especially where different noise characteristics may occur during different signal levels. This is an obvious extension of disclosed timing measurement).
As to claim 3, the combination of Fujioka and Chaki teach the driving circuit according to claim 1 (see above rejection), wherein the determination circuit comprises:
a counter configured to: count, according to the second clock signal (see Fujioka at least fig. 1(a) frequency counter 11, oscillation circuit 7b),
at least one section from the high level section of the vertical synchronization signal; and generate the third count value according to the count (see Chaki at least fig. 1: counter 6 for counting the clocks generated between the extracted edge portions and col. 5 lines 1-3 “The number of clocks counted is therefore the distance between transitions produced in the synchronization signal.” – note a high-level section of a synchronization signal is bounded by edges; thus, counting clocks between those edges inherently measures the duration of the high-level section; col. 5 lines 7-9 “the latch circuits 5.sub.1 to 5.sub.N hold the hysteresis of the clock count values between transitions” – note successive measurements of clock counts between transitions necessarily include both high-level and low-level durations of the synchronization signal. Separating these measurements into distinct high-level and low-level sections would have been an obvious design variation to improve timing resolution, especially where different noise characteristics may occur during different signal levels. This is an obvious extension of disclosed timing measurement);
storage configured to store the threshold values of the third range (see Chaki at least Fig. 1: N-number of latch circuits 51 to 5N for holding the count values of clocks between the edge portions; Col. 6 lines 38-48 “an (N+1) number of inequality coincidence circuits 10.sub.0 to 10.sub.N as comparator means, for comparing the numbers of clocks generated between transitions of the synchronization pattern and the clock count values held by the latch circuits 5.sub.1 to 5.sub.N and the counter 6, and for outputting a signal indicating the coincidence between the number of clocks between the edge portions and the clock count values of the distances between transitions of the synchronization pattern in case the difference between the two numbers of clocks is within a certain range” – therefore Chaki teaches storage of count values and range-based thresholds); and
a controller configured to receive the third count value and the threshold values of the third range, and output the detection signal when the third count value is out of the third range (see Chaki at least col. 4 lines 13-17 “AND gate 8 as decision means .. to give a decision as to whether or not the signal transition patterns are coincident” – note by logical inversion, a detection signal is produced when the measured values fall outside the acceptable range).
As to claim 4, the combination of Fujioka and Chaki teach the driving circuit according to claim 3 (see above rejection), further comprising a frequency controller connected to the second oscillator, and configured to change a frequency of the second clock signal in response to the detection signal (see Fujioka at least fig. 1 and [0057] “correction of one of the liquid crystal driving frequency and the scanning frequency makes it possible to prevent the touch panel-sensed noise frequency and the liquid crystal driving noise frequency from overlapping each other.”).
As to claim 6, the combination of Fujioka and Chaki teach the driving circuit according to claim 4 (see above rejection), wherein the sensor driver comprises a touch controller configured to supply the touch signal to sensors (see Fujioka at least figs. 1: touch panel controller 4).
As to claim 7, the combination of Fujioka and Chaki teach the driving circuit according to claim 6 (see above rejection), wherein the sensor driver comprises the determination circuit and the frequency controller (see Fujioka at least fig. 1: correcting circuit 10 and frequency counter 11).
As to claim 8, the combination of Fujioka and Chaki teach the driving circuit according to claim 3 (see above rejection), further comprising a first frequency controller connected to the first oscillator, and configured to change a frequency of the first clock signal in response to the detection signal (see Fujioka at least fig. 1(b): frequency controller 11 connected to oscillation circuit 7a).
As to claim 10, the combination of Fujioka and Chaki teach the driving circuit according to claim 8 (see above rejection), wherein the display driver comprises: a data driver configured to supply a data signal to data lines; and a timing controller configured to control the data driver (see Fujioka at least fig. 2: source driver 51, data lines S, timing generator 5).
As to claim 11, the combination of Fujioka and Chaki teach the driving circuit according to claim 10 (see above rejection), wherein the display driver comprises the determination circuit and the first frequency controller (see Fujioka at least fig. 1: correcting circuit 10 and frequency counter 11).
As to claim 12, the combination of Fujioka and Chaki teach the driving circuit according to claim 10 (see above rejection), wherein the first frequency controller is configured to supply a control signal to the timing controller in response to the detection signal, and wherein the timing controller is configured to supply an oscillation change signal to the sensor driver in response to the control signal (see Fujioka at least figs. 1-2 and [0057] “correction of one of the liquid crystal driving frequency and the scanning frequency makes it possible to prevent the touch panel-sensed noise frequency and the liquid crystal driving noise frequency from overlapping each other.”).
As to claim 14, the combination of Fujioka and Chaki teach the driving circuit according to claim 1 (see above rejection), wherein the determination circuit comprises:
a counter configured to: count, according to the second clock signal (see Fujioka at least fig. 1(a) frequency counter 11, oscillation circuit 7b),
at least one section from the low level section of the vertical synchronization signal; and generate the fourth count value according to the count (see Chaki at least fig. 1: counter 6 for counting the clocks generated between the extracted edge portions and col. 5 lines 1-3 “The number of clocks counted is therefore the distance between transitions produced in the synchronization signal.” – note a high-level section of a synchronization signal is bounded by edges; thus, counting clocks between those edges inherently measures the duration of the high-level section; col. 5 lines 7-9 “the latch circuits 5.sub.1 to 5.sub.N hold the hysteresis of the clock count values between transitions” – note successive measurements of clock counts between transitions necessarily include both high-level and low-level durations of the synchronization signal. Separating these measurements into distinct high-level and low-level sections would have been an obvious design variation to improve timing resolution, especially where different noise characteristics may occur during different signal levels. This is an obvious extension of disclosed timing measurement);
storage configured to store the threshold values of the fourth range (see Chaki at least Fig. 1: N-number of latch circuits 51 to 5N for holding the count values of clocks between the edge portions; Col. 6 lines 38-48 “an (N+1) number of inequality coincidence circuits 10.sub.0 to 10.sub.N as comparator means, for comparing the numbers of clocks generated between transitions of the synchronization pattern and the clock count values held by the latch circuits 5.sub.1 to 5.sub.N and the counter 6, and for outputting a signal indicating the coincidence between the number of clocks between the edge portions and the clock count values of the distances between transitions of the synchronization pattern in case the difference between the two numbers of clocks is within a certain range” – therefore Chaki teaches storage of count values and range-based thresholds); and
a controller configured to receive the fourth count value and the threshold values of the fourth range, and output the detection signal when the fourth count value is out of the fourth range (see Chaki at least col. 4 lines 13-17 “AND gate 8 as decision means .. to give a decision as to whether or not the signal transition patterns are coincident” – note by logical inversion, a detection signal is produced when the measured values fall outside the acceptable range).
As to claim 16, the combination of Fujioka and Chaki teach the display device according to claim 15 (see above rejection),
wherein to detect the cycle of the vertical synchronization signal according to the second clock signal, the determination circuit is configured to count a number of times that the second clock signal overlaps with at least one of the high level section or the low level section of the vertical synchronization signal (see Chaki at least fig. 1: counter 6 for counting the clocks generated between the extracted edge portions and col. 5 lines 1-3 “The number of clocks counted is therefore the distance between transitions produced in the synchronization signal.” – note a high-level section of a synchronization signal is bounded by edges; thus, counting clocks between those edges inherently measures the duration of the high-level section; col. 5 lines 7-9 “the latch circuits 5.sub.1 to 5.sub.N hold the hysteresis of the clock count values between transitions” – note successive measurements of clock counts between transitions necessarily include both high-level and low-level durations of the synchronization signal. Separating these measurements into distinct high-level and low-level sections would have been an obvious design variation to improve timing resolution, especially where different noise characteristics may occur during different signal levels. This is an obvious extension of disclosed timing measurement),
wherein the determination circuit comprises:
a counter configured to count the cycle of the vertical synchronization signal according to the second clock signal, and generate the third count value or the fourth count value (see Fujioka at least fig. 1(a) frequency counter 11, oscillation circuit 7b; Chaki at least fig. 1: counter 6 for counting the clocks generated between the extracted edge portions);
storage configured to store the threshold values of the third range or the fourth range (see Chaki at least Fig. 1: N-number of latch circuits 51 to 5N for holding the count values of clocks between the edge portions; Col. 6 lines 38-48 “an (N+1) number of inequality coincidence circuits 10.sub.0 to 10.sub.N as comparator means, for comparing the numbers of clocks generated between transitions of the synchronization pattern and the clock count values held by the latch circuits 5.sub.1 to 5.sub.N and the counter 6, and for outputting a signal indicating the coincidence between the number of clocks between the edge portions and the clock count values of the distances between transitions of the synchronization pattern in case the difference between the two numbers of clocks is within a certain range” – therefore Chaki teaches storage of count values and range-based thresholds); and
a controller configured to receive the third count value or the fourth count value, and the threshold values of the third range or the fourth range, and output the detection signal when the third count value is out of the third range or the fourth count value is out of the fourth range (see Chaki at least col. 4 lines 13-17 “AND gate 8 as decision means .. to give a decision as to whether or not the signal transition patterns are coincident” – note by logical inversion, a detection signal is produced when the measured values fall outside the acceptable range).
Allowable Subject Matter
Claims 5, 9, 13 and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
None of the prior art of record teach:
“A driving circuit comprising: a display driver configured to generate a vertical synchronization signal according to a first clock signal of a first oscillator; a sensor driver configured to generate a touch signal according to a second clock signal of a second oscillator; and a determination circuit configured to: store threshold values of a third range or threshold values of a fourth range; detect a cycle of the vertical synchronization signal according to a third count value of the second clock signal included in a high level section of the vertical synchronization signal, or a fourth count value of the second clock signal included in a low level section of the vertical synchronization signal; and output a detection signal when the third count value is out of the third range or the fourth count value is out of the fourth range;
wherein the determination circuit comprises: a counter configured to: count, according to the second clock signal, at least one section from the high level section of the vertical synchronization signal; and generate the third count value according to the count; storage configured to store the threshold values of the third range; and a controller configured to receive the third count value and the threshold values of the third range, and output the detection signal when the third count value is out of the third range;
further comprising a frequency controller connected to the second oscillator, and configured to change a frequency of the second clock signal in response to the detection signal;
wherein, when the frequency of the second clock signal is changed by the frequency controller, the count value is changed to be included in the range.”;
“A driving circuit comprising: a display driver configured to generate a vertical synchronization signal according to a first clock signal of a first oscillator; a sensor driver configured to generate a touch signal according to a second clock signal of a second oscillator; and a determination circuit configured to: store threshold values of a third range or threshold values of a fourth range; detect a cycle of the vertical synchronization signal according to a third count value of the second clock signal included in a high level section of the vertical synchronization signal, or a fourth count value of the second clock signal included in a low level section of the vertical synchronization signal; and output a detection signal when the third count value is out of the third range or the fourth count value is out of the fourth range;
wherein the determination circuit comprises: a counter configured to: count, according to the second clock signal, at least one section from the high level section of the vertical synchronization signal; and generate the third count value according to the count; storage configured to store the threshold values of the third range; and a controller configured to receive the third count value and the threshold values of the third range, and output the detection signal when the third count value is out of the third range;
further comprising a first frequency controller connected to the first oscillator, and configured to change a frequency of the first clock signal in response to the detection signal;
wherein, when the frequency of the first clock signal is changed by the first frequency controller, the count value is changed to be included in the range.”;
“A driving circuit comprising: a display driver configured to generate a vertical synchronization signal according to a first clock signal of a first oscillator; a sensor driver configured to generate a touch signal according to a second clock signal of a second oscillator; and a determination circuit configured to: store threshold values of a third range or threshold values of a fourth range; detect a cycle of the vertical synchronization signal according to a third count value of the second clock signal included in a high level section of the vertical synchronization signal, or a fourth count value of the second clock signal included in a low level section of the vertical synchronization signal; and output a detection signal when the third count value is out of the third range or the fourth count value is out of the fourth range;
wherein the determination circuit comprises: a counter configured to: count, according to the second clock signal, at least one section from the high level section of the vertical synchronization signal; and generate the third count value according to the count; storage configured to store the threshold values of the third range; and a controller configured to receive the third count value and the threshold values of the third range, and output the detection signal when the third count value is out of the third range;
further comprising a first frequency controller connected to the first oscillator, and configured to change a frequency of the first clock signal in response to the detection signal;
wherein the display driver comprises: a data driver configured to supply a data signal to data lines; and a timing controller configured to control the data driver;
wherein the first frequency controller is configured to supply a control signal to the timing controller in response to the detection signal, and wherein the timing controller is configured to supply an oscillation change signal to the sensor driver in response to the control signal;
wherein the sensor driver comprises a second frequency controller connected to the second oscillator, and configured to change a frequency of the second clock signal in response to the oscillation change signal, and wherein, when the frequency of the second clock signal is changed by the second frequency controller, the third count value is changed to be included in the third range.”;
“A display device comprising: a display component comprising pixels connected to scan lines and data lines; a sensor component comprising first sensors and second sensors configured to sense an external input; a display driver configured to divide a first clock signal of a first oscillator, generate a vertical synchronization signal, and supply a data signal to the data lines; a sensor driver configured to divide a second clock signal of a second oscillator, and generate a touch signal to be supplied to the first sensors and/or the second sensors; and a determination circuit configured to: store threshold values of a third range or threshold values of a fourth range; detect a cycle of the vertical synchronization signal according to a third count value of the second clock signal included in a high level section of the vertical synchronization signal, or a fourth count value of the second clock signal included in a low level section of the vertical synchronization signal; and output a detection signal when the third count value is out of the third range or the fourth count value is out of the fourth range;
wherein to detect the cycle of the vertical synchronization signal according to the second clock signal, the determination circuit is configured to count a number of times that the second clock signal overlaps with at least one of the high level section or the low level section of the vertical synchronization signal, wherein the determination circuit comprises: a counter configured to count the cycle of the vertical synchronization signal according to the second clock signal, and generate the third count value or the fourth count value; storage configured to store the threshold values of the third range or the fourth range; and a controller configured to receive the third count value or the fourth count value, and the threshold values of the third range or the fourth range, and output the detection signal when the third count value is out of the third range or the fourth count value is out of the fourth range;
further comprising a frequency controller connected to the second oscillator, and configured to change a frequency of the second clock signal in response to the detection signal, wherein, when the frequency of the second clock signal is changed by the frequency controller, the third count value or the fourth count value is changed to be included in the range.”; and
“A display device comprising: a display component comprising pixels connected to scan lines and data lines; a sensor component comprising first sensors and second sensors configured to sense an external input; a display driver configured to divide a first clock signal of a first oscillator, generate a vertical synchronization signal, and supply a data signal to the data lines; a sensor driver configured to divide a second clock signal of a second oscillator, and generate a touch signal to be supplied to the first sensors and/or the second sensors; and a determination circuit configured to: store threshold values of a third range or threshold values of a fourth range; detect a cycle of the vertical synchronization signal according to a third count value of the second clock signal included in a high level section of the vertical synchronization signal, or a fourth count value of the second clock signal included in a low level section of the vertical synchronization signal; and output a detection signal when the third count value is out of the third range or the fourth count value is out of the fourth range;
wherein to detect the cycle of the vertical synchronization signal according to the second clock signal, the determination circuit is configured to count a number of times that the second clock signal overlaps with at least one of the high level section or the low level section of the vertical synchronization signal, wherein the determination circuit comprises: a counter configured to count the cycle of the vertical synchronization signal according to the second clock signal, and generate the third count value or the fourth count value; storage configured to store the threshold values of the third range or the fourth range; and a controller configured to receive the third count value or the fourth count value, and the threshold values of the third range or the fourth range, and output the detection signal when the third count value is out of the third range or the fourth count value is out of the fourth range;
further comprising a frequency controller connected to the first oscillator, and configured to change a frequency of the first clock signal in response to the detection signal, wherein, when the frequency of the first clock signal is changed by the frequency controller, the third count value or the fourth count value is changed to be included in the range.”
Conclusion
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/JENNIFER L ZUBAJLO/Examiner, Art Unit 2627 12/21/2025
/KE XIAO/Supervisory Patent Examiner, Art Unit 2627