Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10 September 2026 has been entered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The disclosure is objected to because of the following informalities:
Paragraph 94 of the specification as filed (page 20, lines 10–15) gives for the eighth duration DR8 the same signal levels as Paragraph 93 gives for the seventh duration DR7 [e.g., Instant Specification Paragraph 94: the first gate signal GW may have a low pulse and the bias control signal EB may have the high level.; Instant Specification Paragraph 93: the first gate signal GW may have a low pulse and the bias control signal EB may have the high level.].
That statement is inconsistent with FIG. 3, which shows the low pulse of the first gate signal GW in the seventh duration DR7 and the low pulse of the bias control signal EB in the eighth duration DR8, and with the description of the eighth duration elsewhere [e.g., Instant Specification Paragraph 103: in the eighth duration DR8, the seventh pixel switching element T7 and the eighth pixel switching element T8 are turned on.; Instant Specification Paragraph 88: The bias control signal EB may be applied to the control electrode of the eighth pixel switching element T8.].
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 5, 6 and 10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement.
The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 5, as amended on 10 September 2026, recites wherein the bias voltage of the holding frame is constant in the holding frame at a second level greater than a first level, and wherein the bias voltage of the writing frame is constant in the writing frame at the first level.
The specification as filed describes the bias voltage of the holding frame and the bias voltage of the writing frame of the elected embodiment only in relation to each other [e.g., Instant Specification Paragraph 128: the bias voltage VBIAS2 of the holding frame may be set to be greater than the bias voltage VBIAS1 of the writing frame.; Instant Specification Paragraph 132: The bias voltage VBIAS2 of the holding frame may be set greater than the bias voltage VBIAS1 of the writing frame.; Fig. 14: VBIAS1, VBIAS2];
FIG. 14 labels the writing frame and the holding frames with those two voltages and shows no waveform of the bias voltage, and neither the drawings nor the description states that the bias voltage is constant within a holding frame or within a writing frame.
The specification uses the word “constant” of the bias voltage only for the embodiments in which the bias voltage of the writing frame and the bias voltage of the holding frame are equal [e.g., Instant Specification Paragraph 115: the power voltage generator 700 may generate the bias voltage VBIAS having a constant level regardless of the writing frame and the holding frame.; Instant Specification Paragraph 158: the power voltage generator 700 may generate the bias voltage VBIAS having a constant level regardless of the writing frame and the holding frame.].
The description of FIG. 14 adopts the earlier embodiment only with an exception [e.g., Instant Specification Paragraph 127: except for the method of compensating the insufficient degree of the bias.], and the excepted matter is the bias voltage itself: the one level that is the same in the writing frame and in the holding frame is what the embodiment of FIG. 14 replaces.
The remarks filed on 10 September 2026 identify FIG. 16 and its accompanying description as the support for the amendment (page 6) and state that FIG. 14 shows the recited constant levels (page 8).
FIG. 16 is a circuit diagram of a pixel whose accompanying description is of the equal-level embodiment (Paragraph 158 as filed), and FIG. 14, as described above, labels the frames with the two voltages and shows no waveform of the bias voltage.
Claims 6 and 10 depend from claim 5 and include the same recitations.
Claim Rejections - 35 USC § 102 / 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were effectively filed absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned at the time a later invention was effectively filed in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5 and 6 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as anticipated by Kim et al (US 2021/0027696 A1; hereinafter Kim ’696);
or, in the alternative, under 35 U.S.C. 103 as obvious over Kim ’696 (US 2021/0027696 A1) in view of Chung et al (US 2022/0101785 A1; hereinafter Chung).
Regarding claim 5, Kim ’696 discloses a display apparatus [e.g., Paragraph 215: a display device 1001 includes a pixel unit 100, a first scan driver 200, a second scan driver 300, a third scan driver 400, an emission driver 500, a fourth scan driver 600′, a data driver 700, and a timing controller 800′.; Fig. 11: 1001] comprising:
a display panel having a pixel including a driving switching element and a light emitting element; [e.g., Paragraph 230: a light-emitting element LD, first to eighth transistors M1 to M8, and a storage capacitor Cst.; Paragraph 18: a first transistor which includes a first electrode which is connected to a first node electrically connected to a first power source and controls a driving current based on a voltage of a second node; Fig. 11: 100, PX; Fig. 12D: 20, M1, LD]
a driving controller configured to determine a driving frequency [e.g., Paragraph 257: The timing controller 800′ may output the first gate start pulse GSP1, the second gate start pulse GSP2, and the fourth gate start pulse GSP4 at the same frequency (second frequency) as the image refresh rate RR; Paragraph 257: One frame period of a display device may be determined by an output period of the first gate start pulse GSP1.; Fig. 11: 800′]
varied according to input image data or a driving mode; [e.g., Paragraph 50: The display device 1000 may display an image at various image refresh rates (driving frequency or screen refresh rate) according to driving conditions.; Paragraph 51: a refresh rate for driving a moving picture may be a frequency of about 60 Hz or more, for example, 120 Hz.; Paragraph 214: the display device of FIG. 11 is the same as or similar to the display device of FIG. 1 except for a configuration of a fourth scan driver; Paragraph 53: The timing controller 800 may receive input image data IRGB and timing signals Vsync, Hsync, DE, and CLK from a host system]
a gate driver configured to output a gate signal and a bias control signal to the pixel; [e.g., Paragraph 8: a scan driver which supplies a bias scan signal to each of the third scan lines at a first frequency and supplies a scan signal to each of the first scan line and the second scan line at a second frequency which corresponds to an image refresh rate of each of the pixels; Paragraph 222: The first scan driver 200 supplies scan signals (writing scan signals) to first scan lines S1 in response to the first gate start pulse GSP1.; Paragraph 224: The third scan driver 400 may always supply scan signals (bias scan signals) to the third scan lines S3 at a first frequency irrespective of an image refresh rate.; Fig. 11: 200, 400, S1, S3]
an emission driver configured to output an emission signal to the pixel; [e.g., Paragraph 226: The emission driver 500 supplies emission control signals to emission control lines E1 in response to an emission start pulse ESP1.; Fig. 11: 500, E]
a data driver configured to output a data voltage to the pixel; and [e.g., Paragraph 221: The data driver 700 supplies data signals to data lines D in response to a data driving control signal DCS.; Fig. 11: 700, D]
a power voltage generator configured to generate a bias voltage, [e.g., Paragraph 255: voltages of the first initialization power source Aint and the bias power source VEH may be output and controlled from a certain power driver.; Paragraph 233: the fourth transistor M4 is connected between a first node N1 and an emission control line Ei or between the first node N1 and the bias power source VEH.; Fig. 12D: VEH, M4, N1, S3i]
wherein the bias voltage of a holding frame [e.g., Paragraph 253: the driving method of FIGS. 14A to 14D is the same as or similar to the driving method of FIGS. 7A to 7D except for a driving method of a fourth gate pulse GSP4, a first initialization power source Aint, and a bias power source VEH; Paragraph 193: when the display device 1000 is driven at the image refresh rate RR of 60 Hz, one frame period may include one display scan period DSP and three consecutive self-scan periods SSP.; Paragraph 14: The first scan driver and the second scan driver may not supply the writing scan signal and the compensation scan signal during a self-scan period in the one frame period.; Paragraph 259: the voltage level of the bias power source VEH may be increased in response to the repetition of the self-scan period SSP.; Fig. 14C: VEH in the second and third SSP]
is greater than the bias voltage of a writing frame, [e.g., Paragraph 245: The display scan period may include a period in which a data signal corresponding to an output imaged is written.; Paragraph 261: the voltage level of the bias power source VEH returns to a value set to be the lowest in the display scan period DSP again.; Fig. 14C: VEH in the DSP and the first SSP]
wherein the bias voltage of the holding frame is constant in the holding frame at a second level greater than a first level, and [e.g., Paragraph 260: the voltage level of the bias power source VEH may be increased at about 8.3 ms intervals so as to correspond to 120 Hz.; Fig. 14C: VEH in the second and third SSP]
wherein the bias voltage of the writing frame is constant in the writing frame at the first level [e.g., Paragraph 261: the voltage level of the bias power source VEH returns to a value set to be the lowest in the display scan period DSP again.; Fig. 14C: VEH in the DSP and the first SSP] (e.g., see Paragraphs 213–265).
Should it be shown that Kim ’696 discloses a driving controller configured to determine a driving frequency varied according to input image data or a driving mode with insufficient specificity:
Chung discloses a driving controller [e.g., Chung, Paragraph 28: the electroluminescent display device 100 includes a display panel 110 including a plurality of pixels, a gate driver 130 supplying a gate signal to each of the plurality of pixels, and a data driver 140 supplying a data signal to each of the plurality of pixels, and an active control signal generator 150 supplying a light emission signal to each of the plurality of pixels and a timing controller 120.; Paragraph 29: the timing controller 120 controls the gate driver 130, the data driver 140, and the light emission signal generator 150.; Fig. 1: 120]
configured to determine a driving frequency [e.g., Chung, Paragraph 31: the timing controller 120 generates signals related to driving such that the pixels are driven in a variable refresh rate VRR mode or driven to be switchable between a first refresh rate and a second refresh rate.; Paragraph 31: the timing controller 120 simply changes the speed of a clock signal, generates a synchronization signal to generate a horizontal blank or a vertical blank, or drives the gate driver 130 in a mask method, thereby driving the pixel at various refresh rates.]
varied according to input image data or a driving mode [e.g., Chung, Paragraph 9: A refresh rate is changed in units of a frame in accordance with an image.; Paragraph 57: activates pixels by increasing the refresh rate at which the data voltage Vdata is updated when high-speed driving is required, and drives pixels by reducing the refresh rate when it is necessary to reduce power consumption or low-speed driving is required.].
Kim ’696 and Chung are analogous art, each being directed to a light emitting display device that is driven at a variable refresh rate and in which a bias is applied to the driving transistor of the pixel both in the frames in which a data voltage is written and in the frames in which the written data voltage is held [e.g., Kim ’696, Paragraph 14: the third scan driver may supply the bias scan signal in the self-scan period so that bias may be applied to a driving transistor included in each of the pixels.] [e.g., Chung, Paragraph 9: The frame is distinguished into a refresh frame for writing a data voltage and a hold frame for maintaining the data voltage written in the refresh frame.; Paragraph 71: on-bias stress can be defined as an operation to apply directly a suitable bias voltage (for example, V1=V1_H) to the driving transistor DT during non-light emission periods.].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the timing controller of Kim ’696 determine the image refresh rate in accordance with the image, as taught by Chung, so as to increase the refresh rate when high-speed driving is required and to reduce the refresh rate when power consumption is to be reduced [e.g., Chung, Paragraph 57: activates pixels by increasing the refresh rate at which the data voltage Vdata is updated when high-speed driving is required, and drives pixels by reducing the refresh rate when it is necessary to reduce power consumption or low-speed driving is required.]. KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Regarding claim 6, Kim ’696 discloses wherein when the driving frequency is a first driving frequency, the display panel only has the writing frame, and [e.g., Paragraph 190: one frame period may include one display scan period DSP and one self-scan period SSP when the image refresh rate RR is 120 Hz.; Paragraph 157: one frame period may correspond to the first image refresh rate.; Fig. 14A: RR = 120Hz, DSP, SSP, GSP1]
wherein when the driving frequency is a second driving frequency less than the first driving frequency, the display panel has the writing frame and the holding frame [e.g., Paragraph 193: when the display device 1000 is driven at the image refresh rate RR of 60 Hz, one frame period may include one display scan period DSP and three consecutive self-scan periods SSP.; Paragraph 14: The first scan driver and the second scan driver may not supply the writing scan signal and the compensation scan signal during a self-scan period in the one frame period.; Fig. 14C: RR = 60Hz, DSP, SSP].
The alternative stated as to claim 5 changes nothing as to claim 6, the further limitations of which are disclosed by Kim ’696 as set out above.
Should it be shown that Kim ’696 discloses wherein when the driving frequency is a first driving frequency, the display panel only has the writing frame with insufficient specificity:
Chung discloses wherein when the driving frequency is a first driving frequency, the display panel only has the writing frame [e.g., Chung, Paragraph 59: When the pixel is driven at the refresh rate of 120 Hz, the pixel can be driven only by the refresh frame.], and
wherein when the driving frequency is a second driving frequency less than the first driving frequency, the display panel has the writing frame and the holding frame [e.g., Chung, Paragraph 60: When the pixel is driven at the refresh rate of 60 Hz, the refresh frame and the hold frame may be alternately driven.; Fig. 5: Refresh, Hold].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to drive the display panel of Kim ’696, at a first and highest image refresh rate, with display scan periods only, as taught by Chung, so that the data voltage is updated in every period when high-speed driving is required [e.g., Chung, Paragraph 57: activates pixels by increasing the refresh rate at which the data voltage Vdata is updated when high-speed driving is required, and drives pixels by reducing the refresh rate when it is necessary to reduce power consumption or low-speed driving is required.],
Kim ’696 itself contemplating image refresh rates above its 120 Hz example [e.g., Kim ’696, Paragraph 52: the display device 1000 may display an image even at an image refresh rate of 120 Hz or more, for example, 240 Hz or 480 Hz.]. KSR, 550 U.S. 398.
The applied reference has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Claims 5 and 6 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as anticipated by In et al (US 2021/0134210 A1; hereinafter In);
or, in the alternative, under 35 U.S.C. 103 as obvious over In (US 2021/0134210 A1) in view of Chung (US 2022/0101785 A1).
Regarding claim 5, In discloses a display apparatus [e.g., Paragraph 55: the display device 1000 may include a pixel unit 100, scan drivers 200, 300, and 400, an emission driver 500, a data driver 600, and a timing controller 700. The display device 1000 may further include a power supply 800.; Fig. 1: 1000] comprising:
a display panel having a pixel including a driving switching element and a light emitting element; [e.g., Paragraph 94: the pixel 10 may include a light emitting device LD, first to eighth transistors M1 to M8, and a storage capacitor Cst.; Paragraph 97: A first electrode of the first transistor M1 (or driving transistor) may be connected to a first node N1; Fig. 1: 100, PX; Fig. 2: 10, M1, LD]
a driving controller configured to determine a driving frequency [e.g., Paragraph 61: The timing controller 700 may generate a first scan driving control signal SCS1, a second scan driving control signal SCS2, a third scan driving control signal SCS3, an emission driving control signal ECS, and a data driving control signal DCS in accordance with synchronization signals supplied from the outside.; Paragraph 59: the display device 1000 may control an output frequency of the first and second scan drivers 200 and 300, and an output frequency of the data driver 600, which corresponds to the output frequency of the first and second scan drivers 200 and 300 according to driving conditions.; Fig. 1: 700]
varied according to input image data or a driving mode; [e.g., Paragraph 57: The display device 1000 may display an image at various driving frequencies (e.g., image refresh rates or screen refresh rates) according to driving conditions.; Paragraph 118: the display device 1000 may be driven in a first mode in which an image is displayed at a first frequency.; Paragraph 144: the display device 1000 may be driven in a second mode, in which an image is displayed through the low frequency driving of the display device 1000.]
a gate driver configured to output a gate signal and a bias control signal to the pixel; [e.g., Paragraph 71: the first scan driver 200 may sequentially supply a first scan signal to the first scan lines S1.; Paragraph 78: the third scan driver 400 may supply the third scan signal to the third scan lines in the first period and a second period.; Paragraph 56: at least some of scan drivers may be integrated as a single driving circuit, a single module, etc. according to designs.; Fig. 1: 200, 400, S1, S3]
an emission driver configured to output an emission signal to the pixel; [e.g., Paragraph 82: supply an emission control signal to the emission control lines E based on the emission driving control signal ECS.; Fig. 1: 500, E]
a data driver configured to output a data voltage to the pixel; and [e.g., Paragraph 69: The data driver 600 supplies a data signal to the data lines D in accordance with the data driving control signal DCS.; Fig. 1: 600, D]
a power voltage generator configured to generate a bias voltage, [e.g., Paragraph 89: The power supply 800 may supply at least one of the first power source VDD, the second power source VSS, the initialization power source Vint, and the bias power source Vbs, based on the power control signal PCS to the pixel unit.; Paragraph 150: When the fourth transistor M4 is turned on, the voltage of the bias power source Vbs may be supplied to the first node N1, and the first transistor M1 may be in the on-bias state; Fig. 1: 800, Vbs; Fig. 2: M4, Vbs, N1]
wherein the bias voltage of a holding frame [e.g., Paragraph 80: is a period in which an image programmed in the first period is held, the second period may be defined as a holding sub-frame.; Paragraph 180: the power supply 800 may supply the bias power source Vbs having different voltage levels in the first period P1 and the second period P2.] is greater than the bias voltage of a writing frame, [e.g., Paragraph 73: The first period may be a period in which a data signal corresponding to an image is written to the pixels PX. Accordingly, the first period may be defined as a data programming sub-frame.; Paragraph 181: in some exemplary embodiments, the second voltage level may be higher than the first voltage level. That is, in the second period P2, an on-bias stronger than that in the first period P1 may be applied to the first transistor M1.]
wherein the bias voltage of the holding frame is constant in the holding frame [e.g., Paragraph 21: supply the bias power source having a second voltage level different from the first voltage level in the second period.; Fig. 8: P2, Vbs] at a second level greater than a first level, and [e.g., Paragraph 190: the voltage level of the bias power source Vbs may be increased corresponding to the repetition of the second period P2.; Paragraph 191: the voltage level of the bias power source Vbs returns to the lowest set value in the first period P1.]
wherein the bias voltage of the writing frame is constant in the writing frame at the first level [e.g., Paragraph 21: The power supply may supply the bias power source having a first voltage level in the first period; Paragraph 191: the voltage level of the bias power source Vbs returns to the lowest set value in the first period P1.; Fig. 7: P1, Vbs] (e.g., see Paragraphs 54–89 and 177–194).
Should it be shown that In discloses a driving controller configured to determine a driving frequency varied according to input image data or a driving mode with insufficient specificity:
Chung discloses a driving controller [e.g., Chung, Paragraph 28: the electroluminescent display device 100 includes a display panel 110 including a plurality of pixels, a gate driver 130 supplying a gate signal to each of the plurality of pixels, and a data driver 140 supplying a data signal to each of the plurality of pixels, and an active control signal generator 150 supplying a light emission signal to each of the plurality of pixels and a timing controller 120.; Paragraph 29: the timing controller 120 controls the gate driver 130, the data driver 140, and the light emission signal generator 150.; Fig. 1: 120]
configured to determine a driving frequency [e.g., Chung, Paragraph 31: the timing controller 120 generates signals related to driving such that the pixels are driven in a variable refresh rate VRR mode or driven to be switchable between a first refresh rate and a second refresh rate.; Paragraph 31: the timing controller 120 simply changes the speed of a clock signal, generates a synchronization signal to generate a horizontal blank or a vertical blank, or drives the gate driver 130 in a mask method, thereby driving the pixel at various refresh rates.]
varied according to input image data or a driving mode [e.g., Chung, Paragraph 9: A refresh rate is changed in units of a frame in accordance with an image.; Paragraph 57: activates pixels by increasing the refresh rate at which the data voltage Vdata is updated when high-speed driving is required, and drives pixels by reducing the refresh rate when it is necessary to reduce power consumption or low-speed driving is required.].
In and Chung are analogous art, each being directed to a light emitting display device that is driven at a variable refresh rate and in which a bias voltage is applied to the driving transistor of the pixel both in the frames in which a data voltage is written and in the frames in which the written data voltage is held [e.g., In, Paragraph 150: When the fourth transistor M4 is turned on, the voltage of the bias power source Vbs may be supplied to the first node N1, and the first transistor M1 may be in the on-bias state; Paragraph 78: the third scan driver 400 may supply the third scan signal to the third scan lines in the first period and a second period.] [e.g., Chung, Paragraph 9: The frame is distinguished into a refresh frame for writing a data voltage and a hold frame for maintaining the data voltage written in the refresh frame.; Paragraph 71: on-bias stress can be defined as an operation to apply directly a suitable bias voltage (for example, V1=V1_H) to the driving transistor DT during non-light emission periods.].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the timing controller of In determine the image refresh rate in accordance with the image, as taught by Chung, so as to increase the refresh rate when high-speed driving is required and to reduce the refresh rate when power consumption is to be reduced [e.g., Chung, Paragraph 57: activates pixels by increasing the refresh rate at which the data voltage Vdata is updated when high-speed driving is required, and drives pixels by reducing the refresh rate when it is necessary to reduce power consumption or low-speed driving is required.]. KSR, 550 U.S. 398.
Regarding claim 6, In discloses wherein when the driving frequency is a first driving frequency, the display panel only has the writing frame, and [e.g., Paragraph 12: The first period may be repeated, when an image refresh rate is a first frequency; Paragraph 87: when the first frequency and the second frequency are the same, only the first period may be repeated.]
wherein when the driving frequency is a second driving frequency less than the first driving frequency, the display panel has the writing frame and the holding frame [e.g., Paragraph 12: the second period may be activated at least once just after the first period, when the image refresh rate is less than the first frequency.; Paragraph 86: when the second frequency (i.e., an output frequency of the emission control signal) is 120 Hz and the first frequency (i.e., the image refresh rate) is 60 Hz, the first period and one second period may be alternately repeated.; Fig. 4: P1, P2].
The alternative stated as to claim 5 changes nothing as to claim 6, the further limitations of which are disclosed by In as set out above.
Applicant cannot rely upon the certified copy of the foreign priority application to overcome this rejection because a translation of said application has not been made of record in accordance with 37 CFR 1.55. When an English language translation of a non-English language foreign application is required, the translation must be that of the certified copy (of the foreign application as filed) submitted together with a statement that the translation of the certified copy is accurate. See MPEP §§ 215 and 216.
The applied reference has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Claim Rejections - 35 USC § 103
Claims 5, 6 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2022/0076627 A1; hereinafter Kim ’627) in view of Chung (US 2022/0101785 A1).
Note: strikethrough marks claim subject matter not expressly disclosed by the named reference, or not expressly recited by the named patent.
Regarding claim 5, Kim ’627 discloses a display apparatus [e.g., Paragraph 42: The electronic display 12 includes display driver circuitry that includes scan driver circuitry 50 and data driver circuitry 52 that can program the image data 48 onto display pixels 54.; Fig. 6: 12] comprising:
a display panel having a pixel including a driving switching element and a light emitting element; [e.g., Paragraph 44: The display pixel 54 of FIG. 7 includes an organic light emitting diode (OLED) 70 that emits an amount of light that varies depending on the electrical current through the OLED 70. A driving transistor DTFT provides this electrical current.; Fig. 6: 12, 54; Fig. 7: DTFT, 70]
when the image data corresponds to a document or e-book, the image data 48 may be refreshed at a lower refresh rate (e.g., more than 1 Hz, 1 Hz, 10 Hz, 30 Hz, 60 Hz), whereas when the image data corresponds to a frame of a movie, game, or movement on a graphical user interface, the image data may be refreshed at a higher refresh rate (e.g., 24 Hz, 30 Hz, 60 Hz, 120 Hz, 240 Hz).]
a gate driver configured to output a gate signal and a bias control signal to the pixel; [e.g., Paragraph 43: The scan driver 50 may provide scan signals (e.g., pixel reset, data enable, on-bias stress) on scan lines 56 to control the display pixels 54 by row.; Fig. 6: 50, 56]
a data driver configured to output a data voltage to the pixel; and [e.g., Paragraph 42: The electronic display 12 includes display driver circuitry that includes scan driver circuitry 50 and data driver circuitry 52 that can program the image data 48 onto display pixels 54.; Paragraph 43: the scan driver 50 may cause a row of the display pixels 54 to become enabled to receive a portion of the image data 48 from data lines 58 from the data driver 52.; Fig. 6: 52, 58]
a power voltage generator configured to generate a bias voltage, [e.g., Paragraph 45: A switch 76 may selectively provide a bias voltage Vbias from a first bias voltage supply 78.; Paragraph 51: different bias voltage values Vbias 96 and Vreset 98 may be respectively supplied on the first bias voltage supply 78 and the second bias voltage supply 82 for different subframes 90 and 92.; Fig. 7: 76, 78, Vbias]
wherein the bias voltage of a holding frame [e.g., Paragraph 48: Image Frame 1 and Image Frame 2 may be divided into an initial active subframe 90 where image data is programmed and many subsequent blanking subframes 92 where the image data does not change.; Fig. 8: 92, 96] is greater than the bias voltage of a writing frame, [e.g., Paragraph 51: the bias voltage Vbias 96 starts relatively lower for the initial active subframe 90 and gradually increases for subsequent blanking subframes 92.; Fig. 8: 90, 96]
wherein the bias voltage of the holding frame is constant in the holding frame at a second level greater than a first level, and [e.g., Paragraph 53: a second bias voltage value for Vbias may be applied for the blanking subframe 92 that follows the initial active subframe 90.; Fig. 8: 92, 96]
wherein the bias voltage of the writing frame is constant in the writing frame at the first level [e.g., Paragraph 52: a first bias voltage value for Vbias may be applied by briefly closing the switch 76 at the start of the initial active subframe 90 for a pulse 110 before the display pixel 54 begins to emit light; Fig. 8: 90, 96] (e.g., see Paragraphs 42–57).
Kim ’627 does not expressly disclose a driving controller that is configured to determine the driving frequency, or an emission driver configured to output an emission signal to the pixel.
Chung discloses a driving controller [e.g., Chung, Paragraph 28: the electroluminescent display device 100 includes a display panel 110 including a plurality of pixels, a gate driver 130 supplying a gate signal to each of the plurality of pixels, and a data driver 140 supplying a data signal to each of the plurality of pixels, and an active control signal generator 150 supplying a light emission signal to each of the plurality of pixels and a timing controller 120.; Paragraph 29: the timing controller 120 controls the gate driver 130, the data driver 140, and the light emission signal generator 150.; Fig. 1: 120]
configured to determine a driving frequency varied according to input image data or a driving mode [e.g., Chung, Paragraph 31: the timing controller 120 generates signals related to driving such that the pixels are driven in a variable refresh rate VRR mode or driven to be switchable between a first refresh rate and a second refresh rate.; Paragraph 31: the timing controller 120 simply changes the speed of a clock signal, generates a synchronization signal to generate a horizontal blank or a vertical blank, or drives the gate driver 130 in a mask method, thereby driving the pixel at various refresh rates.; Paragraph 9: A refresh rate is changed in units of a frame in accordance with an image.]; and
an emission driver configured to output an emission signal to the pixel [e.g., Chung, Paragraph 35: receives the light emission signal EM through the light emission line EL; Fig. 1: 150, EL, EM].
Kim ’627 and Chung are analogous art, each being directed to a light emitting display that is refreshed at a variable rate and in which a bias voltage is applied to the driving transistor of the pixel both in the frames in which image data is programmed and in the frames in which it is not [e.g., Kim ’627, Paragraph 48: Image Frame 1 and Image Frame 2 may be divided into an initial active subframe 90 where image data is programmed and many subsequent blanking subframes 92 where the image data does not change.; Paragraph 45: A switch 76 may selectively provide a bias voltage Vbias from a first bias voltage supply 78.] [e.g., Chung, Paragraph 9: The frame is distinguished into a refresh frame for writing a data voltage and a hold frame for maintaining the data voltage written in the refresh frame.; Paragraph 71: on-bias stress can be defined as an operation to apply directly a suitable bias voltage (for example, V1=V1_H) to the driving transistor DT during non-light emission periods.].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to provide the electronic display of Kim ’627 with the timing controller of Chung, determining the refresh rate in accordance with the image and controlling the scan driver and the data driver accordingly,
because Kim ’627 refreshes the image data at a lower or a higher rate depending on the image [e.g., Kim ’627, Paragraph 46: when the image data corresponds to a document or e-book, the image data 48 may be refreshed at a lower refresh rate (e.g., more than 1 Hz, 1 Hz, 10 Hz, 30 Hz, 60 Hz), whereas when the image data corresponds to a frame of a movie, game, or movement on a graphical user interface, the image data may be refreshed at a higher refresh rate (e.g., 24 Hz, 30 Hz, 60 Hz, 120 Hz, 240 Hz).] and
the timing controller of Chung is a known means of driving the pixels at such various refresh rates [e.g., Chung, Paragraph 31: the timing controller 120 generates signals related to driving such that the pixels are driven in a variable refresh rate VRR mode or driven to be switchable between a first refresh rate and a second refresh rate.; Paragraph 31: the timing controller 120 simply changes the speed of a clock signal, generates a synchronization signal to generate a horizontal blank or a vertical blank, or drives the gate driver 130 in a mask method, thereby driving the pixel at various refresh rates.]; and
to provide the emission driver and emission signal of Chung, because Kim ’627 applies its bias voltages while the display pixels are not emitting light [e.g., Kim ’627, Paragraph 5: Between each subframe, the display pixels may stop emitting light for a very brief moment while certain bias voltages are applied to the display pixels.] and
Chung applies the bias voltage to the driving transistor during non-light emission periods, its pixels receiving a light emission signal [e.g., Chung, Paragraph 71: on-bias stress can be defined as an operation to apply directly a suitable bias voltage (for example, V1=V1_H) to the driving transistor DT during non-light emission periods.; Paragraph 35: receives the light emission signal EM through the light emission line EL],
Kim ’627 leaving the pixel circuitry open [e.g., Kim ’627, Paragraph 44: The display pixels 54 may use any suitable circuitry. A simplified example of a display pixel 54 appears in FIG. 7.]. KSR, 550 U.S. 398.
Regarding claim 6, Kim ’627 discloses
wherein when the driving frequency is a second driving frequency less than the first driving frequency, the display panel has the writing frame and the holding frame [e.g., Paragraph 48: Image Frame 1 and Image Frame 2 may be divided into an initial active subframe 90 where image data is programmed and many subsequent blanking subframes 92 where the image data does not change.; Paragraph 48: the frequency of the subframes 90 and 92 may remain constant (e.g., 120 Hz or 240 Hz), while the frequency of image frames varies, by adding or subtracting blanking subframes 92.; Fig. 8: 90, 92].
Kim ’627 does not expressly disclose that, when the driving frequency is a first driving frequency, the display panel only has the writing frame.
Chung discloses wherein when the driving frequency is a first driving frequency, the display panel only has the writing frame [e.g., Chung, Paragraph 59: When the pixel is driven at the refresh rate of 120 Hz, the pixel can be driven only by the refresh frame.], and
wherein when the driving frequency is a second driving frequency less than the first driving frequency, the display panel has the writing frame and the holding frame [e.g., Chung, Paragraph 60: When the pixel is driven at the refresh rate of 60 Hz, the refresh frame and the hold frame may be alternately driven.; Fig. 5: Refresh, Hold].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to drive the display panel of Kim ’627, at a first and highest refresh rate, with active subframes only, as taught by Chung, so that the image data is updated in every subframe when high-speed driving is required [e.g., Chung, Paragraph 57: activates pixels by increasing the refresh rate at which the data voltage Vdata is updated when high-speed driving is required, and drives pixels by reducing the refresh rate when it is necessary to reduce power consumption or low-speed driving is required.],
Kim ’627 itself varying the frequency of the image frames by adding or subtracting blanking subframes [e.g., Kim ’627, Paragraph 48: the frequency of the subframes 90 and 92 may remain constant (e.g., 120 Hz or 240 Hz), while the frequency of image frames varies, by adding or subtracting blanking subframes 92.]. KSR, 550 U.S. 398.
Regarding claim 10, Kim ’627 discloses wherein a width of the bias control signal to apply the bias voltage to the driving switching element in the writing frame [e.g., Paragraph 52: a first bias voltage value for Vbias may be applied by briefly closing the switch 76 at the start of the initial active subframe 90 for a pulse 110 before the display pixel 54 begins to emit light]
a second bias voltage value for Vbias may be applied by briefly closing the switch 76 at the start of the blanking subframe 92 for a pulse 120 before the display pixel 54 begins to emit light].
Kim ’627 does not expressly disclose that the width of the bias control signal in the writing frame is equal to the width of the bias control signal in the holding frame, Kim ’627 stating only that the durations may differ in some embodiments [e.g., Kim ’627, Paragraph 53: In some embodiments, the duration of pulses 120 and 122 that are used for blanking subframes 92 may differ from those of the pulses 110 and 112.].
Chung discloses wherein a width of the bias control signal to apply the bias voltage to the driving switching element [e.g., Chung, Paragraph 54: The fifth transistor T5 includes the first electrode which is connected to the third node N3, the second electrode which receives the first bias voltage V1, and the gate electrode which receives a second scan signal SC2.; Paragraph 70: the low second scan signal SC2 is input, and the fifth and sixth transistors T5 and T6 are turned on.; Fig. 3B: SC2(n), T5, DT]
in the writing frame is equal to a width of the bias control signal in the holding frame [e.g., Chung, Paragraph 91: for convenience of the driving circuit, the second scan signal SC2 is driven in the same manner as the second scan signal SC2 of the refresh frame; Fig. 4A: SC2(n)].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to drive the bias control signal of Kim ’627 in the blanking subframes in the same manner as in the active subframe, as taught by Chung, for the convenience of the driving circuit [e.g., Chung, Paragraph 91: for convenience of the driving circuit, the second scan signal SC2 is driven in the same manner as the second scan signal SC2 of the refresh frame]. KSR, 550 U.S. 398.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim ’696 (US 2021/0027696 A1) in view of Chung (US 2022/0101785 A1).
Claim 10 depends from claim 5.
Kim ’696 discloses the display apparatus of claim 5, or Kim ’696 in view of Chung renders it obvious, as set out in paragraph 12 above.
Regarding claim 10, Kim ’696 discloses wherein a width of the bias control signal to apply the bias voltage to the driving switching element in the writing frame [e.g., Paragraph 247: The fourth and seventh transistors M4 and M7 are turned on in response to a scan signal (bias scan signal) supplied to the third scan line S3i and the emission control signal supplied to the emission control line Ei, respectively, in the bias period B_P. Accordingly, on-bias may be applied to the first transistor M1; Fig. 13: B_P, S3i]
the third scan driver 400 may output the scan signals in a display scan period and a self-scan period.; Paragraph 14: the third scan driver may supply the bias scan signal in the self-scan period so that bias may be applied to a driving transistor included in each of the pixels.].
Kim ’696 does not expressly disclose that the width of the bias control signal in the writing frame is equal to the width of the bias control signal in the holding frame, although Kim ’696 supplies the bias scan signal in the display scan period and in the self-scan period in response to one start pulse output at one constant frequency [e.g., Kim ’696, Paragraph 224: The third scan driver 400 supplies scan signals to third scan lines S3 in response to the third gate start pulse GSP3.; Paragraph 224: the third scan driver 400 may output the scan signals in a display scan period and a self-scan period.; Paragraph 256: the timing controller 800′ may output the emission start pulse ESP and the third gate start pulse GSP3 at a constant frequency (first frequency), for example, 240 Hz.; Fig. 14C: GSP3];
the express teaching of Chung is relied upon in preference.
Chung discloses wherein a width of the bias control signal to apply the bias voltage to the driving switching element [e.g., Chung, Paragraph 54: The fifth transistor T5 includes the first electrode which is connected to the third node N3, the second electrode which receives the first bias voltage V1, and the gate electrode which receives a second scan signal SC2.; Paragraph 70: the low second scan signal SC2 is input, and the fifth and sixth transistors T5 and T6 are turned on.; Fig. 3B: SC2(n), T5, DT]
in the writing frame is equal to a width of the bias control signal in the holding frame [e.g., Chung, Paragraph 91: for convenience of the driving circuit, the second scan signal SC2 is driven in the same manner as the second scan signal SC2 of the refresh frame; Fig. 4A: SC2(n)].
Kim ’696 and Chung are analogous art for the reasons given in paragraph 12 above. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to drive the bias scan signal of Kim ’696 in the self-scan period in the same manner as in the display scan period, as taught by Chung, for the convenience of the driving circuit [e.g., Chung, Paragraph 91: for convenience of the driving circuit, the second scan signal SC2 is driven in the same manner as the second scan signal SC2 of the refresh frame]. KSR, 550 U.S. 398.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
U.S. Patent No. 11,217,149 B2, U.S. Patent No. 11,869,412 B2 and U.S. Patent No. 11,462,152 B2 each name an inventive entity different from that of the instant application, and each is assigned on its face to Samsung Display Co., Ltd., the applicant of the instant application.
The patent term filing date of each (10 June 2020, 10 June 2020 and 20 July 2021, respectively) is earlier than that of the instant application (9 February 2022), so that a one-way determination of distinctness applies. See MPEP § 804, subsection II.B.4.
In each rejection below the comparison is with the claims of the patent; the disclosure of the patent is consulted only to construe those claims, and is not applied as prior art. In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970).
Claims 5, 6 and 10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 13 of U.S. Patent No. 11,217,149 B2 (hereinafter the ’149 patent) in view of Chung (US 2022/0101785 A1).
Claim 13 of the ’149 patent depends from claim 12 and, through claims 7, 6 and 5, from claim 1, and includes all of their limitations.
US 2021/0134210 A1 (In), applied in paragraph 13 above, is the pre-grant publication of the application that issued as the ’149 patent.
Regarding instant claim 5, claim 13 of the ’149 patent recites a display apparatus [e.g., Column 20, Line 63: A display device comprising:] comprising:
a display panel having a pixel including a driving switching element and a light emitting element; [e.g., Column 20, Lines 64–65: pixels connected to first scan lines, second scan lines, third scan lines, emission control lines, and data lines; Column 21, Lines 35–38: a first transistor including a first electrode connected to a first node electrically connected to a first power source, and configured to control a driving current based on a voltage of a second node; Column 21, Line 34: a light emitting device]
a gate driver configured to output a gate signal and a bias control signal to the pixel; [e.g., Column 20, Lines 66–67: a first scan driver configured to supply a first scan signal to each of the first scan lines in a first period; Column 21, Lines 4–6: a third scan driver configured to supply a third scan signal to each of the third scan lines in the first period and a second period; Column 21, Lines 47–50: a fourth transistor configured to be turned on in response to the third scan signal; Column 21, Lines 47–50: to supply a bias voltage to the first node]
an emission driver configured to output an emission signal to the pixel; [e.g., Column 21, Lines 7–9: an emission driver configured to supply an emission control signal to the emission control lines in the first period and the second period]
a data driver configured to output a data voltage to the pixel; and [e.g., Column 21, Lines 9–11: a data driver configured to supply a data signal to the data lines in the first period]
a power voltage generator configured to generate a bias voltage, [e.g., Column 22, Lines 28–31: a power supply configured to supply a bias power source corresponding to the bias voltage]
wherein the bias voltage of a holding frame [e.g., Column 22, Lines 32–37: supply the bias power source having a second voltage level different from the first voltage level in the second period]
the power supply is configured to supply the bias power source having a first voltage level in the first period]
wherein the bias voltage of the holding frame is constant in the holding frame at a second level [e.g., Column 22, Lines 32–37: supply the bias power source having a second voltage level different from the first voltage level in the second period]
wherein the bias voltage of the writing frame is constant in the writing frame at the first level [e.g., Column 22, Lines 32–37: the power supply is configured to supply the bias power source having a first voltage level in the first period] (e.g., see claims 1, 5, 6, 7, 12 and 13).
Claim 13 of the ’149 patent does not expressly recite a driving controller configured to determine a driving frequency varied according to input image data or a driving mode, and does not expressly recite that the second voltage level is greater than the first voltage level.
However, claim 13 recites the supply of the data signal in the first period, and the supply of the third scan signal in the first period and in a second period [e.g., Column 21, Lines 9–11: a data driver configured to supply a data signal to the data lines in the first period; Column 21, Lines 4–6: a third scan driver configured to supply a third scan signal to each of the third scan lines in the first period and a second period].
Construed in light of the patent’s disclosure, the first period is the period in which the image data is written and the second period is the period in which the written image is held [e.g., Column 8, Lines 29–33: The first period may be a period in which a data signal corresponding to an image is written to the pixels PX.; Column 9, Lines 1–11: is a period in which an image programmed in the first period is held, the second period may be defined as a holding sub-frame.],
the bias power source has one voltage level throughout each of those periods [e.g., Column 17, Lines 43–49: the power supply 800 may supply the bias power source Vbs having different voltage levels in the first period P1 and the second period P2.; Fig. 7: Vbs, P1, P2], and
a second voltage level different from the first voltage level includes a second voltage level higher than the first [e.g., Column 17, Lines 50–57: in some exemplary embodiments, the second voltage level may be higher than the first voltage level.].
A second voltage level that differs from the first is either higher or lower than it, and the selection of the higher of the two would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, as a choice between two identified and predictable alternatives. KSR, 550 U.S. 398.
Chung discloses a driving controller [e.g., Chung, Paragraph 28: the electroluminescent display device 100 includes a display panel 110 including a plurality of pixels, a gate driver 130 supplying a gate signal to each of the plurality of pixels, and a data driver 140 supplying a data signal to each of the plurality of pixels, and an active control signal generator 150 supplying a light emission signal to each of the plurality of pixels and a timing controller 120.; Paragraph 29: the timing controller 120 controls the gate driver 130, the data driver 140, and the light emission signal generator 150.; Fig. 1: 120]
configured to determine a driving frequency [e.g., Chung, Paragraph 31: the timing controller 120 generates signals related to driving such that the pixels are driven in a variable refresh rate VRR mode or driven to be switchable between a first refresh rate and a second refresh rate.; Paragraph 31: the timing controller 120 simply changes the speed of a clock signal, generates a synchronization signal to generate a horizontal blank or a vertical blank, or drives the gate driver 130 in a mask method, thereby driving the pixel at various refresh rates.]
varied according to input image data or a driving mode [e.g., Chung, Paragraph 9: A refresh rate is changed in units of a frame in accordance with an image.; Paragraph 57: activates pixels by increasing the refresh rate at which the data voltage Vdata is updated when high-speed driving is required, and drives pixels by reducing the refresh rate when it is necessary to reduce power consumption or low-speed driving is required.].
The display device of claim 13 of the ’149 patent and Chung are analogous art, each being directed to a display device in which a bias voltage is applied to the driving transistor of the pixel both in a period in which a data signal is written and in a period in which it is not [e.g., ’149 patent, Column 21, Lines 4–6: a third scan driver configured to supply a third scan signal to each of the third scan lines in the first period and a second period; Column 21, Lines 47–50: to supply a bias voltage to the first node] [e.g., Chung, Paragraph 9: The frame is distinguished into a refresh frame for writing a data voltage and a hold frame for maintaining the data voltage written in the refresh frame.; Paragraph 71: on-bias stress can be defined as an operation to apply directly a suitable bias voltage (for example, V1=V1_H) to the driving transistor DT during non-light emission periods.].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to provide the display device of claim 13 of the ’149 patent with the timing controller of Chung, determining the refresh rate in accordance with the image, so as to increase the refresh rate when high-speed driving is required and to reduce the refresh rate when power consumption is to be reduced [e.g., Chung, Paragraph 57: activates pixels by increasing the refresh rate at which the data voltage Vdata is updated when high-speed driving is required, and drives pixels by reducing the refresh rate when it is necessary to reduce power consumption or low-speed driving is required.]. KSR, 550 U.S. 398.
Regarding instant claim 6, the claim recites wherein when the driving frequency is a first driving frequency, the display panel only has the writing frame, and
wherein when the driving frequency is a second driving frequency less than the first driving frequency, the display panel has the writing frame and the holding frame.
Claim 13 of the ’149 patent does not expressly recite a first driving frequency at which the display device has the first period only, or a lower second driving frequency at which it has the first period and the second period.
Chung discloses wherein when the driving frequency is a first driving frequency, the display panel only has the writing frame [e.g., Chung, Paragraph 59: When the pixel is driven at the refresh rate of 120 Hz, the pixel can be driven only by the refresh frame.], and
wherein when the driving frequency is a second driving frequency less than the first driving frequency, the display panel has the writing frame and the holding frame [e.g., Chung, Paragraph 60: When the pixel is driven at the refresh rate of 60 Hz, the refresh frame and the hold frame may be alternately driven.; Fig. 5: Refresh, Hold].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to drive the display device of claim 13 of the ’149 patent with the first period alone at a first and highest refresh rate, and with the first period and the second period at a lower refresh rate, as taught by Chung, so that the data voltage is updated in every period when high-speed driving is required and the refresh rate is reduced when power consumption is to be reduced [e.g., Chung, Paragraph 57: activates pixels by increasing the refresh rate at which the data voltage Vdata is updated when high-speed driving is required, and drives pixels by reducing the refresh rate when it is necessary to reduce power consumption or low-speed driving is required.]. KSR, 550 U.S. 398.
Regarding instant claim 10, claim 13 of the ’149 patent recites wherein a width of the bias control signal to apply the bias voltage to the driving switching element in the writing frame [e.g., Column 21, Lines 47–50: a fourth transistor configured to be turned on in response to the third scan signal; Column 21, Lines 47–50: to supply a bias voltage to the first node]
a third scan driver configured to supply a third scan signal to each of the third scan lines in the first period and a second period].
Claim 13 of the ’149 patent does not expressly recite that the width of the third scan signal in the first period is equal to its width in the second period.
Chung discloses wherein a width of the bias control signal to apply the bias voltage to the driving switching element [e.g., Chung, Paragraph 54: The fifth transistor T5 includes the first electrode which is connected to the third node N3, the second electrode which receives the first bias voltage V1, and the gate electrode which receives a second scan signal SC2.; Paragraph 70: the low second scan signal SC2 is input, and the fifth and sixth transistors T5 and T6 are turned on.; Fig. 3B: SC2(n), T5, DT] in the writing frame
is equal to a width of the bias control signal in the holding frame [e.g., Chung, Paragraph 91: for convenience of the driving circuit, the second scan signal SC2 is driven in the same manner as the second scan signal SC2 of the refresh frame; Fig. 4A: SC2(n)].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to supply the third scan signal of claim 13 of the ’149 patent in the second period in the same manner as in the first period, as taught by Chung, for the convenience of the driving circuit [e.g., Chung, Paragraph 91: for convenience of the driving circuit, the second scan signal SC2 is driven in the same manner as the second scan signal SC2 of the refresh frame]. KSR, 550 U.S. 398.
Claims 5, 6 and 10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 14 of U.S. Patent No. 11,869,412 B2 (hereinafter the ’412 patent) in view of Chung (US 2022/0101785 A1).
Claim 14 of the ’412 patent depends from claim 13 and, through claim 2, from claim 1, and includes all of their limitations.
The ’412 patent issued from a continuation of the application that issued as the ’149 patent.
Regarding instant claim 5, claim 14 of the ’412 patent recites a display apparatus [e.g., Column 20, Line 64: A display device comprising:] comprising:
a display panel having a pixel [e.g., Column 20, Lines 65–67: a pixel connected to a first scan line, a second scan line, a third scan line, an emission control line, and a data line]
a gate driver configured to output a gate signal and a bias control signal to the pixel; [e.g., Column 21, Lines 1–2: a first scan driver configured to supply a first scan signal to the first scan line in a first period; Column 21, Lines 5–7: a third scan driver configured to supply a third scan signal to the third scan line in the first period and a second period]
an emission driver configured to output an emission signal to the pixel; [e.g., Column 21, Lines 8–10: an emission driver configured to supply an emission control signal to the emission control line in the first period and the second period]
a data driver configured to output a data voltage to the pixel; and [e.g., Column 21, Lines 10–12: a data driver configured to supply a data signal to the data line in the first period]
a power voltage generator configured to generate a bias voltage, [e.g., Column 22, Lines 38–40: a power supply configured to supply a bias power source corresponding to a bias voltage to the pixel]
wherein the bias voltage of a holding frame [e.g., Column 22, Lines 41–45: supply the bias power source having a second voltage level different from the first voltage level in the second period]
the power supply is configured to supply the bias power source having a first voltage level in the first period]
wherein the bias voltage of the holding frame is constant in the holding frame at a second level [e.g., Column 22, Lines 41–45: supply the bias power source having a second voltage level different from the first voltage level in the second period]
wherein the bias voltage of the writing frame is constant in the writing frame at the first level [e.g., Column 22, Lines 41–45: the power supply is configured to supply the bias power source having a first voltage level in the first period] (e.g., see claims 1, 2, 13 and 14).
Claim 14 of the ’412 patent does not expressly recite that the pixel includes a driving switching element and a light emitting element, does not expressly recite a driving controller configured to determine a driving frequency varied according to input image data or a driving mode, and does not expressly recite that the second voltage level is greater than the first voltage level.
However, claim 14 recites the supply of the data signal in the first period, and the supply of the third scan signal in the first period and in a second period [e.g., Column 21, Lines 10–12: a data driver configured to supply a data signal to the data line in the first period; Column 21, Lines 5–7: a third scan driver configured to supply a third scan signal to the third scan line in the first period and a second period].
Construed in light of the patent’s disclosure, the first period is the period in which the image data is written, and the second period is the period in which the written image is held and in which the bias is applied to the pixel by the third scan signal [e.g., Column 8, Lines 29–33: The first period may be a period in which a data signal corresponding to an image is written to the pixels PX.; Column 9, Lines 1–11: The second period may be a bias period in which a bias is applied to the pixels PX by the third scan signal.; Column 9, Lines 1–11: is a period in which an image programmed in the first period is held, the second period may be defined as a holding sub-frame.],
the bias power source has one voltage level throughout each of those periods [e.g., Column 17, Lines 44–50: the power supply 800 may supply the bias power source Vbs having different voltage levels in the first period P1 and the second period P2.; Fig. 7: Vbs, P1, P2], and
a second voltage level different from the first voltage level includes a second voltage level higher than the first [e.g., Column 17, Lines 51–58: in some exemplary embodiments, the second voltage level may be higher than the first voltage level.].
A second voltage level that differs from the first is either higher or lower than it, and the selection of the higher of the two would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, as a choice between two identified and predictable alternatives. KSR, 550 U.S. 398.
Chung discloses a pixel including a driving switching element and a light emitting element [e.g., Chung, Paragraph 36: each of the pixels includes an electroluminescent device and a pixel driving circuit that controls the driving of the electroluminescent device.; Paragraph 36: a driving TFT controls the amount of current supplied to the electroluminescent device].
Chung discloses a driving controller [e.g., Chung, Paragraph 28: the electroluminescent display device 100 includes a display panel 110 including a plurality of pixels, a gate driver 130 supplying a gate signal to each of the plurality of pixels, and a data driver 140 supplying a data signal to each of the plurality of pixels, and an active control signal generator 150 supplying a light emission signal to each of the plurality of pixels and a timing controller 120.; Paragraph 29: the timing controller 120 controls the gate driver 130, the data driver 140, and the light emission signal generator 150.; Fig. 1: 120]
configured to determine a driving frequency [e.g., Chung, Paragraph 31: the timing controller 120 generates signals related to driving such that the pixels are driven in a variable refresh rate VRR mode or driven to be switchable between a first refresh rate and a second refresh rate.; Paragraph 31: the timing controller 120 simply changes the speed of a clock signal, generates a synchronization signal to generate a horizontal blank or a vertical blank, or drives the gate driver 130 in a mask method, thereby driving the pixel at various refresh rates.]
varied according to input image data or a driving mode [e.g., Chung, Paragraph 9: A refresh rate is changed in units of a frame in accordance with an image.; Paragraph 57: activates pixels by increasing the refresh rate at which the data voltage Vdata is updated when high-speed driving is required, and drives pixels by reducing the refresh rate when it is necessary to reduce power consumption or low-speed driving is required.].
The display device of claim 14 of the ’412 patent and Chung are analogous art, each being directed to a display device in which a bias voltage is supplied to the pixel both in a period in which a data signal is written and in a period in which it is not [e.g., ’412 patent, Column 21, Lines 5–7: a third scan driver configured to supply a third scan signal to the third scan line in the first period and a second period; Column 22, Lines 38–40: a power supply configured to supply a bias power source corresponding to a bias voltage to the pixel] [e.g., Chung, Paragraph 9: The frame is distinguished into a refresh frame for writing a data voltage and a hold frame for maintaining the data voltage written in the refresh frame.; Paragraph 71: on-bias stress can be defined as an operation to apply directly a suitable bias voltage (for example, V1=V1_H) to the driving transistor DT during non-light emission periods.].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the pixel of claim 14 of the ’412 patent with the driving transistor and the electroluminescent device of Chung,
so that the current supplied to the electroluminescent device, and with it the light emitted by the pixel, is controlled in accordance with the data voltage [e.g., Chung, Paragraph 36: a driving TFT controls the amount of current supplied to the electroluminescent device]; and
to provide the display device with the timing controller of Chung, determining the refresh rate in accordance with the image, so as to increase the refresh rate when high-speed driving is required and to reduce the refresh rate when power consumption is to be reduced [e.g., Chung, Paragraph 57: activates pixels by increasing the refresh rate at which the data voltage Vdata is updated when high-speed driving is required, and drives pixels by reducing the refresh rate when it is necessary to reduce power consumption or low-speed driving is required.]. KSR, 550 U.S. 398.
Regarding instant claim 6, claim 14 of the ’412 patent recites wherein when the driving frequency is a first driving frequency, the display panel only has the writing frame, and [e.g., Column 21, Lines 19–20: the first period is configured to be repeated when an image refresh rate is a first frequency]
wherein when the driving frequency is a second driving frequency less than the first driving frequency, the display panel has the writing frame and the holding frame [e.g., Column 21, Lines 20–23: the second period is configured to be activated at least once just after the first period when the image refresh rate is less than the first frequency].
Construed in light of the patent’s disclosure, the first period alone is repeated when the image refresh rate is the first frequency [e.g., Column 9, Lines 44–46: only the first period may be repeated.].
Regarding instant claim 10, the claim recites wherein a width of the bias control signal to apply the bias voltage to the driving switching element in the writing frame is equal to a width of the bias control signal in the holding frame.
Claim 14 of the ’412 patent does not expressly recite the width of the third scan signal in the first period or in the second period.
Chung discloses wherein a width of the bias control signal to apply the bias voltage to the driving switching element [e.g., Chung, Paragraph 54: The fifth transistor T5 includes the first electrode which is connected to the third node N3, the second electrode which receives the first bias voltage V1, and the gate electrode which receives a second scan signal SC2.; Paragraph 70: the low second scan signal SC2 is input, and the fifth and sixth transistors T5 and T6 are turned on.; Fig. 3B: SC2(n), T5, DT] in the writing frame
is equal to a width of the bias control signal in the holding frame [e.g., Chung, Paragraph 91: for convenience of the driving circuit, the second scan signal SC2 is driven in the same manner as the second scan signal SC2 of the refresh frame; Fig. 4A: SC2(n)].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to supply the third scan signal of claim 14 of the ’412 patent, by which the bias is applied in each period, in the second period in the same manner as in the first period, as taught by Chung, for the convenience of the driving circuit [e.g., Chung, Paragraph 91: for convenience of the driving circuit, the second scan signal SC2 is driven in the same manner as the second scan signal SC2 of the refresh frame]. KSR, 550 U.S. 398.
Claims 5, 6 and 10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 14 of U.S. Patent No. 11,462,152 B2 (hereinafter the ’152 patent) in view of Chung (US 2022/0101785 A1).
Claim 14 of the ’152 patent depends from claim 13 and, through claim 12, from claim 11, and includes all of their limitations.
Regarding instant claim 5, claim 14 of the ’152 patent recites a display apparatus [e.g., Column 28, Line 5: A display device comprising:] comprising:
a display panel having a pixel including a driving switching element and a light emitting element; [e.g., Column 28, Lines 6–10: a pixel including a first transistor connected between a first node and a second node to generate a driving current; Column 28, Lines 32–33: a light emitting element]
a driving controller [e.g., Column 28, Lines 21–24: a timing controller which controls driving of the scan driver, the emission driver, the data driver, and the power supply]
a gate driver configured to output a gate signal and a bias control signal to the pixel; [e.g., Column 28, Lines 14–16: a scan driver which supplies first to fourth scan signals to the first to fourth scan lines, respectively, in a period in which the emission control signal is supplied; Column 28, Lines 34–36: a second transistor connected between the data line and the first node, and which is turned on in response to the fourth scan signal; Column 28, Lines 25–27: the first scan signal controls a timing at which the voltage of the first power source is supplied to the first node or the second node]
an emission driver configured to output an emission signal to the pixel; [e.g., Column 28, Lines 11–13: an emission driver which supplies an emission control signal to the emission control line]
a data driver configured to output a data voltage to the pixel; and [e.g., Column 28, Line 17: a data driver which supplies a data signal to the data line]
a power voltage generator configured to generate a bias voltage, [e.g., Column 28, Lines 18–21: a power supply which supplies, to the pixel, a voltage of a driving power source, a voltage of a first power source, a voltage of a second power source, and a voltage of a third power source; Column 28, Lines 41–43: a fourth transistor which is turned on in response to the first scan signal to apply the voltage of the first power source to the first transistor]
wherein the bias voltage of a holding frame [e.g., Column 28, Lines 61–63: in the at least one bias scan period, the scan driver supplies the first scan signal through the first scan line, and does not supply the fourth scan signal; Column 28, Line 67 – Column 29, Line 3: supplies the voltage of the first power source having a second voltage level different from the first voltage level in the at least one bias scan period]
in the display scan period, the scan driver supplies the first scan signal through the first scan line, and supplies the fourth scan signal through the fourth scan line; Column 28, Lines 66–67: supplies the voltage of the first power source having a first voltage level in the display scan period]
wherein the bias voltage of the holding frame is constant in the holding frame at a second level [e.g., Column 28, Line 67 – Column 29, Line 3: supplies the voltage of the first power source having a second voltage level different from the first voltage level in the at least one bias scan period]
wherein the bias voltage of the writing frame is constant in the writing frame at the first level [e.g., Column 28, Lines 66–67: supplies the voltage of the first power source having a first voltage level in the display scan period] (e.g., see claims 11, 12, 13 and 14).
Claim 14 of the ’152 patent does not expressly recite that the timing controller is configured to determine a driving frequency varied according to input image data or a driving mode, and does not expressly recite that the second voltage level is greater than the first voltage level.
However, construed in light of the patent’s disclosure, the first power source has one voltage level throughout the display scan period and one voltage level throughout each bias scan period, and a second voltage level different from the first voltage level includes a second voltage level higher than the first [e.g., Column 18, Lines 15–21: the first power source VEH may have a first voltage level VE1 in a display scan period DSP, and have a second voltage level VE2 in at least one bias scan period BSP1 and BSP2.; Column 18, Lines 15–21: The second voltage level VE2 may be higher than the first voltage level VE1.; Fig. 6A: VEH, VE1, VE2, DSP, BSP1, BSP2].
A second voltage level that differs from the first is either higher or lower than it, and the selection of the higher of the two would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, as a choice between two identified and predictable alternatives. KSR, 550 U.S. 398.
Chung discloses a driving controller [e.g., Chung, Paragraph 29: the timing controller 120 controls the gate driver 130, the data driver 140, and the light emission signal generator 150.; Fig. 1: 120]
configured to determine a driving frequency [e.g., Chung, Paragraph 31: the timing controller 120 generates signals related to driving such that the pixels are driven in a variable refresh rate VRR mode or driven to be switchable between a first refresh rate and a second refresh rate.; Paragraph 31: the timing controller 120 simply changes the speed of a clock signal, generates a synchronization signal to generate a horizontal blank or a vertical blank, or drives the gate driver 130 in a mask method, thereby driving the pixel at various refresh rates.]
varied according to input image data or a driving mode [e.g., Chung, Paragraph 9: A refresh rate is changed in units of a frame in accordance with an image.; Paragraph 57: activates pixels by increasing the refresh rate at which the data voltage Vdata is updated when high-speed driving is required, and drives pixels by reducing the refresh rate when it is necessary to reduce power consumption or low-speed driving is required.].
The display device of claim 14 of the ’152 patent and Chung are analogous art, each being directed to a display device in which a bias voltage is applied to the driving transistor of the pixel both in a period in which a data signal is written and in a period in which it is not [e.g., ’152 patent, Column 28, Lines 41–43: a fourth transistor which is turned on in response to the first scan signal to apply the voltage of the first power source to the first transistor; Column 28, Lines 61–63: in the at least one bias scan period, the scan driver supplies the first scan signal through the first scan line, and does not supply the fourth scan signal] [e.g., Chung, Paragraph 9: The frame is distinguished into a refresh frame for writing a data voltage and a hold frame for maintaining the data voltage written in the refresh frame.; Paragraph 71: on-bias stress can be defined as an operation to apply directly a suitable bias voltage (for example, V1=V1_H) to the driving transistor DT during non-light emission periods.].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the timing controller of claim 14 of the ’152 patent determine the refresh rate in accordance with the image, as taught by Chung, so as to increase the refresh rate when high-speed driving is required and to reduce the refresh rate when power consumption is to be reduced [e.g., Chung, Paragraph 57: activates pixels by increasing the refresh rate at which the data voltage Vdata is updated when high-speed driving is required, and drives pixels by reducing the refresh rate when it is necessary to reduce power consumption or low-speed driving is required.]. KSR, 550 U.S. 398.
Regarding instant claim 6, the claim recites wherein when the driving frequency is a first driving frequency, the display panel only has the writing frame, and
wherein when the driving frequency is a second driving frequency less than the first driving frequency, the display panel has the writing frame and the holding frame.
Claim 14 of the ’152 patent does not expressly recite a first driving frequency at which the display device has the display scan period only, or a lower second driving frequency at which it has the display scan period and the bias scan period.
Chung discloses wherein when the driving frequency is a first driving frequency, the display panel only has the writing frame [e.g., Chung, Paragraph 59: When the pixel is driven at the refresh rate of 120 Hz, the pixel can be driven only by the refresh frame.], and
wherein when the driving frequency is a second driving frequency less than the first driving frequency, the display panel has the writing frame and the holding frame [e.g., Chung, Paragraph 60: When the pixel is driven at the refresh rate of 60 Hz, the refresh frame and the hold frame may be alternately driven.; Fig. 5: Refresh, Hold].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to drive the display device of claim 14 of the ’152 patent with the display scan period alone at a first and highest refresh rate, and with the display scan period and at least one bias scan period at a lower refresh rate, as taught by Chung, so that the data voltage is updated in every period when high-speed driving is required and the refresh rate is reduced when power consumption is to be reduced [e.g., Chung, Paragraph 57: activates pixels by increasing the refresh rate at which the data voltage Vdata is updated when high-speed driving is required, and drives pixels by reducing the refresh rate when it is necessary to reduce power consumption or low-speed driving is required.]. KSR, 550 U.S. 398.
Regarding instant claim 10, claim 14 of the ’152 patent recites wherein a width of the bias control signal to apply the bias voltage to the driving switching element in the writing frame [e.g., Column 28, Lines 41–43: a fourth transistor which is turned on in response to the first scan signal to apply the voltage of the first power source to the first transistor; Column 28, Lines 57–60: in the display scan period, the scan driver supplies the first scan signal through the first scan line, and supplies the fourth scan signal through the fourth scan line]
in the at least one bias scan period, the scan driver supplies the first scan signal through the first scan line, and does not supply the fourth scan signal].
Claim 14 of the ’152 patent does not expressly recite that the width of the first scan signal in the display scan period is equal to its width in the bias scan period.
Chung discloses wherein a width of the bias control signal to apply the bias voltage to the driving switching element [e.g., Chung, Paragraph 54: The fifth transistor T5 includes the first electrode which is connected to the third node N3, the second electrode which receives the first bias voltage V1, and the gate electrode which receives a second scan signal SC2.; Paragraph 70: the low second scan signal SC2 is input, and the fifth and sixth transistors T5 and T6 are turned on.; Fig. 3B: SC2(n), T5, DT] in the writing frame
is equal to a width of the bias control signal in the holding frame [e.g., Chung, Paragraph 91: for convenience of the driving circuit, the second scan signal SC2 is driven in the same manner as the second scan signal SC2 of the refresh frame; Fig. 4A: SC2(n)].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to supply the first scan signal of claim 14 of the ’152 patent in the bias scan period in the same manner as in the display scan period, as taught by Chung, for the convenience of the driving circuit [e.g., Chung, Paragraph 91: for convenience of the driving circuit, the second scan signal SC2 is driven in the same manner as the second scan signal SC2 of the refresh frame]. KSR, 550 U.S. 398.
Response to Arguments
The rejection of claim 6 under 35 U.S.C. 112(b) set forth in the Office action mailed 14 July 2026 is withdrawn in view of the amendment to the claims filed 10 September 2026.
Applicant’s arguments filed 10 September 2026 have been fully considered but they are not persuasive.
Applicant states that dependent claims 6 and 10 are novel and patentable over Chung on their own merits (Remarks, page 10).
Applicant’s arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
The teachings of Chung that are applied to the subject matter of claims 6 and 10 in this action are set out in paragraphs 12, 14, 15 and 17–19 above.
Applicant’s arguments with respect to claims 5, 6 and 10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The arguments so answered are those directed to the voltage V1 of Chung (Remarks, pages 8–10); the statement concerning dependent claims 6 and 10 is answered in paragraph 21 above.
Conclusion
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/Jeff Piziali/
Primary Examiner, Art Unit 2628
4 October 2026
